MC68HC812A4CPV8 Freescale Semiconductor, Inc, MC68HC812A4CPV8 Datasheet
MC68HC812A4CPV8
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MC68HC812A4CPV8 Summary of contents
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MC68HC812A4 Data Sheet M68HC12 Microcontrollers MC68HC812A4 Rev. 7 05/2006 freescale.com ...
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...
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... Figure 11-1. PLL Block Diagram — Revised diagram to show correct placement of divide-by-two block 12.11.2 Timer Port Data Direction Register — Descriptive paragraph added for clarity Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved. Freescale Semiconductor Description MC68HC812A4 Data Sheet, Rev ...
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Revision History Revision History Revision Date Level 12.11.3 Data Direction Register for Timer Port — Repetitive information removed. See 12.11.2 Timer Port Data Direction Register August, 18.12 Control Timing — Minimum values added for PW 2001 4 (Continued) 18.14 Non-Multiplexed ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters 6 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 16 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 1 General Description 1.1 Introduction The MC68HC812A4 microcontroller unit (MCU 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include: • 16-bit central processor unit (CPU12) • Lite integration module (LIM) • ...
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... Operating temperature range and voltage requirements are specified when ordering the MC68HC812A4 device. Refer to Table 1-1 for part numbers and to Order Number MC68HC812A4CPV8 XC68HC812A4PV5 FAMILY Evaluation boards, assemblers, compilers, and debuggers are available from Freescale and from third-party suppliers. An up-to-date list of products that support the M68HC12 Family of microcontrollers can be found on the World Wide Web at this URL: http://freescale ...
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Block Diagram BKGD/TAGHI SINGLE-WIRE BACKGROUND RESET DEBUG MODULE EXTAL XTAL XFC PLL CLOCK CONTROL V DDPLL V SSPLL PE7 ARST PE6 IPIPE1/MODB PE5 IPIPE0/MODA PE4 ECLK PE3 LSTRB/TAGLO PE2 R/W PE1 IRQ/V PP PE0 XIRQ PJ7 KWJ7 PJ6 KWJ6 ...
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General Description 1.5 Signal Descriptions A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. The MC68HC812A4 is available in a 112-lead low-profile quad flat pack (LQFP). The ...
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Pin Port — Operating voltage and ground for the MCU — Reference voltages for the ADC — Operating voltage and ground for the ADC ...
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General Description Pin Port RxD1 PS2 Receive pin for SCI1 TxD1 PS3 Transmit pin for SCI1 SDI/MISO PS4 Master in/slave out pin for SPI SDO/MOSI PS5 Master out/slave in pin for SPI SCK PS6 Serial clock for SPI SS PS7 ...
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Table 1-4. Port Pullup, Pulldown, and Reduced Drive Summary Port Resistive Name Input Loads Port A Pullup Port B Pullup Port C Pullup Port D Pullup Port E: PE7, PE3, Pullup PE2, PE0 Port E: Pullup PE1 Port E: None ...
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General Description Ω 4 DIP Ω 4 RESET A4_RESET HEADER 6 1 RSET U2 MC34064 3 ...
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A[0. . 21] PF6/CSP1 PF[ PE[ Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet A[0. . 21] RESET V CC Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet ...
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General Description Ω 4 DIP Ω 4 A4_RESET VSS VDD HEADER 6 1 RSET U2 MC34064 3 GND IN 2 ...
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A[0. . 21] PF[ PE[ Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet D[0. . 15] A[0. . 21] PF[ Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet 3 ...
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General Description 28 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 2 Register Block 2.1 Overview The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG15–REG11 in the INITRG register. INITRG establishes the upper five bits of the register block’s ...
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Register Block Addr. Register Name Read: Port D Data Direction $0007 Register (DDRD) Write: See page 67. Reset: Read: Port E Data Register $0008 (PORTE) Write: See page 68. Reset: Read: Port E Data Direction $0009 Register (DDRE) Write: See ...
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Addr. Register Name Read: Real-Tme Interrupt Control $0014 Register (RTICTL) Write: See page 105. Reset: Real-Time Interrupt Flag Read: Register (RTIFLG) Write: $0015 See page 107. Reset: COP Control Register Read: (COPCTL) Write: $0016 See page 107. Reset: Read: Arm/Reset ...
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Register Block Addr. Register Name Read: Port H Key Wakeup $0026 Interrupt Enable Register Write: (KWIEH) See page 96. Reset: Read: Port H Key Wakeup Flag $0027 Register (KWIFH) Write: See page 96. Reset: Read: Port J Data Register $0028 ...
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Addr. Register Name Read: Port G Data Direction $0033 Register (DDRG) Write: See page 86. Reset: Read: Data Page Register $0034 (DPAGE) Write: See page 86. Reset: Read: Program Page Register $0035 (PPAGE) Write: See page 87. Reset: Read: Extra ...
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Register Block Addr. Register Name Read: Loop Divider Register Low $0041 (LDVL) Write: See page 113. Reset: Read: Reference Divider $0042 Register High (RDVH) Write: See page 114. Reset: Read: Reference Divider $0043 Register Low (RDVL) Write: See page 114. ...
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Addr. Register Name Read: ATD Status Register 1 $0066 (ATDSTAT1) Write: See page 204. Reset: Read: ATD Status Register 2 $0067 (ATDSTAT2) Write: See page 204. Reset: Read: ATD Test Register 1 $0068 (ATDTEST1) Write: See page 205. Reset: Read: ...
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Register Block Addr. Register Name Read: ATD Result Register 4 $0078 (ADR4H) Write: See page 206. Reset: $0079 Reserved Read: ATD Result Register 5 $007A (ADR5H) Write: See page 206. Reset: $007B Reserved Read: ATD Result Register 6 $007C (ADR6H) ...
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Addr. Register Name Read: Timer System Control $0086 Register (TSCR) Write: See page 127. Reset: $0087 Reserved Read: Timer Control $0088 Register 1 (TCTL1) Write: See page 129. Reset: Read: Timer Control $0089 Register 2 (TCTL2) Write: See page 129. ...
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Register Block Addr. Register Name Read: Timer Channel 1 Register $0093 Low (TC1L) Write: See page 133. Reset: Read: Timer Channel 2 Register $0094 High (TC2H) Write: See page 133. Reset: Read: Timer Channel 2 Register $0095 Low (TC2L) Write: ...
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Addr. Register Name Read: Timer Channel 7 Register $009F Low (TC7L) Write: See page 133. Reset: Read: Pulse Accumulator Control $00A0 Register (PACTL) Write: See page 134. Reset: Read: Pulse Accumulator Flag $00A1 Register (PAFLG) Write: See page 135. Reset: ...
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Register Block Addr. Register Name Read: SCI 0 Control $00C2 Register 1 (SC0CR1) Write: See page 169. Reset: Read: SCI 0 Control $00C3 Register 2 (SC0CR2) Write: See page 171. Reset: Read: SCI 0 Status $00C4 Register 1 (SC0SR1) Write: ...
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Addr. Register Name Read: SCI 1 Data Register High $00CE (SC1DRH) Write: See page 174. Reset: Read: SCI 1 Data Register Low $00CF (SC1DRL) Write: See page 174. Reset: Read: SPI 0 Control Register 1 $00D0 (SP0CR1) Write: See page ...
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Register Block Addr. Register Name Read: EEPROM Test Register $00F2 (EETST) Write: See page 75. Reset: Read: EEPROM Programming $00F3 Register (EEPROG) Write: See page 76. Reset: $00F4 Reserved ↓ ↓ $01FF Reserved Figure 2-1. Register Map (Sheet 14 of ...
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Chapter 3 Central Processor Unit (CPU12) 3.1 Overview The CPU12 is a high-speed, 16-bit processor unit. It has full 16-bit data paths and wider internal registers ( bits) for high-speed extended math instructions. The instruction set is a ...
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Central Processor Unit (CPU12) 3.3 CPU Registers This section describes the CPU registers. 3.3.1 Accumulators A and B Accumulators A and B are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. Bit 7 A7 ...
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Index Registers X and Y Index registers X and Y are used for indexed addressing. Indexed addressing adds the value in an index register to a constant or to the value in an accumulator to form the effective address ...
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Central Processor Unit (CPU12) 3.3.6 Condition Code Register Bit 7 S Reset Unaffected Figure 3-9. Condition Code Register (CCR) S — Stop Disable Bit Setting the S bit disables the STOP instruction. X — XIRQ Interrupt Mask ...
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Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 3-1 is ...
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Central Processor Unit (CPU12) 3.6 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after ...
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Chapter 4 Resets and Interrupts 4.1 Introduction Resets and interrupts are exceptions. Each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard ...
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Resets and Interrupts Vector Exception Source Address $FFFE, $FFFF Power-on reset $FFFC, $FFFD Clock monitor reset $FFFA, $FFFB COP reset $FFF8, $FFF9 Unimplemented instruction trap $FFF6, $FFF7 SWI instruction $FFF4, $FFF5 XIRQ pin $FFF2, $FFF3 IRQ pin or key wakeup ...
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Interrupt Registers This section describes the interrupt registers. 4.4.1 Interrupt Control Register Address: $001E Bit 7 Read: IRQE Write: Reset Unimplemented Figure 4-1. Interrupt Control Register (INTCR) Read: Anytime Write: Varies from bit to bit IRQE — ...
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Resets and Interrupts interrupt timer ($FFF0 unimplemented vector address or a non-I-masked vector address (a value higher than $F2) is written, then IRQ is the default highest priority interrupt. 4.5 Resets There are five possible sources of reset: ...
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Effects of Reset When a reset occurs, MCU registers and control bits are changed to known startup states, as follows. 4.6.1 Operating Mode and Memory Map The states of the BGND, MODA, and MODB pins during reset determine the ...
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Resets and Interrupts 4.7 Interrupt Recognition Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared. When an interrupt request is recognized, the CPU responds at the completion of the ...
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Chapter 5 Operating Modes and Resource Mapping 5.1 Introduction The MCU can operate in eight different modes. Each mode has a different default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses ...
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Operating Modes and Resource Mapping 5.2.1.1 Normal Expanded Wide Mode The 16-bit external address bus uses port A for the high byte and port B for the low byte. The 16-bit external data bus uses port C for the high ...
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CPU is operating normally. Other BDM commands are firmware based and require the BDM firmware to be enabled and active for execution. In special single-chip mode, BDM is enabled and active immediately out of ...
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Operating Modes and Resource Mapping 5.4 Mode and Resource Mapping Registers This section describes the mode and resource mapping registers. 5.4.1 Mode Register MODE controls the MCU operating mode and various configuration options. This register is not in the map ...
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Normal modes: Write once Special modes: Write anytime except the first time EMD — Emulate Port D Bit This bit only has meaning in special expanded narrow mode. In expanded wide modes and special peripheral mode, PORTD, DDRD, KWIED, and ...
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Operating Modes and Resource Mapping 5.4.3 RAM Initialization Register After reset, addresses of the 1-Kbyte RAM array begin at location $0800 but can be assigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal RAM is ...
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Miscellaneous Mapping Control Register Additional mapping controls are available that can be used in conjunction with memory expansion and chip selects. To use memory expansion, the part must be operated in one of the expanded modes. Sections of the ...
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Operating Modes and Resource Mapping 5.5 Memory Map Figure 5-6 illustrates the memory map for each mode of operation immediately after reset. $0000 EXT $0800 EXT $1000 $2000 EXT $F000 $FF00 $FFC0 VECTORS VECTORS $FFFF EXPANDED SINGLE-CHIP NORMAL 62 $0000 ...
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Chapter 6 Bus Control and Input/Output (I/O) 6.1 Introduction Internally the MCU has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may bits. There are cases where 8-bit ...
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Bus Control and Input/Output (I/O) Port D and its associated data direction register may be removed from the on-chip map when port D is needed for 16-bit data transfers. If the MCU expanded wide mode, port C ...
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Port B Data Register Address: $0001 Bit 7 Read: PB7 Write: Reset: 0 Expanded and peripheral: ADDR7 Figure 6-3. Port B Data Register (PORTB) Read: Anytime, if register is in the map Write: Anytime, if register is in the ...
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Bus Control and Input/Output (I/O) 6.3.5 Port C Data Register Address: $0004 Bit 7 Read: PC7 Write: Reset: Expanded wide and peripheral: DATA15 Expanded narrow: DATA15/7 DATA14/6 DATA13/5 DATA12/4 DATA11/3 DATA10/2 Figure 6-5. Port C Data Register (PORTC) Read: Anytime, ...
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Port D Data Register Address: $0005 Bit 7 Read: PD7 Write: Reset: Expanded wide and peripheral: DATA7 Alternate pin function: KWD7 Figure 6-7. Port D Data Register (PORTD) Read: Anytime, if register is in the map Write: Anytime, if ...
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Bus Control and Input/Output (I/O) 6.3.9 Port E Data Register Address: $0008 Bit 7 Read: PE7 Write: Reset: Normal narrow expanded: 0 All other modes: 0 Alternate pin function: ARST Figure 6-9. Port E Data Register (PORTE) Read: Anytime, if ...
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Port E Assignment Register Address: $000A Bit 7 Read: ARSIE Write: Reset: Special single-chip: 0 Special expanded narrow: 0 Peripheral: 0 Special expanded wide: 0 Normal single-chip 0 Normal expanded narrow: 0 Normal expanded wide: 0 Figure 6-11. Port ...
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Bus Control and Input/Output (I/O) PIPOE — Pipe Status Signal Output Enable Bit Normal modes: Write once Special modes: Write anytime except the first time 1 = PE6 and PE5 are outputs and indicate the state of the instruction queue; ...
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Pullup Control Register Address: $000C Bit 7 Read: PUPH Write: Reset: 1 Figure 6-12. Pullup Control Register (PUCR) Read: Anytime, if register is in the map Write: Anytime, if register is in the map This register is not in ...
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Bus Control and Input/Output (I/O) 6.3.13 Reduced Drive Register Address: $000D Bit 7 6 Read: RDPJ Write: Reset: 0 Figure 6-13. Reduced Drive Register (RDRIV) Read: Anytime, if register is in the map Write: Anytime, in normal modes; never in ...
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Chapter 7 EEPROM 7.1 Introduction The MC68HC812A4 EEPROM (electrically erasable, programmable, read-only memory) serves as a 4096-byte nonvolatile memory which can be used for frequently accessed static data or as fast access program code. Operating system kernels and standard subroutines ...
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EEPROM $_000 $_800 $_C00 $_E00 $_F00 $_F80 $_FC0 $_FFF Figure 7-1. EEPROM Block Protect Mapping 7.3 EEPROM Control Registers This section describes the EEPROM control registers. 7.3.1 EEPROM Module Configuration Register Address: $00F0 Bit 7 Read: 1 Write: Reset: 1 ...
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EEPROM Block Protect Register Address: $00F1 Bit 7 Read: 1 BPROT6 Write: Reset: 1 Figure 7-3. EEPROM Block Protect Register (EEPROT) Read: Anytime Write: Anytime if EEPGM = 0 and PROTLCK = 0 This register prevents accidental writes to ...
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EEPROM EEVEN — Even Row Programming Bit 1 = Bulk program/erase all even rows 0 = Even row bulk programming/erasing disabled MARG — Program and Erase Voltage Margin Test Enable Bit 1 = Program and erase margin test 0 = ...
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Byte ERASE — Erase Control Bit 1 = EEPROM configuration for erasure 0 = EEPROM configuration for programming Write anytime, if EEPGM = 0 This bit configures the EEPROM for erasure or programming. EELAT — EEPROM ...
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EEPROM 78 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 8 Memory Expansion and Chip-Select 8.1 Introduction To use memory expansion, the MCU must be operated in one of the expanded modes. Sections of the standard 64-Kbyte address space have memory expansion windows which allow an external address space ...
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Memory Expansion and Chip-Select Table 8-1. Memory Expansion Values Internal A21 A20 Address $0800–$6FFF 1 1 $7000–$7FFF 1 1 PDA19 PDA18 PDA17 PDA16 PDA15 PDA14 PDA13 PDA12 DWEN = 1 $7000–$7FFF 1 1 DWEN = 0 $8000–$BFFF PPA21 PPA20 PPA19 ...
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CS3 can be used with a 1-Kbyte space in systems not using memory expansion. However, it must be made to appear as if memory expansion is in use. One of many possible configurations is: • Select the desired 1-Kbyte space ...
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Memory Expansion and Chip-Select INTERNAL SPACE $0000 $0100 $0200 1 KBYTE $0300 $0400 $0500 $0600 $0700 $0800 $0900 REGISTERS $0A00 $0B00 $0C00 $0D00 $0E00 $0F00 $0FFF Figure 8-1. Chip-Selects CS3–CS0 Partial Memory Map Register Value INITRM $00 INITRG $08 WINDEF ...
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INTERNAL SPACE $0000 REGISTERS & RAM & CS[3:0] $1000 EEPROM $2000 $3000 $4000 $5000 $6000 $7000 $8000 $9000 $A000 $B000 $C000 $D000 $E000 $F000 VECTORS $FFFF Figure 8-2. Memory Expansion and Chip-Select Example Register WINDEF MXAR CSCTL0 CSCTL1 MISC Freescale ...
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Memory Expansion and Chip-Select 8.3 Chip-Select Stretch Each chip-select can be chosen to stretch bus cycles associated with it. Stretch can be zero, one, two, or three whole cycles added which allows interfacing to external devices which cannot meet full ...
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The external E-clock may be the stretched E-clock, the E-clock clock depending on the selection of control bits ESTR and IVIS in the MODE register and NECLK in the PEAR register. 8.4 Memory Expansion Registers This section describes ...
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Memory Expansion and Chip-Select 8.4.3 Port F Data Direction Register Address: $0032 Bit 7 Read: 0 Write: Reset Unimplemented Figure 8-9. Port F Data Direction Register (DDRF) Read: Anytime Write: Anytime When port F is active, DDRF determines ...
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Program Page Register Address: $0035 Bit 7 Read: PPA21 Write: Reset: 0 Figure 8-12. Program Page Register (PPAGE) Read: Anytime Write: Anytime When enabled (PWEN = 1), the value in this register determines which of the 256 16-Kbyte pages ...
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Memory Expansion and Chip-Select PWEN — Program Window Enable Bit 1 = Enables paging of the program space (16 Kbytes: $8000–$BFFF) via the PPAGE register 0 = Disables PPAGE EWEN — Extra Window Enable Bit 1 = Enables paging of ...
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Chip-Select Registers This section describes the chip-select registers. 8.6.1 Chip-Select Control Register 0 Address: $003C Bit 7 Read: 0 Write: Reset Unimplemented Figure 8-16. Chip-Select Control Register 0 (CSCTL0) Read: Anytime Write: Anytime Bits have no effect ...
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Memory Expansion and Chip-Select CS0E — Chip-Select 0 Enable Bit CS1, CS2, and CS3 have higher precedence and can override CS0 for portions of this space Enables this chip-select which covers a 512-byte space following the register space ...
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Chip-Select Stretch Registers Each of the seven chip-selects has a 2-bit field in this register which determines the amount of clock stretch for accesses in that chip-select space. Read: Anytime Write: Anytime Address: $003E Bit 7 Read: 0 Write: ...
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Memory Expansion and Chip-Select 8.7 Priority Only one module or chip-select may be selected at a time. If more than one module shares a space, only the highest priority module is selected. Priority On-chip register space — 512 bytes fully ...
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Chapter 9 Key Wakeups 9.1 Introduction The key wakeup feature of the MC68HC812A4 issues an interrupt that wakes up the CPU when stop or wait mode. Three ports are associated with the key wakeup function: port D, ...
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Key Wakeups 9.2.2 Port D Data Direction Register Address: $0007 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 9-2. Port D Data Direction Register (DDRD) Read: Anytime Write: Anytime This register is not in the map in wide expanded ...
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Port D Key Wakeup Flag Register Address: $0021 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 9-4. Port D Key Wakeup Flag Register (KWIFD) Read: Anytime Write: Anytime Each flag is set by a falling edge on its ...
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Key Wakeups 9.2.6 Port H Data Direction Register Address: $0025 Bit 7 Read: DDRH7 Write: Reset: 0 Figure 9-6. Port H Data Direction Register (DDRH) Read: Anytime Write: Anytime Data direction register H is associated with port H and designates ...
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Port J Data Register Address: $0028 Bit 7 Read: PJ7 Write: Reset: 0 Alternate pin function: KWJ7 Figure 9-9. Port J Data Register (PORTJ) Read: Anytime Write: Anytime Port J is associated with key wakeup J. Key wakeups can ...
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Key Wakeups 9.2.12 Port J Key Wakeup Flag Register Address: $002B Bit 7 Read: KWIFJ7 Write: Reset: 0 Figure 9-12. Port J Key Wakeup Flag Register (KWIFJ) Read: Anytime Write: Anytime Each flag gets set by an active edge on ...
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Port J Pullup/Pulldown Select Register Address: $002D Bit 7 Read: PUPSJ7 PUPSJ6 Write: Reset: 0 Figure 9-14. Port J Pullup/Pulldown Select Register (PUPSJ) Read: Anytime Write: Anytime Each bit in the register corresponds to a port J pin. Each ...
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Key Wakeups 100 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 10 Clock Module 10.1 Introduction Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, ...
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Clock Module Figure 10-2 shows clock timing relationships. Four bits in the CLKCTL register control the base clock and M-clock divide selection (÷1, ÷2, ÷4, and ÷8 are selectable). T1CLK T2CLK T3CLK T4CLK INTERNAL ECLK PCLK MCLK 1 MCLK 2 ...
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Functional Description This section provides a functional description of the MC68HC812A4. 10.4.1 Computer Operating Properly (COP) The COP or watchdog timer is an added check that a program is running and sequencing properly. When the COP is being used, ...
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Clock Module SCI0 BAUD RATE GENERATOR MCLK (³ 8191) SCI1 BAUD RATE GENERATOR (³ 8191) Figure 10-4. Clock Chain for SCI0, SCI1, RTI, and COP TEN REGISTER: TMSK2 BITS: MCLK PR[2:0] 0:0:0 ÷ 2 0:0:1 ÷ ...
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PRS[4:0] PCLK 5-BIT ATD PRESCALER REGISTER: SP0BR BITS: SPR2:SPR1:SPR0 0:0:0 SPI BIT RATE ÷ 2 0:0:1 ÷ 2 0:1:0 ÷ 2 0:1:1 SYNCHRONIZER ÷ 2 1:0:0 BKGD PIN ÷ 2 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 Figure 10-6. Clock ...
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Clock Module RTIE — Real-Time Interrupt Enable Bit Write: Anytime RTIE enables interrupt requests generated by the RTIF flag RTIF interrupt requests enabled 0 = RTIF interrupt requests disabled RSWAI — RTI Stop in Wait Bit Write: Once ...
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Real-Time Interrupt Flag Register Address: $0015 Bit 7 Read: RTIF Write: Reset Unimplemented Figure 10-8. Real-Time Interrupt Flag Register (RTIFLG) RTIF — Real-Time Interrupt Flag RTIF is set when the timeout period elapses. RTIF generates an interrupt ...
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Clock Module FCM — Force Clock Monitor Reset Bit Write: Never in normal modes, anytime in special modes FCM forces a reset when the clock monitor is enabled and detects a slow or stopped clock Clock monitor reset ...
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Arm/Reset COP Timer Register Address: $0017 Bit 7 Read: 0 Write: Bit 7 Reset: 0 Figure 10-10. Arm/Reset COP Timer Register (COPRST) To restart the COP timeout period and avoid a COP reset, write $55 and then $AA to ...
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Clock Module 110 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 11 Phase-Lock Loop (PLL) 11.1 Introduction The phase-lock loop (PLL) allows slight adjustments in the frequency of the MCU. The smallest increment of adjustment is ± 9.6 kHz to the output frequency (F (OSCXTAL) and a reference divider set ...
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Phase-Lock Loop (PLL 16,778.40524 11,864.12412 3,001.412373 2,450.642941 2,237.120698 2,122.319042 1,898.259859 1,732.866242 1,604.322397 1,500.706187 1,355.8999 1,342.272419 = .0033 µ 11.3 Register Map Addr. Register Name Read: Loop Divider Register High $0040 (LDVH) Write: See page 113. Reset: ...
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Functional Description The PLL may be used to run the MCU from a different timebase than the incoming crystal value. If the PLL is selected, it continues to run when it’s in wait or stop mode which results in ...
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Phase-Lock Loop (PLL) 11.5.2 Reference Divider Registers Address: $0042 Bit 7 Read: 0 Write: Reset Unimplemented Figure 11-5. Reference Divider Register High (RDVH) Address: $0043 Bit 7 Read: RDV7 Write: Reset: 1 Figure 11-6. Reference Divider Register Low ...
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PLLS — PLL Select Bit (PLL output or crystal input frequency) PLLS selects the PLL after the LCKF flag is set PLL selected 0 = Crystal input selected BCS[C:B:A] — Base Clock Select Bits These bits determine the ...
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Phase-Lock Loop (PLL) 116 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 12 Standard Timer Module 12.1 Introduction The standard timer module is a 16-bit, 8-channel timer with: • Input capture • Output compare • Pulse accumulator functions A block diagram is given in Figure 12.2 Register Map A summary of ...
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Standard Timer Module 12.3 Block Diagram PR[2:1:0] PACLK/65536 MODULE PRESCALER CLOCK TIMCNTH:TIMCNTL 16-BIT COUNTER CHANNEL 0 16-BIT COMPARATOR TIMC0H:TIMC0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TIMC1H:TIMC1L 16-BIT LATCH CHANNELS 2–6 CHANNEL 7 16-BIT COMPARATOR TIMC7H:TIMC7L 16-BIT LATCH PAOVF TIMPACNTH:TIMPACNTL PACLK/65536 ...
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Addr. Register Name Read: Timer IC/OC Select $0080 Register (TIOS) Write: See page 125. Reset: Read: Timer Compare Force $0081 Register (CFORC) Write: See page 125. Reset: Timer Output Read: Compare 7 Mask Register Write: $0082 (OC7M) Reset: See page ...
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Standard Timer Module Addr. Register Name Read: Timer Mask Register 2 $008D (TMSK2) Write: See page 131. Reset: Read: Timer Flag Register 1 $008E (TFLG1) Write: See page 132. Reset: Read: Timer Flag Register 2 $008F (TFLG2) Write: See page ...
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Addr. Register Name Read: Timer Channel 4 Register $0099 Low (TC4L) Write: See page 133. Reset: Read: Timer Channel 5 Register $009A High (TC5H) Write: See page 133. Reset: Read: Timer Channel 5 Register $009B Low (TC5L) Write: See page ...
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Standard Timer Module Addr. Register Name Read: Timer Port Data Register $00AE (PORTT) Write: See page 139. Reset: Read: Timer Port Data Direction $00AF Register (DDRT) Write: See page 140. Reset: Figure 12-2. I/O Register Summary (Sheet ...
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Setting a force output compare bit, FOCx, causes an immediate output compare on channel x. A forced output compare does not set the channel flag. An output compare on channel 7 overrides output compares on all other output compare channels. ...
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Standard Timer Module 12.4.4.2 Gated Time Accumulation Mode Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the PAI pin enables a divided-by-64 clock to drive the PA. The PA edge bit, PEDGE, ...
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Registers and Reset Initialization This section describes the registers and reset initialization. 12.5.1 Timer IC/OC Select Register Address: $0080 Bit 7 Read: IOS7 Write: Reset: 0 Figure 12-4. Timer IC/OC Select Register (TIOS) Read: Anytime Write: Anytime IOS7–IOS0 — ...
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Standard Timer Module 12.5.3 Timer Output Compare 7 Mask Register Address: $0082 Bit 7 Read: OC7M7 Write: Reset: 0 Figure 12-6. Timer Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime OC7M7–OC7M0 — Output Compare 7 Mask Bits Setting ...
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Timer Counter Registers Address: $0084 Bit 7 Read: Bit 15 Write: Reset Unimplemented Figure 12-8. Timer Counter Register High (TCNTH) Address: $0085 Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 12-9. Timer Counter Register ...
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Standard Timer Module TSWAI — Timer Stop in Wait Mode Bit TSWAI disables the timer and PA in wait mode Timer and PA disabled in wait mode 0 = Timer and PA enabled in wait mode If timer ...
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Timer Control Registers 1 and 2 Address: $0088 Bit 7 Read: OM7 Write: Reset: 0 Figure 12-12. Timer Control Register 1 (TCTL1) Address: $0089 Bit 7 Read: OM3 Write: Reset: 0 Figure 12-13. Timer Control Register 2 (TCTL2) Read: ...
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Standard Timer Module 12.5.8 Timer Control Registers 3 and 4 Address: $008A Bit 7 Read: EDG7B Write: Reset: 0 Figure 12-14. Timer Control Register 3 (TCTL3) Address: $008B Bit 7 Read: EDG3B Write: Reset: 0 Figure 12-15. Timer Control Register ...
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Timer Mask Register 2 Address: $008D Bit 7 Read: TOI Write: Reset Unimplemented Figure 12-17. Timer Mask 2 Register (TMSK2) Read: Anytime Write: Anytime TOI — Timer Overflow Interrupt Enable Bit TOI enables interrupt requests generated by ...
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Standard Timer Module Table 12-3. Prescaler Selection (Continued) Value The newly selected prescale divisor does not take effect until the next synchronized edge when all prescale counter stages equal 0. 12.5.11 Timer Flag Register 1 Address: $008E ...
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TOF — Timer Overflow Flag TOF is set when the timer counter rolls over from $FFFF to $0000. Clear TOF by writing it Timer overflow timer overflow When the timer channel 7 ...
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Standard Timer Module 12.5.14 Pulse Accumulator Control Register Address: $00A0 Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-21. Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime PAEN — Pulse Accumulator Enable Bit PAEN enables the pulse ...
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CLK1 and CLK0 — Clock Select Bits CLK1 and CLK0 select the timer counter input clock as shown in 1. Changing the CLKx bits causes an immediate change in the timer counter clock input. 2. When PAE = 0, the ...
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Standard Timer Module PAIF — Pulse Accumulator Input Flag PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of ...
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Timer Test Register Address: $00AD Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-24. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMODN = 0) TCBYP — Timer Divider Chain Bypass Bit TCBYP divides ...
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Standard Timer Module 12.6.2 Pulse Accumulator Pin Setting the PAE bit in the pulse accumulator control register enables the pulse accumulator input pin, PAI. The PAI input and timer channel 7 use the same pin. To use the PAI input, ...
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Interrupt Sources Interrupt Source Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 Timer channel 4 Timer channel 5 Timer channel 6 Timer channel 7 Timer overflow Pulse accumulator overflow Pulse accumulator input 12.10 General-Purpose I/O ...
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Standard Timer Module Due to input synchronizer circuitry, the minimum pulse width for a pulse accumulator input or an input capture input should always be greater than the width of two module clocks. In Data Direction Register ...
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Using the Output Compare Function to Generate a Square Wave This timer exercise is intended to utilize the output compare function to generate a square wave of predetermined duty cycle and frequency. Square wave frequency 1000 Hz, duty cycle ...
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Standard Timer Module ---------------------------------------------------------------------- ; MAIN PROGRAM ; ---------------------------------------------------------------------- ORG $7000 ; MAIN: BSR TIMERINIT ; BSR SQWAVE DONE: BRA DONE ;* ----------------------------------------------------------------- ;* Subroutine TIMERINIT: Initialize Timer for Output Compare on OC2 ;* ----------------------------------------------------------------- TIMERINIT: CLR TMSK1 MOVB #$02,TMSK2 ...
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Chapter 13 Multiple Serial Interface (MSI) 13.1 Introduction The multiple serial interface (MSI) module consists of three independent serial I/O interfaces: • Two serial communication interfaces, SCI0 and SCI1 • One serial peripheral interface, SPI0 Port S shares its pins ...
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Multiple Serial Interface (MSI) 13.3 SPI Features Serial preipheral interface (SPI) fetures include: • Full-duplex operation • Master mode and slave mode • Programmable slave-select output option • Programmable bidirectional data pin option • Interrupt-driven operation with two flags: – ...
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MSI Register Map Addr. Register Name Read: SCI 0 Baud Rate Register $00C0 High (SC0BDH) Write: See page 168. Reset: Read: SCI 0 Baud Rate Register $00C1 Low (SC0BDL) Write: See page 168. Reset: Read: SCI 0 Control $00C2 ...
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Multiple Serial Interface (MSI) Addr. Register Name Read: SCI 1 Status Register 1 $00CC (SC1SR1) Write: See page 172. Reset: Read: SCI 1 Status Register 2 $00CD (SC1SR2) Write: See page 173. Reset: Read: SCI 1 Data Register High $00CE ...
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General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7–PS0 are available for either general-purpose I/O or for SCI and SPI functions. 13.6.1 Port S Data Register Address: ...
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Multiple Serial Interface (MSI) 13.6.2 Port S Data Direction Register Address: $00D7 Bit 7 Read: DDRS7 Write: Reset: 0 Figure 13-4. Port S Data Direction Register (DDRS) Read: Anytime Write: Anytime DDRS7–DDRS0 — Port S Data Direction Bits These bits ...
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RDS — Reduced Drive Port S Bit Setting RDS lowers the drive capability of all port S output pins for lower power consumption and less noise Reduced drive 0 = Full drive Table 13-1. Port S Pullup and ...
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Multiple Serial Interface (MSI) 150 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 14 Serial Communications Interface Module (SCI) 14.1 Introduction The serial communications interface (SCI) allows asynchronous serial communications with peripheral devices and other MCUs. 14.2 Features Features of the SCI include: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format ...
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Serial Communications Interface Module (SCI) 14.3 Block Diagram RXD MODULE BAUD RATE CLOCK GENERATOR ³16 SBR[12:0] T8 RXD TO SCI1 TXD FROM SCI1 WOMS 152 SCI DATA REGISTER RECEIVE SHIFT REGISTER RE RWU RECEIVE AND WAKEUP LOOPS CONTROL RSRC M ...
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Register Map The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. ...
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Serial Communications Interface Module (SCI) Addr. Register Name Read: SCI 1 Baud Rate Register $00C9 Low (SC1BDL) Write: See page 168. Reset: Read: SCI 1 Control Register 1 $00CA (SC1CR1) Write: See page 169. Reset: Read: SCI 1 Control Register ...
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Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status ...
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Serial Communications Interface Module (SCI) 14.5.2 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12–SBR0 bits ...
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MODULE BAUD DIVIDER CLOCK SBR12–SBR0 M PE GENERATION PT SCI INTERRUPT REQUEST SCI INTERRUPT REQUEST Figure 14-4. SCI Transmitter Block Diagram To initiate an SCI transmission: 1. Enable the transmitter by writing a logic 1 to the transmitter enable bit, ...
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Serial Communications Interface Module (SCI) register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCCR2) is also set, the TDRE flag generates an SCI interrupt request. When ...
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When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out to the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to ...
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Serial Communications Interface Module (SCI) 14.5.4.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive ...
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If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, ...
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Serial Communications Interface Module (SCI) RXD SAMPLES CLOCK RT CLOCK COUNT RESET RT CLOCK In Figure 14-8 noise is perceived as the beginning of a start bit although the verification sample at RT3 is high. ...
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Figure 14-10 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. RXD SAMPLES CLOCK ...
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Serial Communications Interface Module (SCI) 14.5.4.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should incoming frame, it sets the framing error flag, FE, in SCI status register ...
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Fast Data Tolerance Figure 14-14 shows how much a fast received frame can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, ...
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Serial Communications Interface Module (SCI) the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and ...
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Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCCR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the ...
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Serial Communications Interface Module (SCI) 14.6 Register Descriptions and Reset Initialization This section provides register descriptions and reset initialization. 14.6.1 SCI Baud Rate Registers SCI0: $00C0 SCI1: $00C8 Bit 7 Read: BTST BSPL Write: Reset: 0 Figure 14-17. SCI Baud ...
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SCI Control Register 1 SCI0: $00C2 SCI1: $00CA Bit 7 Read: LOOPS WOMS Write: Reset: 0 Figure 14-19. SCI Control Register 1 (SC0CR1 or SC1CR1) Read: Anytime Write: Anytime LOOPS — Loop Select Bit LOOPS enables loop operation. In ...
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Serial Communications Interface Module (SCI) Table 14-7. Loop Mode Functions (Continued) (1) LOOPS RSRC DDRSx DDRSx means the data direction bit of the TXD pin. M — Mode Bit M ...
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SCI Control Register 2 SCI0: $00C3 SCI1: $00CB Bit 7 Read: TIE Write: Reset: 0 Figure 14-20. SCI Control Register 2 (SC0CR2 or SC1CR2) Read: Anytime Write: Anytime TIE — Transmitter Interrupt Enable Bit TIE enables the transmit data ...
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Serial Communications Interface Module (SCI) SBK — Send Break Bit Toggling SBK sends one break character ( logic 0s). As long as SBK is set, the transmitter sends logic 0s Transmit break characters ...
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OR — Overrun Flag OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The data in the shift register is lost, but the data already in the SCI ...
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Serial Communications Interface Module (SCI) 14.6.6 SCI Data Registers SCI0: $00C6 SCI1: $00CE Bit 7 Read: R8 Write: Reset: = Unimplemented Figure 14-23. SCI Data Register High (SC0DRH or SC1DRH) SCI0: $00C7 SCI1: $00CF Bit 7 Read: R7 Write: T7 ...
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External Pin Descriptions This section provides a description of TXD and RXD, the SCI’s two external pins. 14.7.1 TXD Pin TXD is the SCI transmitter pin. TXD is available for general-purpose I/O when it is not configured for transmitter ...
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Serial Communications Interface Module (SCI) 14.10 Interrupt Sources Interrupt Source Transmit data register empty Transmission complete Receive data register full Receiver overrun Receiver idle 14.11 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In ...
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Code Listing A comment line is delimited by a semicolon. If there is no code before comment, a semicolon (;) must be placed in the first column to avoid assembly errors. INCLUDE 'EQUATES.ASM' ; User Variables ; Bit Equates ...
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Serial Communications Interface Module (SCI) 178 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 15 Serial Peripheral Interface (SPI) 15.1 Introduction The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communications with peripheral devices. 15.2 Features Features of the SPI include: • Full-duplex operation • Master mode and slave mode • Programmable slave-select ...
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Serial Peripheral Interface (SPI) 15.3 Block Diagram SPR2 BAUD RATE SPR1 SELECT SPR0 CLOCK P-CLOCK DIVIDER SPI CONTROL 180 MSTR CLOCK CPHA LOGIC CPOL PUPS RDS SWOM SHIFT SSOE CONTROL LOGIC SPE MSTR SPC0 MODF WCOL SPIF INTERRUPT REQUEST SPIE ...
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Register Map The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. ...
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Serial Peripheral Interface (SPI) 15.5 Functional Description The SPI allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. In master mode, the SPI generates the synchronizing clock and initiates transmissions. In slave mode, the SPI ...
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SPI data register. The byte remains in a read buffer until replaced by the next byte from the master. 15.5.3 Baud Rate Generation A clock divider in the SPI produces ...
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Serial Peripheral Interface (SPI) MISO/MOSI MASTER SS SLAVE SS CPHA = 0 Figure 15-5. Slave SS Toggling When CPHA = 0 When CPHA = 1, the master begins driving its MOSI pin and the slave begins driving its MISO pin ...
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SS Output In master mode only, the SS pin can function as a chip-select output for connection to the SS input of a slave. The master SS output automatically selects the slave by going low for each transmission and ...
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Serial Peripheral Interface (SPI) 15.6 SPI Register Descriptions and Reset Initialization This section describes the SPI registers and reset initialization. 15.6.1 SPI Control Register 1 Address: $00D0 Bit 7 Read: SPIE Write: Reset: 0 Figure 15-9. SPI Control Register 1 ...
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SSOE — Slave Select Output Enable Bit SSOE enables the output function of master SS pin when the DDRS7 bit is also set output enabled output disabled LSBF — LSB First Bit LSBF enables ...
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Serial Peripheral Interface (SPI) 15.6.3 SPI Baud Rate Register Address: $00D2 Bit 7 Read: 0 Write: Reset Unimplemented Figure 15-11. SPI Baud Rate Register (SP0BR) Read: Anytime Write: Anytime SPR2–SPR0 — SPI Clock Rate Select Bits These bits ...
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SPI Status Register Address: $00D3 Bit 7 Read: SPIF Write: Reset Unimplemented Figure 15-12. SPI Status Register (SP0SR) Read: Anytime Write: Has no meaning or effect SPIF — SPI Flag SPIF is set after the eighth serial ...
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Serial Peripheral Interface (SPI) 15.6.5 SPI Data Register Address: $00D5 Bit 7 Read: Bit 7 Write: Reset: Figure 15-13. SPI Data Register (SP0DR) Read: Anytime; normally, only after SPIF flag set Write: Anytime a data transfer is not taking place ...
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SS (Slave Select) The SS pin has multiple functions that depend on SPI configuration: • The SS pin of a slave SPI is always configured as an input and allows the slave to be selected for transmission. • When ...
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Serial Peripheral Interface (SPI) 15.9 Interrupt Sources Interrupt Source Transmission complete Mode fault 15.10 General-Purpose I/O Ports Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7–PS0 are available for either general-purpose ...
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SUBROUTINE INIT: ; ---------------------------------------------------------------------- INIT: BSET PORTS,#$80 MOVB #$E0,DDRS ; MOVB #$07,SP0BR MOVB #$12,SP0CR1 ; MOVB #$08,SP0CR2 ; LDX #DATA LDAA SP0SR LDAA SP0DR BSET SP0CR1,#$40 RTS ; ---------------------------------------------------------------------- ;* TRANSMIT SUBROUTINE ; ---------------------------------------------------------------------- TRANSMIT: LDAA 1,X+ ...
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Serial Peripheral Interface (SPI) 194 MC68HC812A4 Data Sheet, Rev. 7 Freescale Semiconductor ...
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Chapter 16 Analog-to-Digital Converter (ATD) 16.1 Introduction The analog-to-digital converter (ATD 8-channel, 8-bit, multiplexed-input, successive approximation analog-to-digital converter, accurate to ±1 least significant bit (LSB). It does not require external sample and hold circuits because of the type ...
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Analog-to-Digital Converter (ATD) 16.3 Block Diagram RC DAC ARRAY AND COMPARATOR 196 SAR CHANNEL 0 SAMPLE BUFFER AMP CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CLOCK SELECT/PRESCALE Figure 16-1. ATD Block Diagram MC68HC812A4 ...
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Register Map The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. The register block occupies the first 512 bytes of the 2-Kbyte block. This register map shows default addressing after reset. Addr. ...
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Analog-to-Digital Converter (ATD) Addr. Register Name Read: Port AD Data Input $006F Register (PORTAD) Write: See page 207. Reset: Read: ATD Result Register 0 $0070 (ADR0H) Write: See page 206. Reset: Read: ATD Result Register 1 $0072 (ADR1H) Write: See ...
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In both modes, the CCF flag associated with each register is set when that register is loaded with the appropriate conversion result. That flag is cleared automatically when that result register is read. The conversions are started by writing to ...
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Analog-to-Digital Converter (ATD) 16.6.3 ATD Control Register 2 Address: $0062 Bit 7 Read: ADPU Write: Reset Unimplemented Figure 16-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime except ASCIF flag, which is read-only Writing to this register ...