CYP15G0401DXA-BGI Cypress Semiconductor Corporation., CYP15G0401DXA-BGI Datasheet
CYP15G0401DXA-BGI
Related parts for CYP15G0401DXA-BGI
CYP15G0401DXA-BGI Summary of contents
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... Single +3.3V V • 256-ball Thermally Enhanced BGA • 0.25µ BiCMOS technology Functional Description The CYP15G0401DXA Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 200-to-1500 MBaud per serial link ...
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... The transmit section of the CYP15G0401DXA Quad HOTLink II consists of four byte-wide channels that can be operated independently or bonded to form wider buses. Each channel can accept either 8-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the Transmit Input Register to an embedded 8B/10B Encoder to improve their serial transmission characteristics ...
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... TXCLKD TXRST PARCTL Document #: 38-02002 Rev. *B PRELIMINARY Bit-Rate Clock BIST Enable Transmit Mode CYP15G0401DXA = Internal Signal Character-Rate Clock BISTLE BOE[7:0] Latch RBIST[D:A] Output Enable OELE 4 Latch 8 10 OUTA1+ OUTA1– OUTA2+ OUTA2– TXLBA 10 OUTB1+ OUTB1– ...
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... RBIST[D:A] FRAMCHAR RXRATE RFEN RFMODE RXCKSEL DECMODE 2 RXMODE[1:0] Document #: 38-02002 Rev. *B PRELIMINARY Latch Clock Select Clock Select Clock Select Clock Select CYP15G0401DXA = Internal Signal TRSTZ TMS JTAG TCLK Boundary Scan TDI Controller TDO LFIA 8 RXDA[7:0] RXOPA 3 RXSTA[2:0] RXCLKA+ ÷2 RXCLKA– ...
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... GND DD[3] STD[0] STD[2] ST[0] CLK ST[ TXRST TXOPA SCSEL GND DD[4] STD[1] CLK O− N/C TX GND DD[5] DD[0] CLK CLKA PERA O+ CYP15G0401DXA INA2- OUT INB1- OUT GND V A2− CC B1− INA2+ OUT INB1+ OUT GND V CC A2+ B1 GND ...
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... BOND RX GND GND ST[1] CLK ST[0] STD[2] SCSEL TXOPA TXRST TX GND GND CLK O− N/C TX GND GND PERA CLKA CLK O+ CYP15G0401DXA OUT IND1- OUT INC2- OUT V D1− CC C2− C1− OUT IND1+ OUT INC2+ OUT V CC D1+ C2+ C1+ ...
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... Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.2V DC Voltage Applied to LVTTL Outputs in High-Z State .........................................–0. Output Current into LVTTL Outputs (LOW)..................30 mA Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics Transmit Path Data Signals TXPERA LVTTL Output, ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics TXRST LVTTL Input, asyn- chronous, internal pull-up, sampled by TXCLKA↑ or [1] REFCLK↑ SCSEL LVTTL Input, synchronous, internal pull-down, sampled by TXCLKA↑ [1] or REFCLK↑ Transmit Path Clock and Clock Control [2] TXCKSEL 3-Level Select Static Control Input TXCLKO± ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics Transmit Path Mode Control [2] TXMODE[1:0] 3-Level Select Static Control inputs Receive Path Data Signals RXDA[7:0] LVTTL Output, RXDB[7:0] synchronous to the RXDC[7:0] selected RXCLKx↑ RXDD[7:0] output or [1] REFCLK↑ input RXSTA[2:0] LVTTL Output, ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics [2] RXMODE[1:0] 3-Level Select Static Control Inputs [2] RXCKSEL 3-Level Select Static Control Input [2] FRAMCHAR 3-Level Select Static Control Input [2] RFMODE 3-Level Select Static Control Input [2] DECMODE 3-Level Select Static Control Input Document #: 38-02002 Rev. *B ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics Device Control Signals [2] PARCTL 3-Level Select Static Control Input [2] SPDSEL 3-Level Select , static configuration input REFCLK± Differential LVPECL or single-ended LVTTL input clock Analog I/O and Control OUTA1± CML Differential OUTB1± Output OUTC1± ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics [2] SDASEL 3-Level Select , static configuration input LPEN LVTTL Input, asynchronous, internal pull-down OELE LVTTL Input, asynchronous, internal pull-up BISTLE LVTTL Input, asynchronous, internal pull-up RXLE LVTTL Input, asynchronous, internal pull-up BOE[7:0] LVTTL Input, ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics Bonding Control BONDST[1:0] Bidirectional Open Drain, internal pull-up MASTER LVTTL Input, static configuration input internal pull-down BOND_ALL Bidirectional Open Drain, Internal pull-up BOND_INH LVTTL Input, static configuration input Internal pull-up JTAG Interface TMS ...
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... Pin Descriptions CYP15G0401DXA Quad HOTLink II Transceiver Name I/O Characteristics TRSTZ LVTTL Input, internal pull-up Power V CC GND Document #: 38-02002 Rev. *B PRELIMINARY Signal Description Test Port and Device Reset. Active LOW. Initializes the JTAG controller and all state machines and counters in the device. ...
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... Buffer alignment recommend that the sequence be followed by a second Word Sync Sequence to ensure prop- er operation. Parity Support In addition to the ten data and control bits that are captured at each channel, a TXOPx input is also available on each chan- nel. This allows the CYP15G0401DXA to support ODD parity CYP15G0401DXA Page ...
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... The CYP15G0401DXA is designed to support two independent (but non-overlapping) Special Character code tables. This al- lows the CYP15G0401DXA to operate in mixed environments with other CYP15G0401DXAs using the enhanced Cypress command code set, and the reduced command sets of other non-Cypress devices ...
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... K28.5 characters in this sequence would follow a pattern of either ++––+–+–+–+–+–+– or ––++–+–+–+–+–+–+. When TXMODE[ (open, TX modes 3, 4, and 5), the generation of this character sequence is an atomic (non-inter- CYP15G0401DXA Bus Weight 10B Name 0 2 ...
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... TX Mode 3. Two additional encoding maps are provided for use when re- ceive channel bonding is enabled. When dual-channel bond- ing is enabled (RXMODE[1] = M), the CYP15G0401DXA is configured such that channels A and B are bonded together to form a two-character-wide path, and channels C and D are bonded together to form a second two-character-wide path ...
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... In a similar fashion, anytime TXCTD[0] is sampled HIGH, both the C and D channels start generation of an Atom- ic Word Sync Sequence. When RXMODE[ the CYP15G0401DXA is configured for quad-channel bonding, such that channels and D are bonded together to form a four-character-wide path. When operated in this mode, the TXCTA[0] and TXCTB[0] inputs control the interpretation of the data on all four channels ...
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... The clock multiplier PLL can accept a REFCLK input between X 10 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYP15G0401DXA clock multiplier Receive D (controlled by TXRATE) and by the level on the SPDSEL input. X SPDSEL is a 3-level select ...
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... The switch points are asymmetric to provide hyster- esis to the operation. Receive Channel Enabled The CYP15G0401DXA contains four receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the BOE[7:0] inputs, as controlled by the RXLE latch-enable signal. When ...
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... The location of this character in the data stream is used to determine the character boundaries of all following characters. Framing Character The CYP15G0401DXA allows selection of one of three com- binations of framing characters to support requirements of dif- ferent interfaces. The selection of the framing character is made through the FRAMCHAR input. ...
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... BOE[x] signals are captured in the BIST Enable Latch. These values remain in the BIST Enable Latch until BISTLE is re- turned high to open the latch again. All captured signals in the BIST Enable Latch are set HIGH (i.e., BIST is disabled) follow- ing a device reset (TRSTZ is sampled LOW). CYP15G0401DXA Page ...
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... DECMODE. The specific patterns checked by each receiver are described in detail in the Cypress application note “HOTLink Built-In Self- Test.” The sequence compared by the CYP15G0401DXA is identical to that in the CY7B933 and CY7C924DX, allowing interoperable systems to be built when used at compatible se- rial signaling rates ...
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... The Elasticity buffer may also be set by a de- vice reset operation initiated through the TRSTZ input, howev- er, following such an event the CYP15G0401DXA will normally require a framing event before it will correctly decode charac- ters. Since the Elasticity buffer is not allowed to insert or delete framing characters, the transmit clocks on the channels must all be from a common source ...
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... The signals present on this output bus are modified by the present operating mode of the CYP15G0401DXA as selected by DECMODE. This mapping is shown in Table 18. When the 10B/8B decoder is bypassed (DECMODE = LOW), the framed 10-bit value is presented to the associated output register, along with a status output indicating if the character in the output register is one of the selected framing characters ...
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... CYP15G0401DXA sup- ports multiple different forms of parity generation (in addition to no parity). When the decoders are enabled (DECMODE ≠ LOW), parity can be generated on • the RXDx[7:0] character • the RXDx[7:0] character and RXSTx[2:0] status When the decoders are bypassed (DECMODE = LOW), parity can be generated on • ...
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... RX Modes 0 and 2), these state machines are disabled and characters are decoded directly Mode 0 the RESYNC (111b) status is never reported Mode 2, nei- ther the RESYNC (111b) or Channel Lock Detected (010b) status are reported. CYP15G0401DXA Receive BIST Status (Receive BIST = Enabled) BIST Data Compare. Charac- ter compared correctly BIST Command Compare ...
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... Document #: 38-02002 Rev. *B PRELIMINARY State Transition Conditions Figure 2. Status Type-A Receive State Machine The IN_SYNC state can respond with multiple status types, while others can respond with only one type. CYP15G0401DXA Reset NO_SYNC RXSTx=101 4 3 RESYNC RXSTx=111 2 Page ...
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... BIST sequence must both have RXCKSEL = MID or both have RXCKSEL ≠ MID. JTAG Support The CYP15G0401DXA contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, only boundary scan is supported. This capability is present only on the LVTTL inputs and outputs and the REFCLK± ...
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... JTAG ID The JTAG device ID for the CYP15G0401DXA is ‘0C800069’x. RXSTx = RXSTx = BIST_START (101) BIST_WAIT (111) Start of BIST Detected No BIST_DATA_COMPARE (000)/ BIST_COMMAND_COMPARE(001) Mismatch Auto-Abort Yes Condition No End-of-BIST State Yes, RXSTx = BIST_LAST_BAD (100) Document #: 38-02002 Rev. *B PRELIMINARY 3-Level Select Inputs Each 3-Level select inputs reports as two bits in the scan reg- ister ...
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... CYP15G0401DXA DC Electrical Characteristics Parameter Description LVTTL Compatible Outputs V Output HIGH Voltage OHT V Output LOW Voltage OLT I Output Short Circuit Current OST I High-Z Output Leakage Current OZL LVTTL Compatible Inputs V Input HIGH Voltage IHT V Input LOW Voltage ILT I Input HIGH Current IHT ...
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... CYP15G0401DXA DC Electrical Characteristics Parameter Description Note: 11. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 12. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0 13. The common mode range defines the allowable range of REFCLK+ and REFCLK − (relative to the associated power rail) when |(REFCLK+) − ...
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... CYP15G0401DXA Transmitter LVTTL Switching Characteristics Parameter f TXCLKx Clock Cycle Frequency TS t TXCLKx Period TXCLK t TXCLKx HIGH Time TXCLKH t TXCLKx LOW Time TXCLKL [17, 18, 19] t TXCLKx Rise Time TXCLKR [17, 18, 19] t TXCLKx Fall Time TXCLKF Transmit Data Set-Up Time to TXCLKx↑ (TXCKSEL ≠ LOW) ...
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... Received Data Setup Time to RXCLKC (RXCKSEL = LOW) REFCDS t Received Data Hold Time from RXCLKC (RXCKSEL = LOW) REFCDH t REFCLK Frequency Referenced to Received Clock Period REFRX CYP15G0401DXA Transmit Serial Outputs and TX PLL Characteristics Parameter t Bit Time B t CML Output Rise Time 20−80% (CML Test Load) RISE t CML Output Fall Time 80− ...
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... CYP15G0401DXA Receive Serial Inputs and CDR PLL Characteristics Parameter t Receive PLL lock to input data stream (cold start) RXLOCK Receive PLL lock to input data stream t Receive PLL Unlock Rate RXUNLOCK [17, 25] t Static Alignment SA [17, 26, 27] t Error Free Window EFW [17] Capacitance Parameter Description ...
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... CYP15G0401DXA HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing TXCKSEL ≠ LOW TXCLKx TXDx[7:0], TXCTx[1:0], TXOPx, SCSEL Transmit Interface Write Timing TXCKSEL = LOW TXRATE = LOW REFCLK TXDx[7:0], TXCTx[1:0], TXOPx, SCSEL Transmit Interface Write Timing TXCKSEL = LOW TXRATE = HIGH REFCLK TXDx[7:0], TXCTx[1:0], ...
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... CYP15G0401DXA HOTLink II Transmitter Switching Waveforms Transmit Interface TXCLKO Timing TXCKSEL = LOW TXRATE = LOW REFCLK t TXOH Note 30 TXCLKO Switching Waveforms for the CYP15G0401DXA HOTLink II Receiver Receive Interface Read Timing RXCKSEL = LOW TXRATE = LOW REFCLK RXDx[7:0], RXSTx[2:0], RXOPx RXCLKA RXCLKC Receive Interface Read Timing ...
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... Switching Waveforms for the CYP15G0401DXA HOTLink II Receiver Receive Interface Read Timing RXCKSEL = HIGH or MID RXRATE = LOW RXCLKx+ RXCLKx- RXDx[7:0], RXSTx[2:0], RXOPx Receive Interface Read Timing RXCKSEL = HIGH or MID RXRATE = HIGH RXCLKx+ RXCLKx- RXDx[7:0], RXSTx[2:0], RXOPx Static Alignment /2 − ± ...
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... After powering on, the Transmitter may assume either a posi- tive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character CYP15G0401DXA Page ...
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... Table 23 shows an example of this behavior. Character RD Character − D21.1 D10.2 − 101010 1001 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0401DXA Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 ...
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... D28.1 001 11100 010001 1011 D29.1 001 11101 100001 1011 D30.1 001 11110 010100 1011 D31.1 001 11111 CYP15G0401DXA Bits Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 ...
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... D28.3 011 11100 010001 0101 D29.3 011 11101 100001 0101 D30.3 011 11110 010100 0101 D31.3 011 11111 CYP15G0401DXA Bits Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0011 011000 1100 011101 0011 100010 1100 101101 0011 010010 1100 ...
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... D28.5 101 11100 010001 1101 D29.5 101 11101 100001 1101 D30.5 101 11110 010100 1101 D31.5 101 11111 CYP15G0401DXA Bits Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1010 011000 1010 011101 1010 100010 1010 101101 1010 010010 1010 ...
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... D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0401DXA Bits Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0001 011000 1110 011101 0001 100010 1110 101101 0001 010010 1110 ...
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... C1.7 (CE1) 111 00001 111 00010 C2.7 (CE2) 111 00010 111 00100 C4.7 (CE4) 111 00100 CYP15G0401DXA Bits Current RD− Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011 110000 1100 ...
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... Ordering Information Speed Ordering Code Standard CYP15G0401DXA-BGC Standard CYP15G0401DXA-BGI HOTLink II, and MultiFrame are trademarks of Cypress Semiconductor Corporation. IBM is a registered trademark of International Business Machines. ESCON is a registered trademark of International Business Machines. FICON is a trademark of International Business Machines. Package Diagram 256-Lead Thermally Enhanced L2BGA ( 1.52 mm) BL256 Document #: 38-02002 Rev ...
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... Revision History Document Title: CYP15G0401DXA Quad HOTLink II™ Transceiver (Preliminary) Document Number: 38-02002 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE ** 105840 03/21/01 SZV *A 108025 06/20/01 AMV *B 108437 07/19/01 TME Document #: 38-02002 Rev. *B © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...