MC145421P Freescale Semiconductor, Inc, MC145421P Datasheet
MC145421P
Related parts for MC145421P
MC145421P Summary of contents
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... SLAVE 16 kbps D2 ISDN UDLT 64 kbps B1 64 kbps B2 Order this document by MC145421/D MC145421 MC145425 P SUFFIX 24 PLASTIC PACKAGE 1 CASE 709 DW SUFFIX SOG PACKAGE 24 CASE 751F 1 ORDERING INFORMATION MC145421P Plastic Package MC145425P Plastic Package MC145421DW SOG Package MC145425DW SOG Package MC145421 MC145425 1 ...
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MC145421 — MASTER (PLASTIC AND SOG PACKAGES ref 2 23 LO1 LO2 RE2 D1I 6 19 RE1 D2I 7 18 TDC/RDC DCLK 8 ...
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MC145421 MASTER ISDN BLOCK DIAGRAM 23 + LO1 MODULATOR 22 – LO2 MSI 17 CCI ref DEMODULATOR MC145425 SLAVE ISDN BLOCK DIAGRAM 23 + LO1 ...
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ABSOLUTE MAXIMUM RATINGS (Voltage Referenced Rating DC Supply Voltage V DD – Voltage Any Pin Current, Any Pin (Excluding Operating Temperature Storage Temperature RECOMMENDED ...
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MC145421 MASTER PIN DESCRIPTIONS V DD Positive Supply (Pin 24) The most positive power supply pin, normally + 5 V with respect Negative Supply (Pin 1) The most negative supply pin and logic ground, ...
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DCLK D Channel Clock Input (Pin 8) This input is the transmit and receive data clock for both D channels. D channel input and output operation is de- scribed in the D1O, D2O pin description. Tx Transmit Data Output (Pin ...
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Mu/A Tone Format Input (Pin 11) This pin determines the PCM code for the 500 Hz square wave tone generated when the TONE input is high — Mu– Law (Mu CCITT A–Law (Mu format. TONE ...
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BACKGROUND The MC145421 and the MC145425 ISDN UDLTs provide an economical means of sending and receiving two B chan- nels (64 kbps each) of voice/data and two D channels (16 kbps each) of signal data in a two–wire configuration at ...
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In the master, time–out begins on the rising edge of the third MSI following the last received burst. This is equivalent to two MSI frames. The VD output is forced low during time– out. The B channel output data will ...
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EN1 EN2 DCLK 1 BCLK VD D1I, D2I D1O, D2O Tx B CHANNEL 1 OUTPUT Rx B CHANNEL 1 INPUT Figure 2. MC145425 Slave ISDN UDLT Timing Top Trace: MSI Bottom Trace: Outgoing burst measured at LI (with respect to ...
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LO1 LO2 MASTER OR SLAVE ISDN UDLT V ref LI TRANSFORMER PARAMETERS INDUCTANCE OF Tx: WINDING: 1.75 mH TURNS RATIO 2:1 TURNS RATIO 4:1 MOTOROLA + 5 V 110 110 Tx L1 ...
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SWITCHING CHARACTERISTICS ( Load = 50 pF) No.* Master Timing 1 TDC/RDC Pulse Width High 2 TDC/RDC Pulse Width Low 3 MSI Rising Edge to TDC/RDC Falling Edge ...
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MOTOROLA MC145421 MC145425 13 ...
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MC145421 MC145425 14 MOTOROLA ...
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- 28X 0.010 (0.25 -T- G 26X MOTOROLA PACKAGE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 709– SEATING ...
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...