CY28419ZCT Cypress Semiconductor Corporation., CY28419ZCT Datasheet
CY28419ZCT
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CY28419ZCT Summary of contents
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Features • CK409B-compliant £ • Supports Intel Pentium 4-type CPUs • Selectable CPU frequencies • 3.3V power supply • Ten copies of PCI clocks • Two copies 48-mHz clock • Five copies of 3V66 with one optional VCH Block Diagram ...
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Pin Description Pin No. Pin Name Pin Type 1,2 REF(0: XIN 5 XOUT O, SE 41,44,47,50 CPUT(0:3) O, DIF 40,43,46,49 CPUC(0:3) O, DIF 38, 37 SRCT, SRCC O, DIF 22,23,26,27 3V66(3: 3V66_4VCH O, SE ...
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Frequency Select Pins (FS_A, FS_B) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A and FS_B inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock ...
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Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol 19 Acknowledge from slave 20:27 Byte Count – 8 bits 28 Acknowledge from slave 29:36 Data byte 1 – 8 bits 37 Acknowledge from slave 38:45 Data byte ...
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Byte 0: Control Register 0 Bit @Pup 7 0 Reserved 6 1 Reserved 5 0 Reserved 4 0 Reserved 3 1 Reserved 2 1 Reserved 1 Externally FS_B Selected 0 Externally FS_A Selected Byte 1: Control Register 1 Bit @Pup ...
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Byte 3: Control Register 3 Bit @Pup Name 7 1 All PCI and SRC Clock outputs except PCIF and SRC clocks set to free-running 6 1 PCI6 5 1 PCI5 4 1 PCI4 3 1 PCI3 2 1 PCI2 1 ...
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Byte 6: Control Register 6 Bit @Pup Name 7 0 REF PCIF PCI 3V66 USB_48 DOT_48 CPUT/C SRCT CPUC0, CPUT0 CPUC1, CPUT1 CPUC2, CPUT2 CPUC3, CPUT3 4 0 SRCT, SRCC PCIF PCI ...
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Crystal Loading Crystal loading plays a critical role in achieving low ppm perfor- mance. To realize low-ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (CL). The following diagram shows ...
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PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF Figure 3. Power-down Assertion Timing Waveforms PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of ...
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FS_A, FS_B VTT_PWRGD# PWRGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 6. Clock Generator Power-up/Run State Diagram Document #: 38-07444 Rev. *D 0.2-0.3mS Wait for Sample Sels ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications Parameter Description CPU at 0.7V T CPUT and CPUC Duty Cycle DC T 100-MHz CPUT and CPUC Period Measured at crossing point V PERIOD T 133-MHz CPUT and CPUC Period Measured at crossing point V PERIOD T ...
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AC Electrical Specifications Parameter Description PCI / PCIF T PCIF and PCI Duty Cycle DC T Spread Disabled PCIF/PCI Period Measurement at 1.5V PERIOD T Spread Enabled PCIF/PCI Period PERIOD T PCIF and PCI High Time HIGH T PCIF and ...
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... Shrunk Small Outline package (SSOP) – Tape and Reel CY28419ZC 56-pin Thin Shrunk Small Outline package (TSSOP) CY28419ZCT 56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel Commercial Document #: 38-07444 Rev ...
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Package Drawing and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 2 Purchase components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips 2 ...
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Document History Page Document Title: CY28419 Clock Synthesizer with Differential SRC and CPU Outputs Document Number: 38-07444 REV. ECN NO. Issue Date ** 121413 12/05/02 *A 127740 07/01/03 *B 128452 07/30/03 *C 129785 10/03/03 *D 203832 See ECN Document #: ...