MPC948 Freescale Semiconductor, Inc, MPC948 Datasheet

no-image

MPC948

Manufacturer Part Number
MPC948
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC948
Manufacturer:
EPSON
Quantity:
9
Part Number:
MPC948
Manufacturer:
NS
Quantity:
105
Part Number:
MPC948
Manufacturer:
MTO
Quantity:
1 000
Part Number:
MPC948
Manufacturer:
MTO
Quantity:
20 000
Part Number:
MPC948FA
Manufacturer:
Motorola
Quantity:
302
Part Number:
MPC948FA
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MPC948FAR2
Manufacturer:
FUJITSU
Quantity:
120
Part Number:
MPC948FAR2
Manufacturer:
JAPAN
Quantity:
336
Part Number:
MPC948FAR2
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MPC948L
Manufacturer:
MTO
Quantity:
1 000
Part Number:
MPC948LFA
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Low Voltage 1:12 Clock
Distribution Chip
features the capability to select either a differential LVPECL or a LVTTL
compatible input. The 12 outputs are LVCMOS or LVTTL compatible and
feature the drive strength to drive 50Ω series terminated transmission
lines. With output–to–output skews of 350ps, the MPC948 is ideal as a
clock distribution chip for the most demanding of synchronous systems.
For a similar product targeted at a lower price/performance point, please
consult the MPC947 data sheet.
LOW logic states, the output buffers of the MPC948 are ideal for driving
series terminated transmission lines. More specifically, each of the 12
MPC948 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC948 has an effective fanout of 1:24 in
applications where each line drives a single load. With this level of fanout,
the MPC948 provides enough copies of low skew clocks for high
performance synchronous systems, including use as a clock distribution
chip for the L2 cache of a PowerPC 620 based system.
MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the TTL_CLK_Sel pin will select the TTL level clock input.
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into
high impedance. Note that all of the MPC948 inputs have internal pullup resistors.
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
PowerPC is a trademark of International Business Machines Corporation.
1/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
Clock Distribution for PowerPC
LVPECL or LVCMOS/LVTTL Clock Input
350ps Maximum Output–to–Output Skew
Drives Up to 24 Independent Clock Lines
Maximum Output Frequency of 150MHz
Synchronous Output Enable
Tristatable Outputs
32–Lead TQFP Packaging
3.3V V CC Supply Voltage
The MPC948 is a 1:12 low voltage clock distribution chip. The device
With an output impedance of approximately 7Ω, in both the HIGH and
The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the
All of the control inputs are LVCMOS/LVTTL compatible. The MPC948 provides a synchronous output enable control to allow
The MPC948 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
620 L2 Cache
1
REV 3
DISTRIBUTION CHIP
32–LEAD TQFP PACKAGE
LOW VOLTAGE
MPC948
1:12 CLOCK
CASE 873A–02
FA SUFFIX

Related parts for MPC948

MPC948 Summary of contents

Page 1

... L2 cache of a PowerPC 620 based system. The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies ...

Page 2

... MPC948 PECL_CLK PECL_CLK TTL_CLK TTL_CLK_Sel Sync_OE Tristate VCCO GND 28 MPC948 Q1 29 VCCO GND Figure 2. 32–Lead Pinout (Top View) TTL_CLK Sync_OE Q MOTOROLA 0 1 Figure 1. Logic Diagram GND VCCO GND ...

Page 3

... V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the V CMR range and the input swing lies within the V PP specification. 2. The MPC948 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). ...

Page 4

... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC948 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...

Page 5

... F D É É SECTION AE– MPC948 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...

Page 6

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 MPC948/D TIMING SOLUTIONS BR1333 — Rev 6 ...

Related keywords