CS4215-KL Cirrus Logic, Inc., CS4215-KL Datasheet
CS4215-KL
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CS4215-KL Summary of contents
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... The +5V only power requirement makes the CS4215 ideal for use in workstations and personal computers. Integration of microphone and line level inputs, input and output gain setting, along with headphone and monitor speaker driver, results in a very small footprint. Ordering Information: CS4215-KL CS4215-KQ CDB4215 A/D M Gain ...
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... Mic Inputs (0 to 0.45 Fs) Line Inputs Mic Inputs Line Inputs (AC Coupled) Line Inputs (DC Coupled) Mic Inputs Line Inputs (AC Coupled) Line Inputs (DC Coupled) Mic Inputs (MLB=0) Mic Inputs (MLB=1) Mic Inputs Line Inputs (Note 3) (Note 4) CS4215 Min Typ Max Units Bits - - 0.9 LSB 80 84 ...
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... Headphone Out (Note 6) THD Speaker Out (Note 6) Line Out (Note 5) Headphone Out (Note 6) Line Out Headphone (0 to 0.45 Fs) (All Outputs) Line Out Line Output (Note 5) Line Output (Note 5) Headphone Output (Note 6) Operating Power Down (1 kHz) CS4215 Min Typ Max IDR 0.025 ...
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... High-level Output Voltage Low-level Output Voltage Input Leakage Current Output Leakage Current 4 Symbol (Fs is conversion freq.) Symbol (Fs is conversion freq VA1, VA2, VD1, VD2 = 5V) A Symbol = -2 2.0 mA (Digital Inputs) (High-Z Digital Outputs) CS4215 Min Typ Max 0 - 0.45Fs -0 0.45Fs - 0.55Fs 0.55Fs - 74 - ...
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... In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec (CLKIN, XTAL1, XTAL2). 10. Sample rate specifications must not be exceeded. 11. After powering up the CS4215, RESET should be held low for allow the voltage reference to settle ...
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... must be less than 0.5 Volts (one diode drop). 6 (AGND, DGND = 0V, all voltages with respect to 0V.) Symbol Digital VD1,VD2 Analog VA1,VA2 (Except Supply Pins) (Power Applied) (AGND, DGND = 0V, all voltages with re- Symbol Digital (Note 8) VD1,VD2 Analog (Note 8) VA1,VA2 T A CS4215 Min Max Units -0.3 6.0 -0.3 6.0 - 10.0 -0.3 (VA1, VA2)+0.3 -0.3 (VD1, VD2)+0.3 ...
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... LINR 18 LIN PIO0 3 7 PIO1 Figure 1. Recommended Connection Diagram CS4215 + alog 1/ dph one Jack 31 > ...
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... Control for the functions available on the CS4215, as well as the audio data, are communi- cated to the device over a serial interface. Separate pins for input and output data are pro- vided, allowing concurrent writing to and reading from the device ...
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... The CMOUT reference level is used to rms level shift the signal. This level shifting allows the line inputs coupled into the CS4215. Minimum ADC offset results when the line inputs are DC coupled (see Analog Charac- teristics Table). Figure 3 shows an AC coupled input circuit for signals centered around 0 Volts ...
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... If full scale data from the ADCs is added . Ex- to full scale digital data from the serial interface, clipping will occur. Calibration Both output offset voltage and input offset error are minimized by an internal calibration cycle. At least one calibration cycle must be invoked CS4215 resistors. This circuit is DS76F2 ...
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... A cali- bration cycle will also occur immediately after going from control mode to data mode (D/C go- ing high). When powering up the CS4215, or exiting the power down state, a minimum must occur, to allow the voltage reference to settle, before initiating a calibration cycle. ...
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... Clock Generation The master clock operating the CS4215 may be generated using the on-chip crystal oscillators using an external clock source. In all data modes SCLK and FSYNC must be synchronous to the selected master clock. If the master clock source stops, the digital fil- ters will power down after 5 overheating ...
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... SCLK frequency is always equal to the bit rate. The Frame Synchronizing signal (FSYNC) is used to indicate the start of a frame. It may be output from one of the CS4215s may be generated from an external controller. If FSYNC is generated externally, it must be high for at least 1 SCLK period, and it must fall at least 2 SCLKs before the start of a new frame (see Figure 8) ...
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... SDIN SDOUT _ D/C Control Mode 14 T1 TS8 TS1 TS2 TS3 TS8 TS1 DEVICE A T1 1/Frame Rate or 1/System Sample Rate TSn Time slot numbers Figure 8. Serial Interface Timing for 2 CS4215’ TS1 TS2 Figure 9. Frame Sync and Bit Offset Timing ...
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... SCLK bit time, and indicates that the CS4215 is about to release the bus. TSIN is an input signal that informs the CS4215 that the next time slot is available for it to use. The first device in the chain uses FSYNC as its TSIN signal. All subsequent devices use the TSOUT of the previous device as its TSIN input ...
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... Therefore, the value read back may differ from the value written. In the data mode, (D/C=1), this register can be read and written to through the serial port as part of the Input Settings Registers. In control mode, (D/C=0) these bits can only be read. 16 CS4215 DS76F2 ...
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... Transmit/receive data with attenuated outputs and muted speaker for 194 FSYNC cycles while codec executes offset calibration Transmit/receive audio data with desired level settings Figure 11. Control Mode Flow Chart CS4215 1 This is a software design choice, not a run-time conditional branch Send valid control information ...
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... Must be written Disabled Enabled. A Digital High Pass Filter is used to force the ADC DC offset to zero. CS4215 CLB RSRV FUNCTION DF1 DF0 0 ...
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... D/C goes low TEST VALUE 0 R Digital-Digital Loopback. 1 Digital-Analog-Digital Loopback Disable. 1 Enable. The TEST bits must be written as zero, otherwise special factory test modes may be invoked. CS4215 XEN FUNCTION ENL DAD ...
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... See Appendix "E". This Data Sheet Must be written RSRV VALUE Must be written as 0. CS4215 RSRV FUNCTION FUNCTION D3 ...
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... Note that a digital code DS76F2 Data to A Data to B Data from A Data from B Data Mode Figure 12. Data Mode Timing for 2 CS4215’s +FS -FS 8-bit unsigned: 16-bit 2’s comp: -Law. Figure 13 CS4215 ...
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... A-Law is equivalent to 12 bits. This low-level dynamic range is obtained at the expense of large-signal dynamic range which, for both -Law and A-Law, is equivalent to 6 bits. The CS4215 internally operates at 16 bits. The companded data is expanded to the upper 13 Data Time Slot 5, Output Setting Register Reset (R) ...
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... MA1 MA0 RG3 VALUE 1.5dB gain steps. RG3 is the MSB gain, 1111 = 22.5dB gain 6dB attenuation steps. MA3 is the MSB attenuation, 1111 = mute. CS4215 RO2 RO1 RO0 FUNCTION D3 ...
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... OVR ADI LSB MSB LSB MSB OVR OVR ADI ADI LSB MSB LSB LSB MSB MSB CS4215 IS OVR SE ADI LE HE DAD ENL XEN XCLK ITS ST HPF LSB CLB OLB MLB MSB DS76F2 ...
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... CS4215. The third mode allows laboratory testing using external equipment. Host Self-Test Loopback Modes Since the CS4215 is a mixed-signal device equipped with an internal register that will en- able the host to perform a two-tiered test on power- needed. The loopback test is en- abled by setting the Enable Loopback bit, ENL, in control register 4 ...
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... CS4215 by connecting the right and left analog outputs, after the output attenuator, to the analog inputs of the gain stage. This allows testing of most of the CS4215 from the host by sending a known digital signal to the DACs and monitoring the digital signal from the ADCs. During DAD ...
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... CPU & Digital Logic POWER SUPPLY AND GROUNDING When using separate supplies, the digital power should be connected to the CS4215 via a ferrite bead, positioned closer than 1" to the device (see Figure 1). The codec VA1, VA2 pins should be derived from the cleanest power source available. ...
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... Digital Supply 1 Digital Supply + Figure 20. CS4215 Surface Mount Decoupling Layout Figure 19. CS4215 Decoupling Layout Guideline 1 uF CS4215 Analog Supply + + Analog Supply + + 10 uF DS76F2 ...
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... ADC and DAC Filter Response Plots Figures 21 through 27 show the overall fre- quency response, passband ripple and transition band for the CS4215 ADCs and DACs. Fig- ure 27 shows the DACs’ deviation from linear phase the selected sample frequency. Since the sample frequency is programmable, the fil- ters will adjust to the selected sample frequency ...
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... Input Frequency (Fs) Figure 24. DAC Frequency Response 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Input Frequency (Fs) Figure 26. DAC Transition Band 30 0.2 0.1 -0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.6 0.7 0.8 0.9 1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Figure 27. DAC Deviation from Linear Phase CS4215 Input Frequency (Fs) Figure 25. DAC Passband Ripple Input Frequency (Fs) DS76F2 ...
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... PIN DESCRIPTIONS 1 XTL1OUT 2 VD2 4 DGND2 6 XTL2IN 8 XTL2OUT 10 RESET 14 PDN 16 MINR 18 LINR 20 MINL 22 LINL 24 25 Note: All unlabeled pins are No Connects DS76F2 CS4215 100-PIN TQFP (Q) Top View CS4215 75 74 PIO1 72 PIO0 70 D/C 66 LOUTR 64 LOUTL 60 HEADL 56 HEADC 52 HEADR 51 31 ...
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... Digital ground. Must be connected to AGND1, AGND2 with zero impedance CS4215 9 10 44-PIN 11 PLCC 12 ( Top View CS4215 SDOUT SCLK FSYNC TSOUT TSIN PIO1 38 PIO0 LOUTR 32 LOUTL 31 30 HEADL 29 HEADC 28 HEADR MOUT1 ...
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... AGND1 pin. No other external load may be connected to this output. Digital Interface Signals SDIN - Serial Data Input, Pin 1(L), 87(Q) Audio data for the DACs and control information for all functions is presented to the CS4215 on this pin. SDOUT - Serial Data Output, Pin 44(L), 85(Q) Audio data from the ADCs and status information concerning all functions is written out by the CS4215 onto this pin ...
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... SCLKs before the next frame starts. TSIN - Time Slot Input, Pin 40(L), 77(Q) TSIN high for at least 1 SCLK cycle indicates to the CS4215 that the next time slot is allocated for it to use. TSIN is normally connected to the TSOUT pin of the previous device in the chain. ...
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... These pins are provided as general purpose digital parallel input/output and have open drain outputs. An external pull-up resistor is required. They can be read in control mode, and read and written to in data mode. Note: All unlabeled pins are No Connects which should be left floating. DS76F2 CS4215 35 ...
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... Worst case variation in output signal level versus frequency over kHz. Units in dB. Step Size Typical delta between two adjacent gain or attenuation values. Units in dB. Absolute Step Error The deviation of a gain or attenuation step from a straight line passing through the no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB. 36 CS4215 DS76F2 ...
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... Tested with 48kHz Fs giving an out-of-band energy range of 22kHz to 100kHz. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input at CMOUT. For the DACs, the deviation of the output from CMOUT with mid-scale input code. Units in volts. DS76F2 CS4215 37 ...
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... APPENDIX A This data sheet describes version 2 of the CS4215. Therefore, this appendix is included to describe the differences between versions 0,1 and version 2. This information is only useful for users that still have version 0 and version 1 devices since version 2 devices will supplant the earlier versions. The version number can be found in control mode, time slot 7 ...
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... P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581 General Description The CDB4215 evaluation board allows easy evaluation of the CS4215 audio multimedia codec. Analog inputs provided include two BNC line inputs. Analog outputs provided are two BNC line outputs, one stereo pair of speaker terminals ...
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... BNC’s, a stereo headphone jack, and a pair of mono speaker ter- minals. The CS4215 drives the line outputs into an R-C filter and then to a pair of BNC’s. As with the line inputs, BNC-to-phono adapters are provided for flexibility. The line outputs can drive an im- pedance input impedance of most audio gear ...
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... MINR 19 CMOUT 17 MINL CS4215 16 LINR U1 18 LINL 10 XTL2IN Y2 11 XTL2OUT 6 XTL1IN Y1 7 XTL1OUT 4 CLKIN AGND1 AGND2 DGND1 Figure 1. CS4215 & Power Supplies CDB4215 VA 0 C12 C31 C33 24 VA1 VA2 C34 28 MOUT1 + R52 R51 C16 MOUT2 + 1/2W ...
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... R56 0 150 4 U2 C47 MC33178 R57 150 C46 C1 560 pF NPO 22 Figure 3. Microphone Input Buffer CDB4215 C36 0.1 uF CS4215 16 LINR 0.01 uF NPO C10 19 CMOUT 18 LINL CS4215 C48 15 MINR 0.47 uF NPO 0. CMOUT C45 17 MINL 0.47 uF NPO 0.01 uF DS76DB3 ...
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... FSYNC. Note that when the 1CHIP mode, the SDOUTUB pin on header J14 is not connected to the SDOUT pin on the CS4215 and is float- ing. There are two scenario’s that must be addressed when connecting the CDB4215 to a DSP: one is ...
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... P3 43 SCLK 42 FSYNC CS4215 R49 SDOUT 1 16 SDIN 40 15 TSIN 41 6 TSOUT PDN 9 5 CLKOUT 74HTC541 C42 0 RESET U5C IN4148 PIO0 36 37 PIO1 M/S SLAVE 1 13 OEB OEA R43 1 k 74HCT243 R44 1 k ...
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... The CDB4215 can accommodate all clocking modes supported by the CS4215. A CLKIN BNC, as shown in Figure 5 allows the CLKIN pin on the CS4215 to be used as the master clock source. The two crystals listed in the CS4215 data sheet are also provided and support all the audio and multimedia standard sample frequencies ...
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Figure 6. CDB4215 Board Silkscreen (Not to Scale) 46 CDB4215 DS76DB3 ...
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Figure 7. CDB4215 Compont Side Layout (Not to Scale) DS76DB3 CDB4215 47 ...
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Figure 8. CDB4215 Solder Side Layout (Not to Scale) 48 CDB4215 DS76DB3 ...
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D2/E2 44 pin PLCC MILLIMETERS E DIM MIN A 4.20 A1 2.29 B 0.33 D/E 17.40 D1/E1 16.51 D2/E2 14.99 e 1.19 A NO. OF TERMINALS INCHES NOM MAX MIN NOM MAX 4.45 4.57 ...
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MILLIMETERS MIN NOM DIM - 0. 0.14 0.20 C 0.40 0.51 D 15.70 16.00 D1 13.90 14.00 E 15.70 16.00 E1 13.90 14.00 e 0.375 0.5 L 0.30 0.51 0° ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...