MC68HC912B32 Freescale Semiconductor, Inc, MC68HC912B32 Datasheet

no-image

MC68HC912B32

Manufacturer Part Number
MC68HC912B32
Description
Interfacing the MC68HC912B32 to an LCD Module
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32-CFU8
Quantity:
6
Part Number:
MC68HC912B32CFU8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC912B32CFU8
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC68HC912B32CFUE8
Manufacturer:
FREESCALE
Quantity:
2 005
Part Number:
MC68HC912B32CFUE8
Manufacturer:
FREESCALE
Quantity:
2 005
Company:
Part Number:
MC68HC912B32CFUE8
Quantity:
7
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
M68HC12B Family
Data Sheet
M68HC12
Microcontrollers
M68HC12B
Rev. 9.1
07/2005
freescale.com

Related parts for MC68HC912B32

MC68HC912B32 Summary of contents

Page 1

M68HC12B Family Data Sheet M68HC12 Microcontrollers M68HC12B Rev. 9.1 07/2005 freescale.com ...

Page 2

...

Page 3

... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...

Page 4

Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Revision Date Level Figure 1-7. BDM Tool Connector — Added NC ...

Page 5

List of Chapters Chapter 1 General Description ...

Page 6

List of Chapters 6 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 7

... RH RL 1.6.2.5 V (MC68HC912B32 and MC68HC912BC32 only 1.6.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.3.1 XTAL and EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1 ...

Page 8

Table of Contents 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

Operating Modes and Resource Mapping 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

Table of Contents 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

Table of Contents 12.5 Using the Output Compare Function to Generate a Square Wave . . . . . . . . . . . . . . . . . . . . . 156 12.5.1 Sample Calculation to ...

Page 13

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 14

Table of Contents 15.5.3 BDLC Stop and CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 15

State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 16

Table of Contents 16.12.4 msCAN12 Bus Timing Register ...

Page 17

BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 18

Table of Contents 18 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 19

... General Description 1.1 Introduction The MC68HC912B32, MC68HC12BE32 and MC68HC(9)12BC32, are 16-bit microcontroller units (MCUs) composed of standard on-chip peripherals. The multiplexed external bus can also operate in an 8-bit narrow mode for interfacing with single 8-bit wide memory in lower-cost systems. There is a slight feature set difference between the four pin-for-pin compatible devices as shown in Table 1-1 ...

Page 20

... MC68HC912B32 and MC68HC(9)12BC32 only: – Each channel fully configurable as either input capture or output compare – Simple pulse-width modulator (PWM) mode – ...

Page 21

... Older device mask sets do not support the slow-mode clock divider feature. This register address is reserved in older devices and provides no function. Mask sets that do not have the slow-mode clock divider feature on the MC68HC912B32 include: G96P, G86W, and H91F. Mask sets that do not have the slow-mode clock divider feature on the MC68HC12BE32 include: H54T and J38M ...

Page 22

... CIRCUITRY × 2 DDRA V DDX × SSX PORT A POWER FOR I/O DRIVERS WIDE BUS NARROW BUS Figure 1-1. Block Diagram for MC68HC912B32 and MC68HC12BE32 22 1-KBYTE RAM 768-BYTE EEPROM CONVERTER CPU12 PERIODIC INTERRUPT COP WATCHDOG CLOCK MONITOR BREAK POINTS TIMER AND ACCUMULATOR PP LITE INTEGRATION ...

Page 23

FLASH EEPROM/ROM V FP BKGD SMODN / TAGHI SINGLE-WIRE BACKGROUND DEBUG MODULE EXTAL XTAL RESET PE0 XIRQ PE1 IRQ/V R/W PE2 LSTRB / TAGLO PE3 PE4 ECLK PE5 IPIPE0 / MODA IPIPE1 / MODB PE6 DBE PE7 × 2 ...

Page 24

General Description 1.5 Ordering Information The M68HC12B-series devices are available in 80-pin quad flat pack (QFP) packaging and are shipped in 2-piece sample packs, 84-piece trays, or 420-piece bricks. Operating temperature range, package type, and voltage requirements are specified when ...

Page 25

... ADDR2 / DATA2 / PB2 20 PORT B Notes: 1. Pin (no connect) on the MC68HC12BE32 narrow mode, high and low data bytes are multiplexed in alternate bus cycles on port A. Figure 1-3. Pin Assignments for MC68HC912B32 and MC68HC12BE32 Devices Freescale Semiconductor PORT DLC MC68HC912B32 80-PIN QFP PORT E M68HC12B Family Data Sheet, Rev ...

Page 26

General Description PORT P PP5 1 PP4 2 PW3 / PP3 3 PW2 / PP2 4 PW1/ PP1 5 PW0/ PP0 6 IOC0 / PT0 7 IOC1 / PT1 8 IOC2 / PT2 ...

Page 27

... Operating voltage and ground for the ATD; allows the supply voltage to be bypassed independently 60 49 Reference voltages for the analog-to-digital converter 50 Programming voltage for the FLASH EEPROM and required supply for normal operation — MC68HC912B32 and 69 MC68HC912BC32 only. Pin connect (NC) on the MC68HC12BE32 and MC68HC12BC32. Table NOTE ...

Page 28

General Description EXTAL MCU Figure 1-5. Common Crystal Connections MCU Figure 1-6. External Oscillator Connections 1.6.3.2 ECLK ECLK is the output connection for the internal bus clock and is used to demultiplex the address and data and is used as ...

Page 29

INTCR). IRQ is always configured to level-sensitive triggering at reset. When the MCU is reset, the IRQ function is masked in the condition code register. This pin is always an input and can always be read. ...

Page 30

General Description 1.6.3.8 ADDR15–ADDR0 and DATA15–DATA0 ADDR15–ADDR0 and DATA15–DATA0 are the external address and data bus pins. They share functions with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded ...

Page 31

Pin Pin Name Number PW3–PW0 3–6 ADDR7–ADDR0 25–18 DATA7–DATA0 ADDR15–ADDR8 46–39 DATA15–DATA8 IOC7–IOC0 16–12, 9–7 PAI 16 AN7–AN0 58–51 DBE 26 MODB, MODA 27, 28 IPIPE1, IPIPE0 27, 28 ECLK 29 RESET 32 EXTAL 33 XTAL 34 LSTRB 35 TAGLO ...

Page 32

... Port T 16–12, 9–7 PT7–PT0 1. Port DLC applies to the MC68HC912B32 and MC68HC12BE32 and PCAN to the MC68HC(9)12BC32. 1.6.4.1 Port A Port A pins are used for address and data in expanded modes. The port data register is not in the address map during expanded and peripheral mode operation. When the map, port A can be read or written at anytime ...

Page 33

A an output; clearing a bit in DDRA makes the corresponding bit in port A an input. The default reset state of DDRA is all 0s. When the PUPA bit in the PUCR register is ...

Page 34

... General Description 1.6.4.4 Port DLC The MC68HC912B32 and MC68HC12BE32 contain the port DLC. Byte data link communications (BDLC) pins can be configured as general-purpose I/O port DLC. When BDLC functions are not enabled, the port has seven general-purpose I/O pins, PDLC6–PDLC0. The port DLC control register (DLCSCR) controls port DLC function. The BDLC function, enabled with the BDLCEN bit, takes precedence over other port functions ...

Page 35

... Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset. For the MC68HC912B32 and MC68HC(9)12BC32, refer to the MC68HC12BE32, refer to Chapter 13 Enhanced Capture Timer (ECT) 1 ...

Page 36

... Pullup PS3–PS2 Port S Pullup PS7–PS4 Port T Pullup (1) Pullup Port DLC/PCAN Port AD None BKGD Pullup 1. Port DLC applies to the MC68HC912B32 and MC68HC12BE32 and PCAN to the MC68HC(9)12BC32. 36 Enable Bit Register Bit Reset (Address) Name State PUCR PUPA Disabled ($000C) PUCR ...

Page 37

... PT0 PDLC0 75 8 PT1 PDLC1 9 74 PT2 PDLC2 73 12 PT3 PDLC3 72 13 PT4 PDLC4 71 14 PT5 PDLC5 70 15 PDLC6 PT6 16 PT7 MC68HC912B32 DD1 DDEX0 DDAD DD0 µ µ µ 1.0 F µ 1.0 F 1 DDEX0 R29 R31 R34 ...

Page 38

... PT1 A11 9 A12 4 PT2 A12 12 A13 28 PT3 A13 13 A14 29 PT4 A14 14 A15 3 PT5 A15 15 2 PT6 A16 16 PT7 FLASH 22 CE GROUND 24 MC68HC912B32 OE 31 PGM R62 AM27C010 DD1 DDX0 DDX1 R3 4 C10 MODA µ µ µ 0.1 F 0.1 F 0.1 F ...

Page 39

Chapter 2 Register Block 2.1 Introduction The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG15–REG11 in the register initialization register (INITRG). INITRG establishes the upper five bits of the ...

Page 40

... See page 91. Reduced Drive Register $000D (RDRIV) See page 92. $000E Reserved $000F Reserved Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. 40 Bit Read: PA7 PA6 PA5 Write: Reset: U ...

Page 41

... Highest Priority I Interrupt Register $001F (HPRIO) See page 71. Breakpoint Control Register 0 $0020 (BRKCT0) See page 301. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: RAM15 RAM14 RAM13 ...

Page 42

... PWM Scale Register 0 $0044 (PWSCAL0) See page 131. PWM Scale Counter Register 0 $0045 (PWSCNT0) See page 131. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. 42 Bit Read: 0 BKDBE BKMBH Write: ...

Page 43

... PWM Channel Duty Register 0 $0050 (PWDTY0) See page 135. PWM Channel Duty Register 1 $0051 (PWDTY1) See page 135. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: Bit 7 Bit 6 Bit 5 ...

Page 44

... ATD Control Register 3 $0063 (ATDCTL3) See page 280. ATD Control Register 4 $0064 (ATDCTL4) See page 281. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. 44 Bit Read: Bit 7 Bit 6 Bit 5 Write: ...

Page 45

... ATD Result Register 1 $0073 (ADRx1L) See page 286. ATD Result Register 2 $0074 (ADRx2H) See page 286. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: S8CM SCAN Write: ...

Page 46

... ATD Result Register 7 $007F (ADRx7L) See page 286. Timer IC/OC Select Register $0080 (TIOS) See page 141. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. 46 Bit Read: Bit 7 Bit 6 Bit 5 Write: ...

Page 47

... Timer Mask Register 1 $008C (TMSK1) See page 146. Timer Mask Register 2 $008D (TMSK2) See page 147. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: FOC7 FOC6 FOC5 ...

Page 48

... Compare 4 Register High (TC4H) See page 150. Timer Input Capture/Output $0099 Compare 4 Register Low (TC4L) See page 150. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. 48 Bit Read: C7F C6F ...

Page 49

... Register 1 (PACN1) See page 178. Pulse Accumulator Count $00A5 Register 0 (PACN0) See page 178. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 10 of 19) Freescale Semiconductor Bit Read: ...

Page 50

... See page 185. 8-Bit Pulse Accumulator Holding $00B2 Register 3 (PA3H) See page 186. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 11 of 19) 50 Bit Read: ...

Page 51

... See page 188. Timer Input Capture Holding $00BE Register 3 (TC3H) See page 188. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 12 of 19) Freescale Semiconductor Bit Read: ...

Page 52

... See page 204. SPI Control Register 2 $00D1 (SP0CR2) See page 205. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 13 of 19) 52 Bit Read: Bit 7 ...

Page 53

... Reserved ↓ $00EF Reserved EEPROM Configuration Register $00F0 (EEMCR) See page 94. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 14 of 19) Freescale Semiconductor Bit Read ...

Page 54

... See page 239. BDLC Analog Roundtrip Delay (2) $00FC Register (BARD) See page 240. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 15 of 19) 54 Bit Read: 1 ...

Page 55

... Identifier Acceptance (3) $0108 Control Register (CIDAC) See page 270. $0109 Reserved ↓ Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 16 of 19) Freescale Semiconductor Bit Read ...

Page 56

... Register 4 (CIDAR4) See page 273. msCAN12 Identifier Acceptance (3) $0119 Register 5 (CIDAR5) See page 273. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 17 of 19) 56 Bit ...

Page 57

... Register (DDRCAN) See page 276. $0140 ↓ $014F $0150 ↓ $015F Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 18 of 19) Freescale Semiconductor Bit Read: AC7 AC6 ...

Page 58

... Register Name $0160 ↓ $016F $0170 ↓ $017F Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 19 of 19) 58 Bit TRANSMIT BUFFER 1 (TX1) TRANSMIT BUFFER 2 (Tx2) = Unimplemented R M68HC12B Family Data Sheet, Rev ...

Page 59

Chapter 3 Central Processor Unit (CPU) 3.1 Introduction The CPU12 is a high-speed, 16-bit processor unit. It has full 16-bit data paths and wider internal registers ( bits) for high-speed extended math instructions. The instruction set is a ...

Page 60

Central Processor Unit (CPU) 3.3 CPU Registers This section describes the CPU registers. 3.3.1 Accumulators A and B Accumulators A and B are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. Bit 7 Read: ...

Page 61

Index Registers X and Y Index registers X and Y are used for indexed addressing. Indexed addressing adds the value in an index register to a constant or to the value in an accumulator to form the effective address ...

Page 62

Central Processor Unit (CPU) 3.3.5 Program Counter The program counter contains the address of the next instruction to be executed. The program counter can also serve as an index register in all indexed addressing modes except autoincrement and autodecrement. Bit ...

Page 63

Data Types The CPU12 supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses A byte is eight bits wide and can be accessed at any byte ...

Page 64

Central Processor Unit (CPU) Table 3-1. Addressing Mode Summary (Continued) Addressing Mode Source Format Indexed-Indirect INST [oprx16,xysp] 16-bit offset Indexed-Indirect D accumulator INST [D,xysp] offset 3.6 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size ...

Page 65

Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would ...

Page 66

Central Processor Unit (CPU) 66 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 67

Chapter 4 Resets and Interrupts 4.1 Introduction Resets and interrupts are exceptions. Each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard ...

Page 68

Resets and Interrupts Vector Interrupt Source Address $FFFE, $FFFF Reset $FFFC, $FFFD COP clock monitor fail reset $FFFA, $FFFB COP failure reset $FFF8, $FFF9 Unimplemented instruction trap $FFF6, $FFF7 SWI $FFF4, $FFF5 XIRQ $FFF2, $FFF3 IRQ $FFF0, $FFF1 Real-time interrupt ...

Page 69

Table 4-2. MC68HC(9)12BC32 Interrupt Vector Map Vector Interrupt Source Address $FFFE, $FFFF Reset $FFFC, $FFFD COP clock monitor fail reset $FFFA, $FFFB COP failure reset $FFF8, $FFF9 Unimplemented instruction trap $FFF6, $FFF7 SWI $FFF4, $FFF5 XIRQ $FFF2, $FFF3 IRQ $FFF0, ...

Page 70

Resets and Interrupts 4.4 Latching of Interrupts XIRQ is always level triggered and IRQ can be selected as a level-triggered interrupt. These level-triggered interrupt pins should be released only during the appropriate interrupt service routine. Generally, the interrupt service routine ...

Page 71

Highest Priority I Interrupt Register Address: $001F Bit 7 Read: 1 Write: Reset: 1 Figure 4-2. Highest Priority I Interrupt Register (HPRIO) Read: Anytime Write: Only if I bit in CCR = 1 (interrupts inhibited) To give a maskable ...

Page 72

Resets and Interrupts 4.6.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 4.7 Effects of Reset When a reset occurs, MCU registers and control bits are changed to ...

Page 73

Other Resources The timer, serial communications interface (SCI), serial peripheral interface (SPI), byte data link controller (BDLC), pulse-width modulator (PWM), analog-to-digital converter (ATD), and MSCAN are off after reset. 4.8 Interrupt Recognition Once enabled, an interrupt request can be ...

Page 74

Resets and Interrupts 74 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 75

Chapter 5 Operating Modes and Resource Mapping 5.1 Introduction The MCU can operate in eight different modes. Each mode has a different default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses ...

Page 76

Operating Modes and Resource Mapping 5.2.1 Normal Operating Modes These modes provide three operating configurations. Background debugging is available in all three modes, but must first be enabled for some operations by means of a BDM command. BDM can then ...

Page 77

Special Peripheral Mode The CPU is not active in this mode. An external master can control on-chip peripherals for testing purposes not possible to change to or from this mode without going through reset. Background debugging should ...

Page 78

Operating Modes and Resource Mapping Precedence 5.4 Mode and Resource Mapping Registers This section describes the mode and resource mapping registers. 5.4.1 Mode Register The mode register (MODE) controls the MCU operating mode and various configuration options. This register is ...

Page 79

ESTR — E Clock Stretch Enable Bit ESTR determines if the E clock behaves as a simple free-running clock bus control signal that is active only for external bus cycles. ESTR is always 1 in expanded modes ...

Page 80

Operating Modes and Resource Mapping 5.4.2 Register Initialization Register After reset, the 512-byte register block resides at location $0000 but can be reassigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal registers is controlled by ...

Page 81

... The 32-Kbyte FLASH EEPROM/ROM can be mapped to either the upper or lower half of the 64-Kbyte address space. When mapping conflicts occur, registers, RAM, and EEPROM have priority over FLASH EEPROM. Only the MC68HC912B32 contains FLASH EEPROM. The MC68HC12BE32 contains ROM. To use memory expansion, the part must be operated in one of the expanded modes. ...

Page 82

Operating Modes and Resource Mapping Address: $0013 Bit 7 Read: 0 NDRF Write: Reset states: Expanded 0 modes: Single-chip 0 modes: Figure 5-5. Miscellaneous Mapping Control Register (MISC) Read: Anytime Write: Once in normal modes; anytime in special modes NDRF ...

Page 83

MAPROM — FLASH EEPROM/ROM Map Bit This bit determines the location of the on-chip FLASH EEPROM/ROM. In expanded modes reset single-chip modes reset ROMON is 0, this bit has no ...

Page 84

Operating Modes and Resource Mapping 84 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 85

Chapter 6 Bus Control and Input/Output (I/O) 6.1 Introduction Internally, the MCU has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or 16 bits. There are cases where 8-bit ...

Page 86

Bus Control and Input/Output (I/O) be set. In this special case of expanded mode and EME set, the port E data register (PORTE) and port E data direction register (DDRE) are removed from the on-chip memory map and become external ...

Page 87

Port B Data Register Address: $0001 Bit 7 Read: PB7 Write: Reset: Alternate functions: ADDR7 Expanded wide and peripheral: DATA7 Expanded narrow: ADDR7 Figure 6-3. Port B Data Register (PORTB) Read: Anytime, if register is in the map Write: ...

Page 88

Bus Control and Input/Output (I/O) 6.3.5 Port E Data Register Address: $0008 Bit 7 Read: PE7 Write: Reset: 0 Alternate function: DBE Figure 6-5. Port E Data Register (PORTE) Read: Anytime, if register is in the map Write: Anytime, if ...

Page 89

PE1 and PE0 are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be read regardless of whether the alternate interrupt functions are enabled. This register is not in the map in peripheral mode and ...

Page 90

Bus Control and Input/Output (I/O) CGMTE — CGM Test Output Enable Normal: Write once Special: Write anytime except the first time. This bit is read at anytime PE6 is a test signal output from the CGM module (no ...

Page 91

Pullup Control Register Address: $000C Bit 7 Read: 0 Write: Reset Unimplemented Figure 6-8. Pullup Control Register (PUCR) Read: Anytime, if register is in the map Write: Anytime, if register is in the map These bits select ...

Page 92

Bus Control and Input/Output (I/O) 6.3.9 Reduced Drive of I/O Lines Address: $000D Bit 7 Read: 0 Write: Reset Unimplemented Figure 6-9. Reduced Drive of I/O Lines (RDRIV) Read: Anytime, if register is in the map Write: Once ...

Page 93

Chapter 7 EEPROM 7.1 Introduction The MCU is electrically erasable, programmable read-only memory (EEPROM) serves as a 768-byte non-volatile memory which can be used for frequently accessed static data or as fast access program code. The MCU’s EEPROM is arranged ...

Page 94

EEPROM At bus frequencies below 1 MHz, the RC clock must be turned on for program/erase. Figure 7-1. EEPROM Block Protect Mapping 7.3 EEPROM Control Registers This section describes the EEPROM control registers. 7.3.1 EEPROM Module Configuration Register Address: $00F0 ...

Page 95

EEPROM Block Protect Register Address: $00F1 Bit 7 Read: 1 Write: Reset: 1 Figure 7-3. EEPROM Block Protect Register (EEPROT) The EEPROM block protect register (EEPROT) prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 ...

Page 96

EEPROM MARG — Program and Erase Voltage Margin Test Enable Bit 0 = Normal operation 1 = Program and erase margin test This bit is used to evaluate the program/erase voltage margin. EECPD — Charge Pump Disable Bit 0 = ...

Page 97

If BYTE = 1 and test mode is not enabled, only the location specified by the address written to the programming latches will be erased. The operation will be a byte or an aligned word erase depending on the size ...

Page 98

EEPROM 98 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 99

... Chapter 8 FLASH EEPROM 8.1 Introduction The 32-Kbyte FLASH EEPROM module for the MC68HC912B32 and MC68HC912BC32 serves as electrically erasable and programmable, non-volatile ROM emulation memory. The module can be used for program code that must either execute at high speed or is frequently executed, such as operating system kernels and standard subroutines can be used for static data which is read frequently ...

Page 100

FLASH EEPROM 8.3.1 FLASH EEPROM Lock Control Register Address: $00F4 Bit 7 Read: 0 Write: Reset: 0 Figure 8-1. FLASH EEPROM Lock Control Register (FEELCK) In normal modes, the LOCK bit can be written only once after reset. LOCK — ...

Page 101

GADR — Gate/Drain Stress Test Select Bit 0 = Selects the drain stress circuitry 1 = Selects the gate stress circuitry HVT — Stress Test High Voltage Status Bit 0 = High voltage not present during stress test 1 = ...

Page 102

FLASH EEPROM 8.3.4 FLASH EEPROM Control Register Address: $00F7 Bit 7 Read: 0 Write: Reset: 0 Figure 8-4. FLASH EEPROM Control Register (FEECTL) This register controls the programming and erasure of the FLASH EEPROM. FEESWAI — FLASH EEPROM Stop in ...

Page 103

FLASH EEPROM module control registers may be read or written while ENPE is asserted. If ENPE is asserted and LAT is negated on the same write access, no programming or erasure will be performed. Table 8-1. Effects of ENPE, LAT, ...

Page 104

FLASH EEPROM 8.4.3.2 Program/Erase Verification When programming or erasing the FLASH EEPROM array, a special verification method is required to ensure that the program/erase process is reliable and also to provide the longest possible life expectancy. This method requires stopping ...

Page 105

Programming the FLASH EEPROM Programming the FLASH EEPROM is accomplished by this step-by-step procedure. The V must be at the proper level prior to executing step 4 the first time. 1. Apply program/erase voltage to the V 2. Clear ...

Page 106

FLASH EEPROM GET NEXT ADDRESS/DATA 106 START PROG TURN CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER ( CLEAR ERAS SET LAT WRITE DATA TO ADDRESS SET ENPE DELAY FOR DURATION OF PROGRAM PULSE (t ) ...

Page 107

Erasing the FLASH EEPROM This sequence demonstrates the recommended procedure for erasing the FLASH EEPROM. The V voltage must be at the proper level prior to executing step 4 the first time. 1. Turn Apply program/erase ...

Page 108

FLASH EEPROM 108 START ERASE TURN CLEAR MARGIN FLAG CLEAR ERASE PULSE COUNTER ( SET ERAS SET LAT WRITE TO ARRAY SET ENPE DELAY FOR DURATION OF ERASE PULSE (t ) EPULSE CLEAR ENPE DELAY ...

Page 109

Program/Erase Protection Interlocks The FLASH EEPROM program and erase mechanisms provide maximum protection from accidental programming or erasure. The voltage required to program/erase the FLASH EEPROM (V is not present, no programming/erasing will occur. Furthermore, the program/erase voltage will ...

Page 110

FLASH EEPROM 110 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 111

Chapter 9 Read-Only Memory (ROM) 9.1 Introduction The MC68HC12BE32 and MC68HC12BC32 contain 32 Kbytes of read-only memory (ROM). The ROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access ...

Page 112

Read-Only Memory (ROM) 112 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 113

... Register $00E0 is reserved in older devices and provides no function. Mask sets that do not have the slow-mode clock divider feature on the MC68HC912B32 include: G96P, G86W, and H91F. Mask sets that do not have the slow-mode clock divider feature on the MC68HC12BE32 include: H54T and J38M. ...

Page 114

Clock Generation Module (CGM) 10.3 Register Map Addr. Register Name Real-Time Interrupt Control $0014 Register (RTICTL) See page 118. Real-Time Interrupt Flag Register $0015 (RTIFLG) See page 119. COP Control Register (COPCTL) $0016 See page 119. Arm/Reset COP Timer $0017 ...

Page 115

OSCILLATOR T1 CLOCK T2 CLOCK T3 CLOCK T4 CLOCK E CLOCK P CLOCK Figure 10-3. Internal Clock Relationships in Normal Run Modes OSCILLATOR T1 CLOCK T2 CLOCK T3 CLOCK T4 CLOCK E CLOCK (1) (G) P CLOCK (1) (G) E ...

Page 116

Clock Generation Module (CGM) 10.5 Slow Mode Divider The slow mode divider is included to deliver a variable bus frequency to the MCU in wait mode. The bus clocks are derived from the constant P clock. The slow clock counter ...

Page 117

Clock Registers This section describes the clock registers. All register addresses shown reflect the reset state. Registers may be mapped to any 2-Kbyte space. 10.7.1 Slow Mode Divider Register Address: $00E0 Bit 7 Read: 0 Write: Reset ...

Page 118

Clock Generation Module (CGM) 10.7.2 Real-Time Interrupt Control Register Address: $0014 Bit 7 Read: RTIE Write: Reset Unimplemented Figure 10-6. Real-Time Interrupt Control Register (RTICTL) Read: Anytime Write: Varies on a bit-by-bit basis RTIE — Real-Time Interrupt Enable ...

Page 119

Real-Time Interrupt Flag Register Address: $0015 Bit 7 Read: RTIF Write: Reset: 0 Figure 10-7. Real-Time Interrupt Flag Register (RTIFLG) RTIF — Real-Time Interrupt Flag Bit This bit is cleared automatically by a write to this register with this ...

Page 120

Clock Generation Module (CGM) FCOP — Force COP Watchdog Reset Bit Writes are not allowed in normal modes; can be written anytime in special modes. If DISR is set, this bit has no effect Normal operation 1 = ...

Page 121

Clock Divider Chains Figure 10-10, Figure 10-11, Figure peripherals: • SCI — Serial peripheral interface • BDLC — Byte data link communications • RTI — Real-time interrupt • COP — Computer operating properly • TIM — Standard timer module ...

Page 122

Clock Generation Module (CGM) P CLOCK REGISTER: TMSK2 BITS: PR2, PR1, AND PR0 TEN 0:0:0 ÷ 2 0:0:1 ÷ 2 0:1:0 ÷ 0:1:1 2 ÷ 2 1:0:0 ÷ 2 1:0:1 ÷ 2 PORT T7 PAEN MCLK REGISTER: TMSK2 BITS: PR2, ...

Page 123

P CLOCK 5-BIT MODULUS COUNTER (PR0-PR4) REGISTER: SP0BR ÷ 2 BITS: SPR2, SPR1, AND SPR0 0:0:0 ÷ 2 0:0:1 ÷ 0:1:0 2 ÷ 2 0:1:1 ÷ 2 1:0:0 ÷ 2 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 Figure 10-13. Clock ...

Page 124

Clock Generation Module (CGM) 124 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 125

Chapter 11 Pulse-Width Modulator (PWM) 11.1 Introduction The pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a combination of one 16-bit and two 8-bit PWM waveforms. Each waveform channel has a programmable ...

Page 126

Pulse-Width Modulator (PWM) CLOCK SOURCE (ECLK) GATE CLOCK EDGE SYNC PWENx PPOL = 0 PPOL = 1 Figure 11-1. Block Diagram of PWM Left-Aligned Output Channel CLOCK SOURCE (ECLK) GATE CLOCK EDGE SYNC PWENx PPOL = 0 PPOL = 1 ...

Page 127

PSBCK PSBCK IS BIT 0 OF PWCTL REGISTER. INTERNAL SIGNAL LIMBDM THE MCU IS IN BACKGROUND DEBUG MODE. LIMBDM ECLK 0:0:0 ÷ 2 0:0:1 ÷ 0:1:0 2 ÷ 0:1:1 2 ÷ 1:0:0 2 ÷ 1:0:1 2 ÷ ...

Page 128

Pulse-Width Modulator (PWM) 11.2 PWM Register Descriptions This section provides descriptions of the PWM registers. 11.2.1 PWM Clocks and Concatenate Register Address: $0040 Bit 7 Read: CON23 Write: Reset: 0 Figure 11-4. PWM Clocks and Concatenate Register (PWCLK) Read: Anytime ...

Page 129

PWM Clock Select and Polarity Register Address: $0041 Bit 7 Read: PCLK3 Write: Reset: 0 Figure 11-5. PWM Clock Select and Polarity Register (PWPOL) Read: Anytime Write: Anytime PCLK3 — PWM Channel 3 Clock Select Bit 0 = Clock ...

Page 130

Pulse-Width Modulator (PWM) 11.2.3 PWM Enable Register Address: $0042 Bit 7 Read: 0 Write: Reset Unimplemented Figure 11-6. PWM Enable Register (PWEN) Read: Anytime Write: Anytime Setting any of the PWENx bits causes the associated port P line ...

Page 131

PWM Prescale Counter Address: $0043 Bit 7 Read: 0 Write: Reset Unimplemented Figure 11-7. PWM Prescale Counter (PWPRES) Read: Anytime Write: Only in special mode (SMOD = 1) PWPRES is a free-running 7-bit counter. 11.2.5 PWM Scale ...

Page 132

Pulse-Width Modulator (PWM) 11.2.7 PWM Scale Register 1 Address: $0046 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 11-10. PWM Scale Register 1 (PWSCAL1) Read: Anytime Write: Anytime A write causes the scaler counter PWSCNT1 to load the PWSCAL1 ...

Page 133

PWM Channel Counters 0–3 Address: $0048 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 11-12. PWM Channel Counter 0 (PWCNT0) Address: $0049 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 11-13. PWM Channel Counter 1 (PWCNT1) Address: ...

Page 134

Pulse-Width Modulator (PWM) 11.2.10 PWM Channel Period Registers 0–3 Address: $004C Bit 7 Read: Bit 7 Write: Reset: 1 Figure 11-16. PWM Channel Period Register 0 (PWPER0) Address: $004D Bit 7 Read: Bit 7 Write: Reset: 1 Figure 11-17. PWM ...

Page 135

PWM Channel Duty Registers 0–3 Address: $0050 Bit 7 Read: Bit 7 Write: Reset: 1 Figure 11-20. PWM Channel Duty Register 0 (PWDTY0) Address: $0051 Bit 7 Read: Bit 7 Write: Reset: 1 Figure 11-21. PWM Channel Duty Register ...

Page 136

Pulse-Width Modulator (PWM) 11.2.12 PWM Control Register Address: $0054 Bit 7 Read: 0 Write: Reset: 0 Figure 11-24. PWM Control Register (PWCTL) Read: Anytime Write: Anytime PSWAI — PWM Halts While in Wait Mode Bit 0 = Continue PWM main ...

Page 137

PWM Special Mode Register Address: $0055 Bit 7 Read: DISCR Write: Reset: 0 Figure 11-25. PWM Special Mode Register (PWTST) Read: Anytime Write: Only in special mode (SMODN = 0) These bits are available only in special mode and ...

Page 138

Pulse-Width Modulator (PWM) 11.2.15 Port P Data Direction Register Address: $0057 Bit 7 Read: DDP7 Write: Reset: 0 Figure 11-27. Port P Data Direction Register (DDRP) Read: Anytime Write: Anytime DDRP determines pin direction of port P when used for ...

Page 139

PWM Period Calculation These parameters were used to calculate the high-time values shown in Table 11-3: • Period = $1000 (Hex) = 4096 (decimal) • E clock = 8 MHz • Prescaler = 4 • Frequency = (8 MHz) ...

Page 140

Pulse-Width Modulator (PWM) 11.4.3 Code Listing A comment line is deliminted by a semi-colon. If there is no code before comment, an “;” must be placed in the first column to avoid assembly errors. INCLUDE 'EQUATES.ASM' ; ---------------------------------------------------------------------- ; MAIN ...

Page 141

... Chapter 12 Standard Timer (TIM) 12.1 Introduction The standard timer module (TIM) for the MC68HC912B32 and MC68HC(9)12BC32 consists of a 16-bit software-programmable counter driven by a prescaler. It contains eight complete 16-bit input capture/output compare channels and one 16-bit pulse accumulator. See The MC68HC12BE32 contains an enhanced capture timer (ECT). The timer on the MC68HC12BE32 is backward compatible with code used on the MC68HC912B32 ...

Page 142

Standard Timer (TIM) 12.3 Block Diagram PRESCALER DIVIDE CTL TIMER COUNT REGISTER MODULE CLOCK PRESCALER PR2, PR1, PR0 INPUT CAPTURE/ OUTPUT COMPARE REGISTER PULSE ACCUMULATOR INT 142 CONTROL REGISTERS TCRE COUNTER RESET TCNT TCNT RESET 16-BIT COUNTER OC7 BUFFER LATCH ...

Page 143

Timer Compare Force Register Address: $0081 Bit 7 Read: FOC7 Write: Reset: 0 Figure 12-3. Timer Compare Force Register (CFORC) Read: Anytime, always returns $00 (1 state is transient) Write: Anytime FOC7–FOC0 — Force Output Compare Action Bits for ...

Page 144

Standard Timer (TIM) 12.3.4 Timer Count Register Address: $0084 Bit 7 Read: Bit 15 Write: Reset: 0 Address: $0085 Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 12-6. Timer Count Register (TCNT) Read: Anytime Write: Has no ...

Page 145

TSBCK — Timer Stops While in Background Mode Bit 0 = Allows timer to continue running while in background mode 1 = Disables timer when MCU is in background mode; useful for emulation TFFCA — Timer Fast Flag Clear All ...

Page 146

Standard Timer (TIM) Address: $008A Bit 7 Read: EDG7B Write: Reset: 0 Figure 12-10. Timer Control Register 3 (TCTL3) Address: $008B Bit 7 Read: EDG3B Write: Reset: 0 Figure 12-11. Timer Control Register 4 (TCTL4) Read: Anytime Write: Anytime EDGnB ...

Page 147

C7I–C0I — Input Capture/Output Compare x Interrupt Enable Bits Address: $008D Bit 7 Read: TOI Write: Reset Unimplemented Figure 12-13. Timer Interrupt Mask 2 Register (TMSK2) Read: Anytime Write: Anytime TOI — Timer Overflow Interrupt Enable Bit 0 ...

Page 148

Standard Timer (TIM) 12.3.8 Timer Interrupt Flag Registers Address: $008E Bit 7 Read: C7F Write: Reset: 0 Figure 12-14. Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism; set bits cause corresponding bits to be cleared ...

Page 149

Timer Input Capture/Output Compare Registers Address: $0090 Bit 7 Read: Bit 15 Write: Reset: 0 Address: $0091 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 12-16. Timer Input Capture/Output Compare Register 0 (TC0) Address: $0092 Bit 7 Read: ...

Page 150

Standard Timer (TIM) Address: $0096 Bit 7 Read: Bit 15 Write: Reset: 0 Address: $0097 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 12-19. Timer Input Capture/Output Compare Register 3 (TC3) Address: $0098 Bit 7 Read: Bit 15 Write: ...

Page 151

Address: $009C Bit 7 Read: Bit 15 Write: Reset: 0 Address: $009D Bit 7 Read: Bit 7 Write: Reset: 0 Figure 12-22. Timer Input Capture/Output Compare Register 6 (TC6) Address: $009E Bit 7 Read: Bit 15 Write: Reset: 0 Address: ...

Page 152

Standard Timer (TIM) PAEN — Pulse Accumulator System Enable Bit 0 = Pulse accumulator system disabled 1 = Pulse accumulator system enabled PAEN is independent from TEN. PAMOD — Pulse Accumulator Mode Bit 0 = Event counter mode 1 = ...

Page 153

Pulse Accumulator Flag Register Address: $00A1 Bit 7 Read: 0 Write: Reset: 0 Figure 12-25. Pulse Accumulator Flag Register (PAFLG) Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT ...

Page 154

Standard Timer (TIM) 12.3.13 Timer Test Register Address: $00AD Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-27. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMODN = 0) TCBYP — Timer Divider Chain Bypass ...

Page 155

Data Direction Register for Timer Port Address: $00AF Bit 7 Read: DDT7 Write: Reset: 0 Figure 12-29. Data Direction Register for Timer Port (DDRT) Read: Anytime Write: Anytime 0 = Configures the corresponding I/O pin for input only 1 ...

Page 156

Standard Timer (TIM) 12.5 Using the Output Compare Function to Generate a Square Wave This timer exercise is intended to utilize the output compare function to generate a square wave of predetermined duty cycle and frequency. Square wave frequency 1000 ...

Page 157

MAIN PROGRAM ; ---------------------------------------------------------------------- ORG $7000 ; MAIN: BSR TIMERINIT ; BSR SQWAVE DONE: BRA DONE ;* ----------------------------------------------------------------- ;* Subroutine TIMERINIT: Initialize Timer for Output Compare on OC2 ;* ----------------------------------------------------------------- TIMERINIT: CLR TMSK1 MOVB #$02,TMSK2 ; ; MOVB ...

Page 158

Standard Timer (TIM) 158 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 159

... Four user selectable delay counters for input noise immunity increase • Main timer prescaler extended to 7-bit This section describes the standard timer found on the MC68HC912B32 as well as the additional features found on the MC68HC12BE32. 13.2 Basic Timer Overview The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform ...

Page 160

Enhanced Capture Timer (ECT) Module The 16-bit modulus down-counter can control the transfer of the IC register’s contents and the pulse accumulators to the respective holding registers for a given period, every time the count reaches 0. The modulus down-counter ...

Page 161

PRESCALER P CLOCK PIN PT0 LOGIC PIN PT1 LOGIC PIN PT2 LOGIC PIN PT3 LOGIC PIN PT4 EDG4 LOGIC EDG0 PIN PT5 LOGIC EDG5 EDG1 PIN PT6 LOGIC EDG6 EDG2 PIN PT7 EDG7 LOGIC EDG3 ...

Page 162

Enhanced Capture Timer (ECT) Module ÷1, 2, ..., 128 PRESCALER P CLOCK PIN PT0 LOGIC PIN PT1 LOGIC PIN PT2 LOGIC PIN PT3 LOGIC PIN PT4 LOGIC EDG4 EDG0 PIN PT5 LOGIC EDG5 EDG1 PIN PT6 LOGIC EDG6 EDG2 PIN ...

Page 163

Pulse Accumulators Four 8-bit pulse accumulators with four 8-bit holding registers are associated with the four IC buffered channels. See Figure 13-3. A pulse accumulator counts the number of active edges at the input of its channel. The user ...

Page 164

Enhanced Capture Timer (ECT) Module PT0 EDGE DETECTOR PT1 EDGE DETECTOR PT2 EDGE DETECTOR PT3 EDGE DETECTOR Figure 13-3. 8-Bit Pulse Accumulators Block Diagram 164 LOAD HOLDING REGISTER AND RESET PULSE ACCUMULATOR EDG0 DELAY COUNTER EDG1 DELAY COUNTER EDG2 DELAY ...

Page 165

CLK1 CLK0 PRESCALED CLOCK FROM TIMER INTERRUPT 8-BIT PAC3 (PACN3) INTERRUPT 8-BIT PAC1 (PACN1) Figure 13-4. 16-Bit Pulse Accumulators Block Diagram Freescale Semiconductor TIMCLK (TIMER CLOCK) 4:1 MUX CLOCK SELECT (PAMOD) 8-BIT PAC2 (PACN2) PACA 8-BIT PAC0 (PACN0) PACB M68HC12B ...

Page 166

Enhanced Capture Timer (ECT) Module 13.4.1 Timer Input Capture/Output Compare Select Register Address: $0080 Bit 7 Read: IOS7 Write: Reset: 0 Figure 13-5. Timer Input Capture/Output Compare Read: Anytime Write: Anytime IOS[7:0] — Input Capture or Output Compare Channel Configuration ...

Page 167

OC7M[7:0] Bits The bits of OC7M correspond bit-for-bit with the timer port (PORTT) bits. Setting the OC7Mn will set the corresponding port output port regardless of the state of the DDRTn bit, when the corresponding TIOSn bit ...

Page 168

Enhanced Capture Timer (ECT) Module 13.4.5 Timer Count Registers Address: $0084 Bit 7 Read: Bit 15 Write: Reset: 0 Address: $0085 Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 13-10. Timer Count Registers (TCNT) Read: Anytime Write: ...

Page 169

TSWAI — Timer Module Stops While in Wait Bit TSWAI also affects pulse accumulators and modulus down counters Allows the timer module to continue running during wait 1 = Disables the timer module when the MCU is in ...

Page 170

Enhanced Capture Timer (ECT) Module Table 13-1. Compare Result Output Action OMn operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0, respectively, the ...

Page 171

Timer Interrupt Mask Registers Address: $008C Bit 7 Read: C7I Write: Reset: 0 Figure 13-16. Timer Interrupt Mask 1 Register (TMSK1) Read: Anytime Write: Anytime C7I–C0I — Input Capture/Output Compare x Interrupt Enable Bits The bits in TMSK1 correspond ...

Page 172

Enhanced Capture Timer (ECT) Module PR2, PR1, and PR0 — Timer Prescaler Select Bits These three bits specify the number of ÷2 stages that are to be inserted between the module clock and the main timer counter. See next synchronized ...

Page 173

EDGE PTN DETECTOR Figure 13-19. C3F–C0F Interrupt Flag Setting Address: $008F Bit 7 Read: TOF Write: Reset: 0 Figure 13-20. Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be ...

Page 174

Enhanced Capture Timer (ECT) Module Address: $0092–$0093 Bit 7 Read: Bit 15 Write: Reset: 0 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-22. Timer Input Capture/Output Compare Register 1 (TC1) Address: $0094–$0095 Bit 7 Read: Bit 15 Write: ...

Page 175

Address: $009A–$009B Bit 7 Read: Bit 15 Write: Reset: 0 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-26. Timer Input Capture/Output Compare Register 5 (TC5) Address: $009C–$009D Bit 7 Read: Bit 15 Write: Reset: 0 Bit 7 Read: ...

Page 176

Enhanced Capture Timer (ECT) Module 13.4.11 16-Bit Pulse Accumulator A Control Register Address: $00A0 Bit 7 Read: 0 Write: Reset Unimplemented Figure 13-29. 16-Bit Pulse Accumulator A Control Register (PACTL) Read: Anytime Write: Anytime Sixteen-bit pulse accumulator A ...

Page 177

CLK1 and CLK0 — Clock Select Bits CLK1 CLK0 the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to ...

Page 178

Enhanced Capture Timer (ECT) Module 13.4.13 Pulse Accumulators Count Registers Address: $00A2 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-31. Pulse Accumulator Count Register 3 (PACN3) Address: $00A3 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-32. ...

Page 179

The two 8-bit pulse accumulators, PAC1 and PAC0, are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL, $B0) the PACN1 and PACN0 register contents are, respectively, the high and low bytes ...

Page 180

Enhanced Capture Timer (ECT) Module MCEN — Modulus Down-Counter Enable Bit When MCEN = 0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled Modulus counter disabled. 1 ...

Page 181

Input Control Pulse Accumulators Control Register Address: $00A8 Bit 7 Read: 0 Write: Reset: 0 Figure 13-37. Input Control Pulse Accumulators Control Register (ICPACR) Read: Anytime Write: Anytime The 8-bit pulse accumulators, PAC3 and PAC2, can be enabled only ...

Page 182

Enhanced Capture Timer (ECT) Module 13.4.18 Input Control Overwrite Register Address: $00AA Bit 7 Read: NOVW7 Write: Reset: 0 Figure 13-39. Input Control Overwrite Register (ICOVW) Read: Anytime Write: Anytime An IC register is empty when it has been read ...

Page 183

... The 8-bit pulse accumulators are cleared. 13.4.20 Timer Test Register Address: $00AD Bit 7 Read: 0 Write: Reset Unimplemented 1. Available only on MC68HC912B32 devices. Figure 13-41. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMOD = 1) Freescale Semiconductor Figure 13-19. In all other input capture cases, the 13.3.1.2 Buffered ...

Page 184

Enhanced Capture Timer (ECT) Module TCBYP — Main Timer Divider Chain Bypass Bit 0 = Normal operation 1 = For testing only. The 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed. The clock ...

Page 185

DDT[7:0] — Data Direction Bits for Timer Port The timer forces the I/O state output for each timer port line associated with an enabled output compare. In these cases the data direction bits will not be changed, ...

Page 186

Enhanced Capture Timer (ECT) Module PBOVF — Pulse Accumulator B Overflow Flag This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to $0000 or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to $00. This ...

Page 187

Modulus Down-Counter Count Registers Address: $00B6 Bit 7 Read: Bit 15 Write: Reset: 1 Address: $00B7 Bit 7 Read: Bit 7 Write: Reset: 1 Figure 13-50. Modulus Down-Counter Count Registers (MCCNT) Read: Anytime Write: Anytime A full access for ...

Page 188

Enhanced Capture Timer (ECT) Module Address: $00BA Bit 7 Read: Bit 15 Write: Reset: 0 Address: $00BB Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-52. Timer Input Capture Holding Register 1 (TC1H) Address: $00BC Bit 7 Read: Bit ...

Page 189

Timer and Modulus Counter Operation in Different Modes STOP Timer and modulus counter are off since clocks are stopped. BGDM Timer and modulus counter keep on running unless bit 5, TSBCK, of TSCR is set to 1. See Timer ...

Page 190

Enhanced Capture Timer (ECT) Module 190 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...

Page 191

Chapter 14 Serial Interface 14.1 Introduction • The serial interface of the MCU consists of two independent serial input/output (I/O) subsystems: • Serial communication interface (SCI) • Serial peripheral interface (SPI) Each serial pin shares function with the general-purpose port ...

Page 192

Serial Interface 14.2 Serial Communication Interface (SCI) The SCI on the MCU is an NRZ format (one start, eight or nine data, and one stop bit) asynchronous communication system with independent internal baud rate generation circuitry and an SCI transmitter ...

Page 193

Data Format The serial data format requires these conditions: • An idle-line in the high state before transmission or reception of a message • A start bit (logic 0), transmitted or received, that indicates the start of each character ...

Page 194

Serial Interface 14.2.3 SCI Register Descriptions Control and data registers for the SCI subsystem are described here. The memory address indicated for each register is the default address that is in use after reset. The entire 512-byte register block can ...

Page 195

SCI Control Register 1 Address: $00C2 Bit 7 Read: LOOPS Write: Reset: 0 Figure 14-5. SCI Control Register 1 (SC0CR1) Read: Anytime Write: Anytime LOOPS — SCI LOOP Mode/Single-Wire Mode Enable Bit 0 = SCI transmit and receive sections ...

Page 196

Serial Interface RSRC — Receiver Source Bit When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver Receiver input connected to the transmitter internally (not TXD pin Receiver input connected to ...

Page 197

SCI Control Register 2 Address: $00C3 Bit 7 Read: TIE Write: Reset: 0 Figure 14-6. SCI Control Register 2 (SC0CR2) Read: Anytime Write: Anytime TIE — Transmit Interrupt Enable Bit 0 = TDRE interrupts disabled 1 = SCI interrupt ...

Page 198

Serial Interface 14.2.3.4 SCI Status Register 1 Address: $00C4 Bit 7 Read: TDRE Write: Reset: 1 Figure 14-7. SCI Status Register 1 (SC0SR1) Read: Anytime; used in auto clearing mechanism Write: Has no meaning or effect The bits in these ...

Page 199

OR — Overrun Error Flag New byte is ready to be transferred from the receive shift register to the receive data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until this ...

Page 200

Serial Interface 14.2.3.6 SCI Data Register Address: $00C6 Bit 7 Read: R8 Write: Reset: U Figure 14-9. SCI Data Register High (SC0DRH) Address: $00C7 Bit 7 Read: R7T7 Write: Reset: Figure 14-10. SCI Data Register Low (SC0DRL) Read: Anytime Write: ...

Related keywords