ADM7001 Infineon Technologies AG, ADM7001 Datasheet
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... Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... Single Ethernet 10/100M PHY Revision History: 2005-11-25, Rev. 1.07 Previous Version: Page/Date Subjects (major changes since last revision) 2003-03-05 Rev. 1.0: First release of ADM7001 2003-04-08 Rev. 1.01: Register Modifications and Pin updates 2003-07-24 Rev. 1.02: The following sections were updated: 1.2, 1.3, 2.1, 2.2.1, 2.2.5, 2.2.7, 2.2.8, 2.2.8, 4.1, 4.2.3-4, 4.2.11-12, 4.3.4, 4.3.9, 4.3.11, 4.3.12, & 4.3.16 2003-07-30 Rev. 1.03: Updated section 6.2 2003-09-15 Rev. 1.04: Updated Section 2.2.5, 2.2.8, & ...
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... Auto Negotiation and Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 Reduced Media Independent Interface (RMII 3.2.2 Receive Path for 100M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.3 Receive Path for 10M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.4 Transmit Path for 100M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.5 Transmit Path for 10M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.6 Media Independent Interface (MII Data Sheet 4 ADM7001/X Data sheet Table of Contents 16 Rev. 1.07, 2005-11-25 ...
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... MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.1 RXCLK Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4.3 TXCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.4.4 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5 GPSI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.1 GPSI Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.2 GPSI Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6 Serial Management Interface (MDC/MDIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.7 Power On Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data Sheet 5 ADM7001/X Data sheet Table of Contents Rev. 1.07, 2005-11-25 ...
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... TXCLK Output Timing 82 Figure 33 MII Transmit Timing 83 Figure 34 GPSI Receive Timing 84 Figure 35 GPSI Transmit Timing 84 Figure 36 Serial Management Interface (MDC/MDIO) Timing 85 Figure 37 Power On Configuration Timing 86 Figure 38 ADM7001/X,Low Profile Quad Flat Package (LQFP) 87 Data Sheet 6 ADM7001/X Data sheet List of Figures Rev. 1.07, 2005-11-25 ...
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... TXCLK Output Timing 82 Table 34 MII Transmit Timing 83 Table 35 GPSI Receive Timing 84 Table 36 GPSI Transmit Timing 85 Table 37 Serial Management Interface (MDC/MDIO) Timing 85 Table 38 Power On Configuration Timing 86 Table 39 Dimensions for 100 Pin LQFP Package 88 Data Sheet 7 ADM7001/X Data sheet List of Tables Rev. 1.07, 2005-11-25 ...
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... Overview The ADM7001 single chip one port 10/100M PHY, which is designed for today’s low cost and low power dual speed application. The ADM7001X is the environmentally friendly “green” package version. It supports auto sensing 10/100 Mbps ports with on-chip clock recovery and base line wander correction including integrated MLT-3 functionality for 100 Mbps operation, and also supports Manchester Code Converter with on chip clock recovery circuitry for 10 Mbps functionality ...
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... Built-in Clock Generator and Power On Reset Signal to save system cost. • 48 LQFP without regulator. • Supports Power saving function. • Supports Parallel LED output. Data Sheet 9 ADM7001/X Data sheet Product Overview Rev. 1.07, 2005-11-25 ...
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... Block Diagram Figure 1 ADM7001/X Block Diagram Data Sheet 10 ADM7001/X Data sheet Product Overview Rev. 1.07, 2005-11-25 ...
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... Note: For those pins, which have multiple functions, pin name is separated by slash ("/"). If not specified, all signals are default to digital signals. Please refer to abbreviations. Data Sheet ADM7001L/T 48 Pin Table 1Pin Type Descriptions' for an explanation of pin 11 ADM7001/X Data sheet Interface Description VCC25OUT(CORE) GNDPLL VCCPLL_25 GNDTR VCCA_25 Rev. 1.07, 2005-11-25 ...
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... Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high (identical to output with no type attribute). OD/PP Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with the OD attribute output with the PP attribute. ST Schmitt-Trigger characteristics TTL TTL characteristics Data Sheet 12 ADM7001/X Data sheet Interface Description Rev. 1.07, 2005-11-25 ...
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... Twisted Pair Transmit Output Positive AI/O Twisted Pair Transmit Output Negative AI/O Twisted Pair Receive Input Positive AI/O Twisted Pair Receive Input Negative AI Fiber Enable Value on this pin will be latched by ADM7001/X/X during power on reset as fiber select signal Twisted Pair Mode Fiber Optic Mode B 100BASE-FX Signal Detect. ...
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... Pin or Ball Name No GNDO 2, 37 GNDIK 1, 18 VCCO_25 7 VCCIK_25 Data Sheet Pin Buffer Function Type Type D,GND Ground used by 3.3 V I/O. D,GND Ground used by Core. D,PWR 2.5V Power used by Digital I/O Pad. D,PWR 2.5 V Power used by Core 14 ADM7001/X Data sheet Interface Description Rev. 1.07, 2005-11-25 ...
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... VCCA_25 32 VCCPLL_25 Data Sheet Pin Buffer Function Type Type A,PWR 3.3V Power input to ADM7001/X and used by built-in 3 2.5 V regulator. A,PWR 2.5V Power output by ADM7001/X. Maximum Supply current from this pin is 200 mA A,GND Analog Ground Pad A,PWR Analog 2.5 V Power A,PWR Analog 2.5 V Power used by Clock Generator module. ...
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... Clock output in 100BASE-X mode and 2.5M Clock output for 10BASE-T mode. This clock is continuously driven output and generated from XI. Before Speed is recognized, this pin drives out continuous 25M clock N/A GPSI Transmit Clock. 10M Clock output in 10BASE-T mode. 16 ADM7001/X Data sheet Interface Description Rev. 1.07, 2005-11-25 ...
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... RMII Mode, left unconnected or pull down externally for normal operation. Serial Transmit Data. TXD0 for the designated port inputs the data that is transmitted and is driven synchronously to TXCLK in 10Mb/s mode. When ADM7001/X is programmed into GPSI mode, TXD[3:1] should be left unconnected or pull down externally for normal operation. I TTL Transmit Enable ...
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... Due to recovered from incoming receive data possible that RXCLK starts running yet RXDV keeps low for a while. During power on reset, there is no receiving clock driven by ADM7001/X RMII 50M Clock Output. This pin outputs continuous 50M clock in RMII mode. To ...
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... RXD Data Sheet Pin Buffer Function Type Type I LVTTL Disable Auto Crossover Function PD Value on this pin will be latched by ADM7001/X to select Auto Cross-Over Function. Note: LVTTL: Low Voltage TTL Level 0 , Enable Auto Crossover Disable Auto Crossover B O 8mA MII Receive Data Valid. ...
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... CRSDV is de-asserted. No Operation in GPSI Mode GPSI Mode Select Value on this pin will be sampled by ADM7001/X during power on reset to form GPSI internal control signal. Together with RMII_EN, these two pins form three possible internal supported by ADM7001/X. RMII_EN GPSI Interface ...
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... Buffer Function Type Type I LVTTL Repeater Mode. PD Value on this pin will be latched by ADM7001/X during power on reset as repeater mode Note: LVTTL: Low Voltage TTL Level 0 , SW/NIC mode, CRS will be asserted according to B RX/TX in half duplex mode REPEATER mode. CRS will be asserted only mode in half duplex operation ...
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... Note: LVTTL: Low Voltage TTL Level LVTTL Management Data Reference Clock. A non-continuous clock input for management usage. ADM7001/X will use this clock to sample data input on MDIO and drive data onto MDIO according to rising edge of this clock. Note: LVTTL: Low Voltage TTL Level LVTTL PHY Address bit 0 ...
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... Type LVTTL Low Power Operation. PU Note: When RESET# is reset to 0 and PWRDOWN# is set to 0, whole ADM7001/X blocks will be disabled ADM7001/X in low power mode operation. All blocks B except the energy detection and crystal oscillator are de- activated ADM7001/X in normal mode operation. B Note: LVTTL: Low Voltage TTL Level LVTTL Industrial Test Pin ...
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... Active low (Note) 100ms (blink 100ms) to indicate that there is transmit or receive activity after Link Up. Keeps high all the time when link is failed. I TTL Recommend 100M Operation. PU This bit is only available in TP mode. Together with ANEN to form speed mode select for ADM7001/X: ANEN SPD100 Mode ...
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... Enable Auto Negotiation B O 8mA Collision LED. Keep high (Note) when ADM7001 full duplex mode and will blink 100 ms when collision condition is detected in half duplex mode. Note: When recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high ...
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... For 100Base-TX operation, the on-chip twisted pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensation circuits detects the incoming signal. ADM7001/X uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable ...
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... The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The ADM7001/X implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application ...
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... Symbol Alignment The symbol alignment circuit in the ADM7001/X determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the descrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. ...
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... The ADM7001/X performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10 Mbits/s link status to form the reportable link status bit in serial management register 1h, and driven to the LNKACT pin ...
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... If this condition is detected, the ADM7001/X will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to receive 5B code-groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become deasserted ...
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... When DIS_ANASDEN_N in register 18 is set to 0, ADM7001/X doesn't support SDP detection in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7001/X uses the data on RXP/RXN to detect consecutive 65 “1” on the receive data (Recovered from RXP/RXN) to determine whether “ ...
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... Collision is detected internal to the MAC, which is generated by an AND function of TXEN and RXDV derived from internal timing recovery circuitry. Note should be taken that due to TXEN and RXDV are asynchronous to each other, COL signal outputted by ADM7001/X is irrelevant to either TXCLK or RXCLK. Data Sheet ...
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... The auto negotiation function within the ADM7001/X can be controlled either by internal register access or by the use of configuration pins are sampled. If disabled, auto negotiation will not occur until software enables bit 12 in register 0 ...
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... The reduced media Independent interface (RMII) is compliant to the RMII consortium’s RMII Rev. 1.2 specification. The REFCLK pin that supplies the 50 MHz reference clock to the ADM7001/X is used as the RMII REFCLK signal. All RMII signals with the exception of the assertion of CRSDV_P are synchronous to REFCLK. ...
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... CRSDV is asserted asynchronously to REFCLK as in the valid receive case shown in . However, once false carrier is detected, RXD[1:0] is changed to (10) (11) (Value 1110 in MII) and RXER is asserted. Both RXD[1:0] and RXER transition synchronously to REFCLK. After carrier sense is de-asserted, CRSDV is de-asserted synchronously to REFCLK. Figure 6 RMII Reception Without Error Data Sheet 35 ADM7001/X Data sheet Function Description Rev. 1.07, 2005-11-25 ...
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... TXD[1:0] are synchronous to REFCLK. When TXEN is asserted, it indicates that TXD[1:0] contains valid data to be transmitted. When TXEN is de-asserted, value on TXD[1:0] should be ignored odd number of di-bits are presented onto TXD[1:0] and TXEN, the final di-bit will be discarded by ADM7001/X. Data Sheet Figure 8 ...
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... Figure 10 100M RMII Transmit Diagram Data Sheet 37 ADM7001/X Data sheet Function Description Rev. 1.07, 2005-11-25 ...
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... Data Sheet Auto Negotiation Enable Disable 100 Full √ √ √ √ √ √ √ √ √ √ Figure 12. 38 ADM7001/X Data sheet Function Description Figure 11 Capability 100 Half 10 Full 10 Half √ √ √ √ √ √ √ √ √ √ ...
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... RXCLK by ADM7001/X. When ADM7001/X detects there is valid data, RXDV and the received data are presented onto RXD[3:0] synchronously to RX_CLK. Whenever received data is not valid anymore, RXDV will be de-asserted by ADM7001/X and "0" will be put on RXD[3:0]. Figure 13 ...
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... RXER will keep low in 10M Operation. Figure 15 MII Receive With Symbol Error(100M Only) Data Sheet Figure 15. The packet with the symbol error is treated were a valid 40 ADM7001/X Data sheet Function Description Rev. 1.07, 2005-11-25 ...
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... When TXEN is asserted, it indicates that TXD[3:0] contains valid data to be transmitted. When TXEN is de-asserted, value on TXD[1:0] should be ignored. Figure 16 MII Transmission When ADM7001/X operates in half duplex mode, either 10M or 100M, it will assert COL signal whenever it detects there is collision on the medium. Figure 17 MII Transmit with Collision (Half Duplex Only) 3 ...
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... Figure 19 shows the relationship among RXCLK, RXD and CRS during a receive of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001/X. When ADM7001/X detects there is valid data, received data is presented onto RXD synchronously to RXCLK. Whenever received data is not valid anymore, CRS will be de-asserted by ADM7001/X and "0" will be put on RXD. ...
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... GPSI Transmit Diagram 3.3 LED Display Register 19 is used for different mode led display. ADM7001/X provides power on LED self test to minimize and ease the system test cost. All LEDs will be Off during power on reset (Output value same as recommend value on LED pins). After power on reset, all internal parallel LEDs will be On for 2 seconds to ease manufacture overhead There are three types of LED supported by ADM7001/X internally ...
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... MDIO pin. Figure 21 SMII Read Operation 3.4.2 Reset Operation The ADM7001/X can be reset either by hardware or software. A hardware reset is accomplished by applying a negative pulse, with duration of at least 200 ms to the RC pin of the ADM7001/X during normal operation to Data Sheet LEDSPD Cable Distance meters ...
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... An analog block is designed for carrier sense detecting. When there is no carrier sense presented on medium (cable not attached), then "SIGNAL DETECT" will not be ON. Whenever cable is attached to ADM7001/X and the voltage threshold is above +/- 50mV, then SD will be asserted HIGH to indicate that there is cable attached to ADM7001/X ...
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... LED. 3.6 Voltage Regulator ADM7001/X requires two different levels, 3.3 V and 2 voltage supply to provide the power to different parts of circuitry inside the chip. ADM7001/X has a build-in voltage regulator circuitry to generate the 2.5 V voltage (VCC25OUT) from 3.3 V power source (VCC3IN). External Application Circuitry is shown in ...
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... Figure 24 Power and Ground Filtering Data Sheet VCCO_25 GNDIK ADM7001 GNDO VCCIK_25 QFP 48 47 ADM7001/X Data sheet Function Description VCC25OUT(CORE) GNDPLL VCCPLL_25 GNDTR VCCA_25 Rev. 1.07, 2005-11-25 ...
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... Value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= Target for development.) Register is writable by SW Register can be modified by HW, but the priority SW versus HW has to be specified 48 ADM7001/X Data sheet Registers Description Page Number ...
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... SW can read the register, with write mask the register can be cleared SW can read and write this register Register is read and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is read and writable by SW. Description 49 ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... This bit determines whether the link speed should set up by the auto negotiation process or not set at power up or reset if the PI_RECANEN pin detects a logic 1 input level in Twisted-Pair Mode. 0 ANEN_0, Disable Auto negotiation process B 1 ANEN_1, Enable auto negotiation process B 50 ADM7001/X Data sheet Registers Description Reset Value 3000 H Rev. 1.07, 2005-11-25 ...
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... TXEN. 0 CT_0, Disable COL signal test B 1 CT_1, Enable COL signal test B Speed Selection MSB SPEED_MSB. Set to 0 all the time indicate that the PHY841F does not support 1000 Mbit/s function. Reserved Not Applicable 51 ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... Status Register SR Status Register Data Sheet Offset ADM7001/X Data sheet Registers Description Reset Value 7849 H Rev. 1.07, 2005-11-25 ...
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... If auto negotiation is enabled, this bit indicates whether the auto negotiation process has been completed or not. Set to 0 all the time when Fiber Mode is selected. 0 AN_C_0, Auto Negotiation process not completed B 1 AN_C_1, Auto Negotiation process completed B 53 ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... Jabber Detect 0 JAB_0, Jabber condition not detected B 1 JAB_1, Jabber condition detected B Extended Capability This bit defaults to 1, indicating that the PHY841F implements extended registers. 0 XTND_0, No extended register set B 1 XTND_1, Extended register set B 54 ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... Type PHYID 15:10 ro MODEL 9:4 REVID 3:0 Data Sheet Offset 02 H Description PHY-ID IEEE Address Offset 03 H Description PHY-ID 15:0 IEEE Address/Model No./Rev. No. MODEL 5:0 ADMTEK PHY Revision ID. REV-ID 3:0 ADMTEK PHY Revision ID. 55 ADM7001/X Data sheet Registers Description Reset Value 002E H Reset Value CC62 H Rev. 1.07, 2005-11-25 ...
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... B 11 BSP, Both Symmetric PAUSE and Asymmetric PAUSE toward B local device Pause Operation for Full Duplex Value on PAUREC will be stored in this bit during power on reset. Technology Ability for 100Base-T4 Defaults ADM7001/X Data sheet Registers Description Reset Value 01E1 H Rev. 1.07, 2005-11-25 ...
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... TF_1, Capable of 10M Full Duplex operation B 10Base-T Half Duplex 0 TD_0, Not capable of 10M operation B 1 TD_1, Capable of 10M operation B Selector Field These 5 bits are hardwired to 00001 supports IEEE 802.3 CSMA/CD. Offset ADM7001/X Data sheet Registers Description , indicating that the PHY841F B Reset Value 01E1 Rev. 1.07, 2005-11-25 H ...
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... TF_1, Capable of 10M Full Duplex operation B 0 TF_0, Not capable of 10M full duplex operation B 10Base-T Half Duplex 1 TD_1, Capable of 10M operation B 0 TD_0, Not capable of 10M operation B Encoding Definitions Offset ADM7001/X Data sheet Registers Description Reset Value 0000 H Rev. 1.07, 2005-11-25 ...
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... PRCV_1, A new page has been received B Link Partner Auto Negotiation Able 0 LPAN_0, Link Partner is not auto negotiable B 1 LPAN_1, Link Partner is auto negotiable B Offset 07 H Description Reserved Not Applicable 59 ADM7001/X Data sheet Registers Description Reset Value Reserved H Offset Address ...
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... PCS Layer Loop back mode PMA Layer Loop back mode PMD layer loop back mode B Reserved Not Applicable Enable called output remote fault status 0 FLT_0, Disable FLT_1, Enable ADM7001/X Data sheet Registers Description Offset Address ...
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... Enable Register 8 to Store Next Page Information. 0 En8_0, Store Next Page in Register En8_1, Store Next Page in Register 8 B Disable Power Management Feature 0 DPMG_0, Enable. Enable Medium Detect Function DPMG_1, Disable. Medium_On is high all the time ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... PHY 10M Module Configuration Register P10_MCR PHY 10M Module Configuration Register Field Bits Type Res 15 ro Data Sheet Offset 11 H Description Reserved Not Applicable 62 ADM7001/X Data sheet Registers Description Reset Value 0008 H Rev. 1.07, 2005-11-25 ...
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... TJD_0, Enable Transmit Jabber Function B 1 TJD_1, Disable Transmit Jabber Function B Normal Threshold 0 NTH_0, Lower 10BASE-T Receive threshold B 1 NTH_1, Normal 10BASE-T Receive threshold B Force 10M Receive Good Link. 0 FRL_0, Normal Operation B 1 FRL_1, Force Good Link B 63 ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... B 1 CLE_1, Disable cable length led B Interrupt active value control 0 IAC_0, Active low B 1 IAC_1, Active high B ADMtek reserved bits. Writing value other than 0 to this bit may cause abnormal operation. 64 ADM7001/X Data sheet Registers Description Reset Value 0022 H Rev. 1.07, 2005-11-25 ...
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... Link/Receive Activity B 1010 , Link and TX/RX Activity B 1011 , 100M False Carrier Error/10M Receive Jabber B 1100 , 100M Error End of Stream/10M Transmit Jabber B 1101 , Reserved B 1110 , Distance (See LED Description for more detail ADM7001/X Data sheet Registers Description Reset Value 0A34 H Rev. 1.07, 2005-11-25 ...
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... TX/RX Activity B 1001 , Link/Receive Activity B 1010 , Link and TX/RX Activity B 1011 , 100M False Carrier Error/10M Receive Jabber B 1100 , 100M Error End of Stream/10M Transmit Jabber B 1101 , Reserved B 1110 , Distance (See LED Description for more detail ADM7001/X Data sheet Registers Description Rev. 1.07, 2005-11-25 ...
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... Transmit Jabber Interrupt Enable 0 TJIE_0, Interrupt Disable B 1 TJIE_1, Interrupt Enable B Receive Jabber Interrupt Enable 0 RJIE_0, Interrupt Disable B 1 RJIE_1, Interrupt Enable B Error End of Stream Enable 0 EESE_0, Interrupt Disable B 1 EESE_1, Interrupt Enable B 67 ADM7001/X Data sheet Registers Description Reset Value 03FF H Rev. 1.07, 2005-11-25 ...
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... XOVS_0, MDI mode B 1 XOVS_1, MDIX mode B Cable Length. Only valid for 100M MSB is IC0 meters meters meters 100 meters 120 meters 140 meters H 68 ADM7001/X Data sheet Registers Description Reset Value 0000 H Rev. 1.07, 2005-11-25 ...
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... Real Time Link Status 0 LINK_0, Link Down B 1 LINK_1, Link Up B Pause Recommend Value Only Changed when PHY Reset. This bit is disabled automatically when RDUP RPAU_0, Pause Disable B 1 RPAU_1, Pause Enable B 69 ADM7001/X Data sheet Registers Description Reset Value 0060 H Rev. 1.07, 2005-11-25 ...
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... PREC_1, Pause Enable B Far End Fault Disable 0 FEFD_0, Enable B 1 FEFD_1, Disable B Cross Over Capability Recommend Value 0 XOVR_0, Disable B 1 XOVR_1, Enable B Cross Over Status 0 XOVS_0, Non-Cross Over B 1 XOVS_1, Cross Over B 70 ADM7001/X Data sheet Registers Description Reset Value 0000 H Rev. 1.07, 2005-11-25 ...
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... Interrupt Status Register Data Sheet Description RMII_SMII Interface 0 RSll_0, Non RMII_SMII Interface B 1 RSll_1, RMII or SMII Interface used B Repeater Mode Recommend Value 0 RM_0, NIC/ RM_1, Repeater B PHY Address Offset ADM7001/X Data sheet Registers Description Reset Value 0000 H Rev. 1.07, 2005-11-25 ...
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... FCAR_0, No false carrier B 1 FCAR_1, False Carrier B Transmit Jabber 0 TJAB_0, No Jabber B 1 TJAB_1, Jabber B Receive Jabber 0 RJAB_0, No Jabber B 1 RJAB_1, Jabber B Error End of Stream 0 STRE_0, No ESD Error B 1 STRE_1, ESD Error B Offset ADM7001/X Data sheet Registers Description Reset Value 0000 H Rev. 1.07, 2005-11-25 ...
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... False Carrier H 2 100MSE, 100M Symbol Error H 3 10MTJ, 10M Transmit Jabber H 4 10MRJ, 10M Receive Jabber H 5 ESS, Error Start of Stream H 6 EES, Error End of Stream H Offset 1F H Description CHIPID 15:0 73 ADM7001/X Data sheet Registers Description Reset Value 8125 H Rev. 1.07, 2005-11-25 ...
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... Symbol Values Min. Typ. V – – 0 – – 2.0 – – ADM7001/X Electrical Characteristics Unit Note / Test Condition Max. 3.6 V – 2.75 V – 0.3 V – CC33 V + 0.25 V – CC25 °C 155 – 0.5 W – 2000 V – Unit Note / Test Condition Max ...
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... FIFO depth. Check peer receive FIFO description to confirm. Data Sheet WB;,B3(5 WB;,B+, Symbol Values Min. Typ. t 40.0 40.0 XI_PER - 50 ppm t 14 20.0 XI_HI 14 20.0 TX_ILO t – – XI_RISE t – – XI_FALL 75 ADM7001/X Data sheet Electrical Characteristics WB;,B/2 WB;,B)$// Unit Note / Test Condition Max. 40.0 ns – ppm – ns – – ns – – – Rev. 1.07, 2005-11-25 ...
Page 76
... Symbol Values Min. Typ. t 20.0 20.0 IN50_PER - 50 ppm t 8 10.0 IN50_HI t 8 10.0 IN50_LO t – – IN50_RISE t – – IN50_FALL 76 ADM7001/X Data sheet Electrical Characteristics t_IN50_LO t_IN50_FALL Unit Note / Test Condition Max. 20.0 ns – ppm – ns – – ns – – – Rev. 1.07, 2005-11-25 ...
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... Min. Typ. t 20.0 20.0 OUT50_PER - 50 ppm t 8 10.0 OUT50_HI t 8 10.0 OUT50_LO t – – OUT50_RISE t – – OUT50_FALL t – 0.15 OUT50_JIT 77 ADM7001/X Data sheet Electrical Characteristics t_OUT50_LO t_OUT50_FALL Unit Note / Test Condition Max. 20.0 ns – ppm 12 ns – – – – – Rev. 1.07, 2005-11-25 ...
Page 78
... RT_DSETUP t 2 – RT_DHOLD t – – RT_TXE2MH100 t – – RT_TXE2MH10 t – – RT_TXE2ML100 t – – RT_TXE2ML10 WB55B''/< 78 ADM7001/X Data sheet Electrical Characteristics WB57B7;(0/ Unit Note / Test Condition Max. – ns – – ns – 235 ns – 1550 ns – 260 ns – 1250 ns – ...
Page 79
... RR_ML2CSL10 t – – RR_CSH2DAT100 t – – RR_CSH2DAT10 t – 160 RR_CSL2DAT100 t – 1600 RR_CSL2DAT10 t – – RR_DDLY t_RCK_PER t_RCK_HI 79 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max. 265 ns – 1000 ns – 260 ns – 570 ns – 160 ns – 1600 ns – ...
Page 80
... RCK_HI10 t 16 – RCK_LO100 t – 200 RCK_LO10 t – – RCK_RISE t – – RCK_FALL t – 0.15 RCK_JIT 80 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max. 40.0 ns – ppm 400.0 ns – ppm 24 – – – – – – – ...
Page 81
... MR_DDLY100 t 10 – MR_DDLY10 t – – MR_ML2CSL100 t – – MR_ML2CSL10 t – – MR_ML2DAT100 t – – MR_ML2DAT10 81 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max. 140 ns – 1450 ns – 150 ns – 2300 ns – – – 120 ns – ...
Page 82
... TCK_HI100 t 160 – TCK_HI10 t 16 – TCK_LO100 t 160 – TCK_LO10 t – – TCK_RISE t – – TCK_FALL t – 0.15 TCK_JIT 82 ADM7001/X Data sheet Electrical Characteristics t_TCK_LO t_TCK_FALL Unit Note / Test Condition Max. 40.0 ns – ppm 40.0 ns – ppm 24 ns – 240 ns – – 240 ns – ...
Page 83
... MT_TXE2MH10 t – – MT_TXE2CSH100 t – – MT_TXE2CSH10 t – – MT_TXE2ML100 t – – MT_TXE2ML10 t – – MT_TXE2CSL100 t – – MT_TXE2CSL10 83 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max – – – 350 ns – – 200 ns – – ...
Page 84
... GSPI_RCK_HI t 40 – GSPI_RCK_LO t – – GR_MH2CSH t – – GR_MH2DAT t 40 – GR_DDLY t – – GR_ML2CSL 84 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max. 100.0 ns – ppm – ns – – ns – 1500 ns – 1600 ns – – ...
Page 85
... GT_TXE2ML t – – GT_TXECSL t_MDC_LO t_MDIO_DLY t_MDIO_SETUP Symbol Values Min. Typ. t 100 – MDC_PER t 40 – MDC_HI 85 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max. 100.0 ns – ppm – ns – – ns – – ns – – ns – 150 ns – ...
Page 86
... Typ. t TBD – V33_V25 t 200 – V25_RST t 800 – RST_PW t 200 – PL_DSETUP t 0 – PL_DHOLD 86 ADM7001/X Data sheet Electrical Characteristics Unit Note / Test Condition Max. – ns – – – ns – – ns – t_RST_PW t_PL_DSETUP Unit Note / Test Condition Max. ...
Page 87
... Packaging ADM7001/X, Low Profile Quad Flat Package (LQFP) 48 Pin Figure 38 ADM7001/X,Low Profile Quad Flat Package (LQFP) Data Sheet 87 ADM7001/X Data sheet Packaging Rev. 1.07, 2005-11-25 ...
Page 88
... BSC. 5.60 5.60 Tolerance of Form and Position 0.20 0.20 0.10 0.20 44L 0.20 0.27 0.50 BSC. 5.00 5.00 Tolerance of Form and Position 0.20 0.20 0.08 0.08 48L 0.20 0.27 88 ADM7001/X Data sheet Inch Min. Typ. – – 0.002 – 0.053 0.005 0.354 BSC. 0.276 BSC. 0.354 BSC. 0.276 BSC. 0.003 – 0.003 – 0° 3.5° 0° – 11° ...
Page 89
... Table 39 Dimensions for 100 Pin LQFP Package (cont’d) Symbol Millimeter (mm aaa bbb ccc ddd Data Sheet 0.50 BSC. 5.50 5.50 Tolerance of Form and Position 0.20 0.20 0.08 0.08 89 ADM7001/X Data sheet Packaging Inch 0.020 BSC. 0.217 0.217 0.008 0.008 0.003 0.003 Rev. 1.07, 2005-11-25 ...
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... Published by Infineon Technologies AG ...