PEF2256H Infineon Technologies AG, PEF2256H Datasheet
PEF2256H
Available stocks
Related parts for PEF2256H
PEF2256H Summary of contents
Page 1
FALC ...
Page 2
... SICAT , SICOFI ® ® 10BaseV , 10BaseVX are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. ® Microsoft is a registered trademark of Microsoft Corporation, Linux ® Visio of Visio Corporation, and FrameMaker The information in this document is subject to change without notice. ...
Page 3
Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Table of Contents 4.1.15.1 HDLC or LAPD Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Table of Contents 4.4.7.1 HDLC or LAPD access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Table of Contents 5.2 Framer Operating Modes (T1/J1 142 5.2.1 ...
Page 7
Table of Contents 5.5.2 Transmit System Interface (T1/J1 179 5.5.2.1 Transmit Offset Programming ...
Page 8
Table of Contents 8.3.8 Data Link Access in ESF/F72 Format (T1/J1 221 Register Description . . . . . . . ...
Page 9
Table of Contents Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
List of Figures Figure 1 GSM Base Station Aplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
List of Figures Figure 43 Single Channel Loop-Back (E1 120 Figure 44 ...
Page 12
List of Figures Figure 85 MCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 13
List of Tables Table 1 Pin Definitions - Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . 26 Table 2 Pin Definitions - Line Interface ...
Page 14
List of Tables Table 43 Structure of Periodical Performance Report (T1/J1 170 Table 44 Bit Functions in Periodical Performance Report . . . . . . . ...
Page 15
List of Tables Table 85 SCLKR/SCLKX Timing Parameter Values 481 Table 86 Receive System Interface Marker Timing Parameter Values . ...
Page 16
Preface ® The FALC 56 framer and line interface component is designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The digital functions as well as the analog characteristics are configured ...
Page 17
Introduction ® The FALC 56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Due to its ...
Page 18
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications ® FALC 56 Version 2.1 1.1 Features Line Interface • High-density, generic interface for all E1/T1/J1 applications • Analog receive and transmit circuits for long-haul and short-haul applications • ...
Page 19
Common master clock reference for E1 and T1/J1 (any frequency within 1.02 and 20 MHz) • Power-down function • Support of automatic protection switching • Dual-rail or single-rail digital inputs and outputs • Unipolar NRZ or CMI for interfacing ...
Page 20
Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass • Provides different time slot mapping modes • Supports fractional E1 or T1/J1 access • Flexible transparent modes • • • Pseudo-random binary sequence generator and monitor (framed or unframed) • ...
Page 21
One-second timer (internal or external timing reference) General • General input/output function included in multifunction ports • Boundary scan standard IEEE 1149.1 P-LBGA-81-1 package; body size 10 mm × 10 mm; ball pitch 1 • P-MQFP-80-1 package; ...
Page 22
Typical Applications Figure 1 shows a typical application used in GSM base stations. Figure 1 GSM Base Station Aplication User’s Manual Hardware Description PEF 2256 H/E 22 DS1.1, 2003-10-23 ® FALC 56 Introduction ...
Page 23
External Signals 2.1 Logic Symbol Figure 2 Logic Symbol User’s Manual Hardware Description PEF 2256 H/E External Signals 23 DS1.1, 2003-10-23 ® FALC 56 ...
Page 24
Pin Diagram P-MQFP-80-1 Figure 3 Pin Configuration P-MQFP-80-1 User’s Manual Hardware Description PEF 2256 H/E External Signals 24 DS1.1, 2003-10-23 ® FALC 56 ...
Page 25
Pin Diagram P-LBGA-81-1 Figure 4 Pin Configuration P-LBGA-81-1 User’s Manual Hardware Description PEF 2256 H/E External Signals 25 DS1.1, 2003-10-23 ® FALC 56 ...
Page 26
Pin Description This chapter describes the pin functions. There is no functional difference between TQFP and BGA package. Pin numbers refer to the TQPP package while the ball numbers refer to the BGA package. 2.4.1 Input/Output Signals Table 1 ...
Page 27
Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin or Name Pin Ball No. Type 51 (E9) ALE I 52 (E7 (D7 User’s Manual Hardware Description Buffer Function Type PU Address ...
Page 28
Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin or Name Pin Ball No. Type 12 (E3) DBW I 11 (E1 (D9 User’s Manual Hardware Description Buffer Function Type PU Data Bus Width This input ...
Page 29
Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin or Name Pin Ball No. Type 55 (C9) BHE I BLE I 57 (C7) INT O User’s Manual Hardware Description Buffer Function Type PU Bus High Enable Used in Intel bus ...
Page 30
Table 2 Pin Definitions - Line Interface Pin or Name Pin Ball No. Type 3 (C2) RL1 I RDIP I ROID I User’s Manual Hardware Description Buffer Function Type analog Line Receiver Input 1 Analog input from the external transformer. ...
Page 31
Table 2 Pin Definitions - Line Interface (cont’d) Pin or Name Pin Ball No. Type 2 (B1) RL2 I RDIN I RCLKI I User’s Manual Hardware Description Buffer Function Type analog Line Receiver Input 2 Analog input from the external ...
Page 32
Table 2 Pin Definitions - Line Interface (cont’d) Pin or Name Pin Ball No. Type 7 (D4) XL1 O XDOP O XOID O User’s Manual Hardware Description Buffer Function Type analog Transmit Line 1 Analog output to the external transformer. ...
Page 33
Table 2 Pin Definitions - Line Interface (cont’d) Pin or Name Pin Ball No. Type 5 (C1) XL2 O XDON O XFM O User’s Manual Hardware Description Buffer Function Type analog Transmit Line 2 Analog output to the external transformer. ...
Page 34
Table 3 Pin Definitions - Clock Interface Pin or Name Pin Ball No. Type 73 (C4) MCLK I 79 (A2) SYNC I 76 (B4) CLK1 O User’s Manual Hardware Description Buffer Function Type Master Clock A reference clock of better ...
Page 35
Table 3 Pin Definitions - Clock Interface (cont’d) Pin or Name Pin Ball No. Type 77 (C3) CLK2 O User’s Manual Hardware Description Buffer Function Type PU DCO-X Clock Output Output of the de-jittered system clock generated by the DCO-X ...
Page 36
Table 3 Pin Definitions - Clock Interface (cont’d) Pin or Name Pin Ball No. Type 78 (B3) SEC I O FSC O User’s Manual Hardware Description Buffer Function Type PU One-Second Timer Reference Input A pulse with logical high level ...
Page 37
Table 3 Pin Definitions - Clock Interface (cont’d) Pin or Name Pin Ball No. Type 75 (A3) RCLK O User’s Manual Hardware Description Buffer Function Type PU Receive Clock After reset this port is configured to be internally pulled up ...
Page 38
Table 4 Pin Definitions - System Interface Pin or Name Pin Ball No. Type 66 (B6) RDO O 65 (A7) SCLKR I/O User’s Manual Hardware Description Buffer Function Type Receive Data Output Received data that is sent to the system ...
Page 39
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 67 (D6) RPA 68 (A6) RPB 69 (B5) RBC 70 (D5) RPD I User’s Manual Hardware Description Buffer Function Type Receive Multifunction Ports Depending on ...
Page 40
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 67 (D6) RPA O 68 (A6) RPB 69 (B5) RBC 70 (D5) RPD O User’s Manual Hardware Description Buffer Function Type Receive Frame Marker (RFM) ...
Page 41
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 67 (D6) RPA O 68 (A6) RPB 69 (B5) RBC 70 (D5) RPD User’s Manual Hardware Description Buffer Function Type Receive Signaling ...
Page 42
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 67 (D6) RPA O 68 (A6) RPB 69 (B5) RBC 70 (D5) RPD (D8) XDI I 64 (C6) SCLKX I User’s ...
Page 43
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 60 (B8) XPA 61 (A9) XPB 62 (A8) XBC 63 (B7) XPD I I User’s Manual Hardware Description Buffer Function Type Transmit Multifunction Ports Depending ...
Page 44
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 60 (B8) XPA I 61 (A9) XPB 62 (A8) XBC 63 (B7) XPD User’s Manual Hardware Description Buffer Function Type PU Transmit ...
Page 45
Table 4 Pin Definitions - System Interface (cont’d) Pin or Name Pin Ball No. Type 60 (B8) XPA O 61 (A9) XPB 62 (A8) XBC 63 (B7) XPD User’s Manual Hardware Description Buffer Function Type ...
Page 46
Table 5 Miscellaneous Pin Definitions Pin (Ball) Name Pin No. Type Power Supply 80 (B2) VSEL I 4 (D3 DDR 6 (D2 DDX 9 (E2 DDP 74 (A4 DDC 9 (A5) V ...
Page 47
Table 5 Miscellaneous Pin Definitions (cont’d) Pin (Ball) Name Pin No. Type 1 (A1 (D1) 10 (E4) 10 (B9) 25 (C5) 35 (E4) 42 (H9) 59 (J3) 72 (J7) Analog Switch 19 (H1) AS1 I/O 20 ...
Page 48
Table 5 Miscellaneous Pin Definitions (cont’d) Pin (Ball) Name Pin No. Type 17 (G3) TCK I 18 (G2) TDO O Unused Pins - (E5) N.C. Note open drain output PP = push/pull output PU = input or input/output ...
Page 49
Functional Description E1/T1/J1 3.1 Functional Overview ® The FALC 56 device contains analog and digital function blocks that are configured and controlled by an external microprocessor or microcontroller. The functional block diagram is shown in Figure 5. The main ...
Page 50
Block Diagram • Figure 5 Block Diagram User’s Manual Hardware Description PEF 2256 H/E Functional Description E1/T1/J1 50 DS1.1, 2003-10-23 ® FALC 56 ...
Page 51
Functional Blocks 3.3.1 Microprocessor Interface The communication between the CPU and the FALC accessible registers. The interface can be configured as Intel or Motorola type with a selectable data bus width bits. The CPU transfers ...
Page 52
Table 8 Selectable Bus and Microprocessor Interface Configuration ALE IM Microprocessor interface Motorola Intel SS DD switching 0 Intel The assignment of registers with even/odd addresses to the data lines in case ...
Page 53
Figure 6 FIFO Word Access (Intel Mode) xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx ...
Page 54
Interrupt Interface ® Special events in the FALC 56 are indicated by means of a single interrupt output with programmable characteristics (open drain or push-pull, defined by register IPC), which requests the CPU to read status information from the ...
Page 55
After reading the assigned interrupt status registers ISR(5:0), the pointer in register GIS is cleared or updated if another interrupt requires service. If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes inactive. ...
Page 56
Boundary Scan Interface ® In the FALC 56 a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, ...
Page 57
Test handling (boundary scan operation) is performed using the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, that means TRS is ...
Page 58
Figure 10 JTAG TAP Controller State Machine User’s Manual Hardware Description PEF 2256 H/E Functional Description E1/T1/J1 58 DS1.1, 2003-10-23 ® FALC 56 ...
Page 59
Master Clocking Unit ® The FALC 56 provides a flexible clocking unit, which references to any clock in the range of 1. MHz supplied on pin MCLK. The clocking unit has to be tuned to the selected ...
Page 60
Power Supply 3.4.1 Power Supply Configuration ® The FALC 56 uses two different supply voltages internally, which are 3.3 V and 1.8 V. For compatibility reasons possible to operate the device off a single 3.3 V power ...
Page 61
Figure 13 Dual Voltage Power Supply Mode 3.4.2 Power Supply De-Coupling To gain best performance, the following values are recommended for the external de-coupling between V and V DDC Table 10 Decoupling Capacitor Parameters Parameter Value 470 nF ± 20 ...
Page 62
Figure 14 Decoupling Capacitor Placement User’s Manual Hardware Description PEF 2256 H/E Functional Description E1/T1/J1 62 DS1.1, 2003-10-23 ® FALC 56 ...
Page 63
Functional Description E1 4.1 Receive Path in E1 Mode Figure 15 Receive Clock System (E1) 4.1.1 Receive Line Interface For data input, three different data types are supported: • Ternary coded signals received at multifunction ports RL1 and RL2 ...
Page 64
Receive Equalization Network (E1) ® The FALC 56 automatically recovers the signals received on pins RL1 range -43 ...
Page 65
Table 11 RCLK Output Selection (E1) Clock Source Receive Data (2.048 Mbit/s on RL1/RL2, RDIP/RDIN or ROID) Receive Data in case of LOS DCO-R The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ...
Page 66
Receive Line Termination (E1) The signal at the ternary interface is received at both ends of a transformer. A termination resistor is used to achieve line impedance matching (see The E1 operating modes 75 Ω or 120 Ω are ...
Page 67
Figure 17 Receive Line Monitoring (E1) Table 13 External Component Recommendations (Monitoring) 1) Parameter This includes all parasitic effects caused by circuit board design. Using the receive line monitor mode and the hardware ...
Page 68
Switching between both devices can be done through the microcontroller interface or by using the tristate hardware input pin as shown in the figure. Figure 18 Short Haul Protection Switching Application (E1) For long haul redundancy requirements (see ...
Page 69
Figure 19 Long Haul Protection Switching Application (E1) 4.1.9 Loss-of-Signal Detection (E1) There are different definitions for detecting Loss-Of-Signal (LOS) alarms in the ITU-T G.775 and ETS 300233. The FALC is performed by generating an interrupt (if not masked) and ...
Page 70
LIM1.RIL(2:0) (see by an 8-bit register (PCD). The contents of the PCD register is multiplied by 16, which results in the number of pulse periods, i.e. the time which has to suspend until the alarm has to be ...
Page 71
Slave mode In slave mode (LIM0.MAS = 0) the DCO-R is synchronized with the recovered route clock. In case of LOS the DCO-R switches automatically to Master mode. If bit CMR1.DCS is set automatic switching from RCLK to SYNC ...
Page 72
Figure 20 Jitter Attenuation Performance (E1) Also the requirements of ETSI TBR 12/13 are satisfied. Insuring adequate margin against TBR 12/13 output jitter limit with 15 UI input ...
Page 73
Jitter Tolerance (E1) ® The FALC 56 receiver’s tolerance to input jitter complies with ITU requirements. Figure 21 shows the curves of different input jitter specifications stated below as well as ® the FALC 56 performance. Figure 21 Jitter ...
Page 74
Framer/Synchronizer (E1) The following functions are performed: • Synchronization on pulse frame and multiframe • Error indication when synchronization is lost. In this case, AIS is sent automatically to the system side and remote alarm is sent to the ...
Page 75
Reporting and controlling of slips Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data which is circularly written to the elastic buffer using internally generated receive route clock (RCLK). Reading of ...
Page 76
RCLK and the current working clock of the receive ...
Page 77
Receive Signaling Controller (E1) The signaling controller can be programmed to operate in various signaling modes. The ® FALC 56 performs the following signaling and data link methods. 4.1.15.1 HDLC or LAPD Access ® The FALC 56 offers three ...
Page 78
CRC checking or bit stuffing. This allows user specific protocol variations. 4.1.15.2 Support of Signaling System #7 The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is described in ...
Page 79
Figure 23 Automatic Handling of Errored Signaling Units User’s Manual Hardware Description PEF 2256 H/E Functional Description E1 79 DS1.1, 2003-10-23 ® FALC 56 F0071 ...
Page 80
S -Bit Access (E1) a ® The FALC 56 supports the S a • The access through register RSW • The access through registers RSA(8:4), capable of storing the information for a complete multiframe • The access through the ...
Page 81
Because the CAS controller is working on the PCM highway side of the receive buffer, slips disturb the CAS data. SYPR SCLKR T TS31 TS0 RDO FAS/NFAS RSIG FAS/NFAS T = Time ...
Page 82
Additionally the FALC data change pointer (RSP1/2) which directly points to the updated RS(16:1) register. Because the CAS controller is working on the PCM highway side of the receive buffer, slips disturb the CAS ...
Page 83
Doubleframe Format (E1) The framing structure is defined by the contents of time slot 0 (refer to Table 17 Allocation of Bits Time Slot 0 (E1) Bit 1 AlternateNumber Frames Frame Containing the Frame Alignment ...
Page 84
Transmit Transparent Modes In transmit direction, contents of time slot 0 frame alignment signal of the outgoing PCM frame are normally generated by the FALC time slot 0 can be achieved by selecting the transparent mode XSP.TT0. With the ...
Page 85
The presence of the correct service word (bit frame • A correct FAS word in frame the service word in frame the FAS word ...
Page 86
CRC-Multiframe (E1) The multiframe structure shown in the receiver and FMR1.XFS for the transmitter. 2 submultiframes = 2 × 8 frames Multiframe : Frame alignment : refer to section Doubleframe Format Multiframe alignment : bit 1 of frames 1, ...
Page 87
For transmit direction, contents of time slot 0 are additionally determined by the selected transparent mode. Table 20 Transmit Transparent Mode (CRC Multiframe E1) enabled by Transmit Transparent Source for Framing + CRC – (int. gen.) XSP.TT0 via pin XDI ...
Page 88
In doubleframe asynchronous state, counting of framing errors, CRC4 bit errors and detection of remote alarm is stopped. AIS is automatically sent to the backplane interface (can be disabled by bit FMR2.DAIS). Further on the updating of the registers RSW, ...
Page 89
A research for basic frame alignment is initiated if the CRC4 multiframe synchronization cannot be achieved within 8 ms and is started just after the previous ...
Page 90
S -Bit Access (E1) a Due to signaling procedures using the five S CRC multiframe structure, three possibilities of access by the microprocessor are implemented. • The standard procedure allows reading/writing the S without further support. The S • ...
Page 91
S 6-Bit Error Indication Counters a The S 6-bit error indication counter CRC2L/H (16 bits) counts the received S a sequence 0001 or 0011 in every CRC submultiframe. In the primary rate access digital section this counter option gives information ...
Page 92
Note: E-bits can be processed by the system interface. Setting bit TSWM.TSIS enables transparency for E-bits in transmit direction (refer to OUT of Primary BFA: Inhibit Incoming CRC-4 Performance Monitoring Reset all Timers Set FRS0.LFA/LMFA/NMF = 110 No IN Primary ...
Page 93
Additional Receive Framer Functions (E1) 4.3.1 Error Performance Monitoring and Alarm Handling Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and ISR2.AIS. Transmission is enabled by bit FMR1.XAIS. Loss-Of-Signal: Detection and recovery is flagged by bit ...
Page 94
Table 21 Summary of Alarm Detection and Release (E1) (cont’d) Alarm Detection Condition Remote Alarm in Y-bit = 1 received in CAS time slot 16 (TS16RA) multiframe alignment word Loss-of-Signal in All zeros for at least 16 time slot 16 ...
Page 95
Automatic Clock Source Switching In slave mode (LIM0.MAS = 0) the DCO-R synchronizes to the recovered route clock. In case of loss-of-signal (LOS) the DCO-R switches to Master mode automatically. If bit CMR1.DCS is set, automatic switching from RCLK ...
Page 96
SEC/FSC. Selecting the external second timer is done with GCR.SES. Refer also to register GPC1 for input/output selection. 4.3.6 In-Band Loop Generation and Detection ® The FALC ...
Page 97
Transmit Path in E1 Mode 4.4.1 Transmitter (E1) The serial bit stream is processed by the transmitter which has the following functions: • Frame/multiframe synthesis of one of the two selectable framing formats • Insertion of service and data ...
Page 98
Transmit Line Interface (E1) The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. The unipolar data is provided by the digital transmitter. Figure 26 Transmitter Configuration (E1) ...
Page 99
Transmit Jitter Attenuator (E1) The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and meets the following requirements: ITU-T I.431, G. 703, G. 736 to 739, G.823 and ETSI TBR12/13. The DCO-X circuitry works internally with the ...
Page 100
XL1/ XDOP/ DR XOID DR XL2/ XDON XCLK TCLK (E1: 8MHz) (T1: 6MHz) Clocking MCLK Unit Figure 27 Transmit Clock System (E1) Note Dual-Rail interface DCO-X Digital Controlled Oscillator transmit 4.4.4 Transmit Elastic Buffer (E1) The received bit ...
Page 101
Clock adaption between system clock (SCLKX) and internally generated transmit route clock (XCLK). • Compensation of input wander and jitter. • Frame alignment between system frame and transmit route frame • Reporting and controlling of slips Writing of received ...
Page 102
XL1/2 and if the transmit line current drops below the detection limit the high-impedance state is cleared. Two conditions are detected by the monitor: transmit line de-jitteredity (more than 31 consecutive zeros) indicated by FRS1.XLO and transmit line high current ...
Page 103
Each HDLC controller can be used to operate on the line side (called "normal HDLC" the system side (called "inverse HDLC"). 4.4.7.2 Support of Signaling System #7 The HDLC controller of channel 1 supports the signaling system #7 ...
Page 104
S -bits which shall be inserted in the outgoing data stream can be a selected by XC0.SA(8:4). 4.4.7.4 Channel Associated Signaling CAS (E1, serial mode) In external signaling mode (serial mode) the signaling data received on port XSIG ...
Page 105
If the FALC 56 is configured for no signaling, the system interface data stream passes ® the FALC 56 undisturbedly. 4.5 System Interface in E1 Mode ® The FALC 56 offers a flexible feature for system designers where for ...
Page 106
PC(4:1).RPC(2:0) = 001. The RFM selection disables the internal time slot assigner, no offset programming is performed. The receive frame marker is active high for one 2.048 MHz cycle or one system clock cycle (see GPC1.SRFM) and is clocked off ...
Page 107
Figure 30 System Interface (E1) User’s Manual Hardware Description Functional Description E1 107 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E ...
Page 108
Receive System Interface (E1) FRAME 1 FRAME 2 FRAME 3 RDO RMFB SYPR SYPR Trigger 1) Edge SCLKR 8.192 MHz T SCLKR 2.048 MHz RDO/RSIG Bit 255 2 Mbit/s Data Rate RDO/RSIG 4 Mbit/s Data Rate Bit 0 Bit ...
Page 109
Receive Offset Programming Depending on the selection of the synchronization signals (SYPR or RFM), different calculation formulas are used to define the position of the synchronization pulses. These formulas are given below, see of SYPR and RFM is always ...
Page 110
RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) SYPR SYPR SYPR Figure 32 SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) RDO (CP0 ...
Page 111
RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) RFM RFM RFM BP = 251 Figure 34 RFM Offset Programming (2.048 Mbit/s, ...
Page 112
Transmit System Interface (E1) Figure 36 Transmit System Interface Clocking: 2.048 MHz (E1) User’s Manual Hardware Description Functional Description E1 112 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E F0003 ...
Page 113
Figure 37 Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1) User’s Manual Hardware Description Functional Description E1 113 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E F0004 ...
Page 114
Transmit Offset Programming The pulse length of SYPX is always the basic E1 bit width (488 ns), independent of the selected system highway clock and data frequency. SYPX Offset Calculation T: Time between beginning of SYPX pulse and beginning ...
Page 115
Figure 38 SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) Figure 39 SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) User’s Manual Hardware Description Functional Description E1 115 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E ...
Page 116
Time Slot Assigner (E1) HDLC channel 1 offers the flexibility to connect data during certain time slots, as defined by registers RTR(4:1) and TTR(4:1), to the RFIFO and XFIFO, respectively. Any combinations of time slots can be programmed for ...
Page 117
Test Functions (E1) 4.6.1 Pseudo-Random Binary Sequence Generation and Monitor ® The FALC 56 has the ability to generate and monitor 2 binary sequences (PRBS). The generated PRBS pattern is transmitted to the remote end on pins XL1/2 or ...
Page 118
Payload Loop-Back To perform an effective circuit test a payload loop is implemented. The payload loop-back (FMR2.PLB) loops the data stream from the receiver section back to transmitter section. The looped data passes the complete receiver including the wander ...
Page 119
Local Loop The local loop-back mode selected by LIM0. disconnects the receive lines RL1/2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by the system interface is routed through ...
Page 120
Single Channel Loop-Back Each of the 32 time slots can be selected for loop-back from the system PCM input (XDI) to the system PCM output (RDO). This loop-back is programmed for one time slot at a time selected by ...
Page 121
Alarm Simulation (E1) Alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. However, possible reported to the processor or to the remote end when the device is in the ...
Page 122
Functional Description T1/J1 5.1 Receive Path in T1/J1 Mode Figure 44 Receive Clock System (T1/J1) 5.1.1 Receive Line Interface (T1/J1) For data input, three different data types are supported: • Ternary coded signals received at multifunction ports RL1 and ...
Page 123
Receive Equalization Network (T1/J1) ® The FALC 56 automatically recovers the signals received on pins RL1/2. The maximum reachable length with a 22 AWG twisted-pair cable is 2000 m (~6560 ft.). The integrated receive equalization network recovers signals with ...
Page 124
Table 26 RCLK Output Selection (T1/J1) Clock Source Receive Data (1.544 Mbit/s on RL1/RL2, RDIP/RDIN or ROID) Receive Data in case of LOS DCO-R The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ...
Page 125
Receive Line Termination (T1/J1) The signal at the ternary interface is received at both ends of a transformer. A termination resistor is used to achieve line impedance matching (see Figure 45 Receiver Configuration (T1/J1) Table 27 Recommended Receiver Configuration ...
Page 126
Receive Line Monitoring Mode For short-haul applications like shown in switched into receive line monitoring mode (LIM0.RLM = 1). One device is used as a short-haul receiver while the other is used as a short-haul monitor. In this mode ...
Page 127
If both channels are configured identically and supplied with the same system data and clocks, the transmit path can be switched from one channel to the other ...
Page 128
Figure 48 Long Haul Protection Switching Application (T1/J1) 5.1.9 Loss-of-Signal Detection (T1/J1) There are different definitions for detecting Loss-Of-Signal alarms (LOS) in the ITU-T G.775 and AT&T TR 54016. The FALC indication is performed by generating an interrupt (if not ...
Page 129
LIM1.RIL(2:0) (see set by an 8-bit register (PCD). The contents of the PCD register is multiplied by 16, which results in the number of pulse periods, i.e. the time which has to suspend until the alarm has ...
Page 130
Slave mode In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route clock. In case of LOS the DCO-R switches automatically to master mode. If bit CMR1.DCS is set automatic switching from RCLK to SYNC ...
Page 131
Table 29 System Clocking (T1/J1) (cont’d) Mode Internal SYNC LOS Active Input Slave yes 1.544 or 2.048 MHz The jitter attenuator meets the jitter transfer requirements of the PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431 ...
Page 132
Jitter Tolerance (T1/J1) ® The FALC 56 receiver’s tolerance to input jitter complies with ITU, AT&T and Telcordia requirements for T1 applications. Figure 50 shows the curves of different input jitter specifications stated below as well as ® the ...
Page 133
Output Jitter (T1/J1) According to the input jitter defined by PUB62411 the FALC jitter which is specified in Table 30 Table 30 Output Jitter (T1/J1) Specification Measurement Filter Bandwidth Lower Cutoff PUB 62411 kHz 10 Hz ...
Page 134
RBS1/0 = 00: two frame buffer or 386 bits Maximum of wander amplitude (peak-to-peak 648 ns) System interface clocking rate: modulo 2.048 MHz: 142 UI in channel translation mode channel translation mode ...
Page 135
Table 31 Channel Translation Modes (DS1/J1) Channels Channel Channel Translation Translation Mode 0 Mode 1 FS/DL FS/ – – – ...
Page 136
Table 32 Receive Buffer Operation Modes (T1/J1) Buffer Size (SIC1.RBS1/0) 1) Bypass Short buffer 1 frame 2 frames 1) In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK. Figure 51 gives an idea ...
Page 137
Frame 2 Time Slots W : Write Pointer (Route Clock controlled Read Pointer (System Clock controlled) S Limits for Slip Detection (mode dependent) Figure 51 The Receive Elastic Buffer as Circularly Organized Memory User’s Manual Hardware ...
Page 138
Receive Signaling Controller (T1/J1) The signaling controller can be programmed to operate in various signaling modes. The ® FALC 56 performs the following signaling and data link methods. 5.1.15.1 HDLC or LAPD Access ® The FALC 56 offers three ...
Page 139
Support of Signaling System #7 The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is described in ITU-Q.703. The following description assumes, that the reader is familiar with the SS7 protocol definition. SS7 support must ...
Page 140
Figure 52 Automatic Handling of Errored Signaling Units User’s Manual Hardware Description Functional Description T1/J1 140 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E F0071 ...
Page 141
CAS Bit-Robbing (T1/J1, serial mode) The signaling information is carried in the LSB of every sixth frame for each time slot. The signaling controller samples the bit stream either on the receive line side or if external signaling is ...
Page 142
If the FALC is used for HDLC formats only, the BOM receiver has to be switched off. If HDLC and BOM receiver have been switched on (MODE.HRAC/BRAC), an automatic switching between ...
Page 143
After reset, the FALC 56 must be programmed with FMR1.PMOD = 1 to enable the T1/J1 (PCM24) mode. Switching between the framing formats is done by bit FMR4.FM1⁄ 0 for the receiver and for the transmitter. 5.2.2 General Aspects ...
Page 144
When resynchronization is initiated, the following values apply for the time required to achieve the synchronous state in case there is one definite framing candidate within the data stream: Table 33 Resynchronization Timing (T1/J1) Frame Mode Average F4 1.0 F12 ...
Page 145
Auto-Mode Definite Candidate EXLS FRS DON DOFF Multiple Candidates EXLS, FRS FRS DON DOFF 1) EXLS FRS 1) : Depends on the Disturbance D One Disturbance : Figure 53 Influences on Synchronization Status (T1/J1) User’s Manual Hardware Description Functional Description ...
Page 146
Figure 53 gives an overview of influences on synchronization status for the case of different external actions. Activation of auto mode and non-auto mode is performed by bit FMR4.AUTO. Generally, for initiating resynchronization it is recommended to use bit: FMR0.EXLS ...
Page 147
Multiframe ( Format, T1/J1) Normally, this kind of multiframe structure only makes sense when using the CAS robbed-bit signaling. The multiframe alignment signal is located at the FS-bit position of every other frame (refer to Table ...
Page 148
Multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. • FMR2.SSP = 1: terminal frame and multiframe synchronization are separated Two errors within 4/5/6 terminal framing bits lead to the same reaction as ...
Page 149
Table 36 Extended Superframe Structure (F24, ESF; T1/J1) (cont’d) Multiframe Frame Number Multiframe Bit Number 15 2702 16 2895 17 3088 18 3231 19 3474 20 3667 21 3860 22 4053 23 4246 24 4439 5.2.6.1 Synchronization Procedures For multiframe ...
Page 150
FALC asynchronous state, searching for a possible additionally available framing pattern. This procedure is repeated until the framer has found three consecutive multiframe pattern in a row. • FMR2.MCSP/SSP = 10: This ...
Page 151
CRC6 generation/checking according to JT G.706 Setting of RC0.SJR the FALC JT G.706. The CRC6 checksum is calculated including the FS/DL-bits. In synchronous state CRC6 errors increment an error counter. 5.2.7 72-Frame Multiframe (SLC96 Format, T1/J1) The 72-multiframe is ...
Page 152
Table 37 72-Frame Multiframe Structure (T1/J1) Frame Number – – – – – – – ...
Page 153
Table 37 72-Frame Multiframe Structure (T1/J1) (cont’d) Frame Number – – – User’s Manual Hardware Description Functional Description T1/J1 F Signaling Channel S Designation D A – D ...
Page 154
Summary of Frame Conditions (T1/J1) Table 38 Summary Frame Recover/Out of Frame Conditions (T1/J1) Format Frame Recover Condition F4 Only one FT pattern found, optional forcing on next available FT framing candidate F12 (D4) FMR2.SSP = 0: Combined FT ...
Page 155
Additional Receive Framer Functions (T1/J1) 5.3.1 Error Performance Monitoring and Alarm Handling • Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and ISR2.AIS. Transmission is enabled by bit FMR1.XAIS. • Loss-Of-Signal: Detection and recovery is flagged ...
Page 156
Table 39 Summary of Alarm Detection and Release (T1/J1) (cont’d) Alarm Detection Condition Yellow Alarm or RC1.RRAM = 0: Remote Alarm bit 255 consecutive time 1) (RRA) slots or FS-bit = 1 of frame12 in F12 ...
Page 157
However, received data is switched through transparently if bit FMR2.DAIS is set. • Automatic clock source switching In slave mode (LIM0.MAS = 0) the DCO-R synchronizes on the recovered route clock. In case of loss-of-signal (LOS) the DCO-R ...
Page 158
SEC/FSC. Selecting the external second timer is done with GCR.SES. Refer also to register GPC1 for input/output selection. 5.3.6 Clear Channel Capability For support of common T1 ...
Page 159
Pulse-Density Detection ® The FALC 56 examines the receive data stream on the pulse-density requirement which is defined by ANSI T1. 403. More than 14 consecutive zeros or less than N ones in each and every time window of ...
Page 160
Transmit Line Interface (T1/J1) The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. The unipolar data is provided on pin XDI and the digital transmitter. Similar to ...
Page 161
Transmit Jitter Attenuator (T1/J1) The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and meets the following requirements: PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431 and G.703. The DCO-X circuitry works internally ...
Page 162
RL1/2 RDIP/N Equalizer ROID XL1/2 DRS Line XDOP/N Driver XOID Figure 55 Clocking in Remote Loop Configuration (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 RCLK DPLL DRS JATT Buffer Pulse Shaper RCLK Transmit RCLK Jitter Attenuator 162 ® FALC ...
Page 163
XL1/ XDOP/ DR XOID DR XL2/ XDON XCLK TCLK (E1: 8MHz) (T1: 6MHz) Clocking MCLK Unit Figure 56 Transmit Clock System (T1/J1) Note Dual-Rail interface DCO-X Digital Controlled Oscillator transmit 5.4.4 Transmit Elastic Buffer (T1/J1) The transmit elastic ...
Page 164
Maximum of wander channel translation mode 0 Maximum of wander channel translation mode 1 System interface clocking rate: modulo 1.544 MHz: Maximum of wander average delay after performing a slip: 96 bits ...
Page 165
XDI and XP(A:D) is programmable by bits SIC2.SICS(2:0), the remaining channel phases are cleared or ignored respectively. The following table gives an overview of the transmit buffer operating modes. Table 41 Transmit Buffer Operating ...
Page 166
Table 42 Pulse Shaper Programming (T1/J1) (cont’d) Range in Range in XPM0 m ft. Serial Resistor Value: 4 Ω 133 133 to 266 122 266 to 399 3C ...
Page 167
Figure 57 Transmit Line Monitor Configuration (T1/J1) 5.4.7 Transmit Signaling Controller (T1/J1) Similar to the receive signaling controller the same signaling methods and the same time slot assignment are provided. The FALC link methods. 5.4.7.1 HDLC or LAPD access The ...
Page 168
SS7 support must be activated by setting the MODE register. Data stored in the transmit FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following hardware features in transmit direction: • Transmission of flags at the beginning ...
Page 169
CAS Bit-Robbing (T1/J1, µP access mode) The signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side. Signaling data is sourced internally from registers XS(12:1). Internal ...
Page 170
Table 43 Structure of Periodical Performance Report (T1/J1) Octet No FLAG = 01111110 2 SAPI = 001110 3 TEI = 0000000 4 CONTROL = 00000011 = unacklowledged frame ...
Page 171
Table 44 Bit Functions in Periodical Performance Report Bit Value Interpretation Number of CRC error events = 1 1 < number of CRC error events ≤ < number of CRC error events ...
Page 172
Table 45 System Clocking and Data Rates (T1/J1) System Data Rate Clock Rate 1.544/2.048 MHz × 1.544/2.048 Mbit/s 3.088/4.096 Mbit/s - 6.176/8.192 Mbit/s - 12.352/16.384 Mbit/s - × = valid invalid Generally the data or marker on the ...
Page 173
Figure 58 System Interface (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 173 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E ...
Page 174
Receive System Interface (T1/J1) RDO FRAME 1 FRAME 2 FRAME 3 RMFB SYPR SYPR Trigger Sample 1) Edge Edge SCLKR 8.192 MHz T SCLKR 1.544 MHz RDO/RSIG Bit 255 Bit 0 2 Mbit/s Data Rate RDO/RSIG 4 Mbit/s Data ...
Page 175
Receive Offset Programming Depending on the selection of the synchronization signals (SYPR or RFM), different calculation formulas are used to define the position of the synchronization pulses. These formulas are given below, see of SYPR and RFM is always ...
Page 176
RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) SYPR SYPR SYPR Figure 60 SYPR Offset Programming (1.544 Mbit/s, 1.544 MHz) RDO (CP0) F ...
Page 177
RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) RFM RFM RFM BP = 188 (BP = bit position) Figure 62 ...
Page 178
SYPR SCLKR T TS31 TS0 RDO RSIG Time slot offset (RC0, RC1 FS/DL-bit ABCD = Signaling bits for time slots 1...24, time slot mapping according to channel translation ...
Page 179
SYPR SCLKR T TS23 TS0 RDO RSIG RSIG ...
Page 180
Figure 67 Transmit System Clocking: 1.544 MHz (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 180 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E F0005 ...
Page 181
Figure 68 Transmit System Clocking: 8.192 MHz/4.096 Mbit/s (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 181 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E F0006 ...
Page 182
SYPX SCLKX T TS31 TS0 XDI XSIG Time slot offset (RC0, RC1 FS/DL-bit ABCD = Signaling bits for time slots 1...24, time slot mapping according to channel translation ...
Page 183
Figure 71 Signaling Marker for CAS/CAS-CC Applications (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 183 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E ...
Page 184
Figure 72 Signaling Marker for CAS-BR Applications (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 184 DS1.1, 2003-10-23 ® FALC 56 PEF 2256 H/E ...
Page 185
FS/DL data on system transmit highway (XDI), time slot 0: MSB 1 Figure 73 Transmit FS/DL Bits on XDI (T1/J1) 5.5.2.1 Transmit Offset Programming The pulse length of SYPR and RFM is always the basic T1/J1 bit width (648 ns) ...
Page 186
XDI SCLKX SIC3.RESX = 1 (rising edge) SCLKX SIC3.RESX = 0 (falling edge) SYPX SYPX SYPX Figure 74 SYPX Offset Programming (1.544 Mbit/s, 1.544 MHz) XDI (CP0) F ...
Page 187
Time Slot Assigner (T1/J1) HDLC channel 1 offers the flexibility to connect data during certain time slots, as defined by registers RTR(4:1) and TTR(4:1), to the RFIFO and XFIFO, respectively. Any combinations of time slots can be programmed for ...
Page 188
The format for receive FS/DL data transmission in time slot 0 of the system interface is as shown in Figure 67 below. In order to get an undisturbed reception even in the asynchronous state bit FMR2.DAIS has to be set. ...
Page 189
Clock + RL1 Data RL2 Recovery XL1 XL2 XCLK Figure 76 Remote Loop (T1/J1) User’s Manual Hardware Description Functional Description T1/J1 RCLK Rec. Framer FIFO MUX Trans. Framer MUX RCLK DCO-R/X 189 ® FALC 56 PEF 2256 H/E Elast. RDO ...
Page 190
Payload Loop-Back To perform an effective circuit test a line loop is implemented. If the payload loop-back (FMR2.PLB) is activated the received 192 bits of payload data is looped back to the transmit direction. The framing bits, CRC6 and ...
Page 191
Local Loop The local loop-back mode, selected by LIM0. disconnects the receive lines RL1/2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by system interface are routed through the ...
Page 192
Single Channel Loop-Back (loop-back of time slots) The channel loop-back is selected by LOOP.ECLB = 1. Each of the 24 time slots can be selected for loop-back from the system PCM input (XDI) to the system PCM output (RDO). ...
Page 193
Alarm Simulation (T1/J1) Alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. However, possible real alarm conditions are not reported to the processor or to the remote end when ...
Page 194
CRC6 generation and checking according to ITU-JT G.706 (CRC checksum calculation includes FS/DL-bits, see • Remote alarm handling according to ITU-JT G.704 (remote alarm pattern in DL-channel is "1111111111111111", see on page 150) • NTT synchronization requirements in ESF ...
Page 195
Operational Description E1 6.1 Operational Overview E1 ® The FALC 56 can be operated in two modes, which are either E1 mode or T1/J1 mode. The device is programmable via a microprocessor interface which enables byte or word access ...
Page 196
Table 47 Initial Values after Reset (E1) (cont’d) Register Reset Value Meaning LOOP 00 Channel loop-back and single frame mode are disabled. H XSW 00 All bits of the transmitted service word are cleared. Spare H XSP 00 bit values ...
Page 197
Table 47 Initial Values after Reset (E1) (cont’d) Register Reset Value Meaning PC(4: Input function of ports RP(A to D): SYPR Input function of ports XP(A to D): SYPX H, H PC5 00 SCLKR, ...
Page 198
Table 48 Initialization Parameters (E1) (cont’d) Configuration System clocking and data rate Transmit offset counters Receive offset counters AIS to system interface Operational Set Up Select framing Framing additions Synchronization mode Signaling mode Features like channel loop-back, idle channel activation, ...
Page 199
Specific E1 Register Settings The following is a suggestion for a basic initialization to meet most of the E1 requirements. Depending on different applications and requirement any other initialization can be used. Table 49 Line Interface Initialization (E1) Register Setting ...
Page 200
Table 50 Framer Initialization (E1) (cont’d) Register Setting Function FMR2.FRS(2: this mode a search of double framing is automatically FMR1.AFR = 1 restarted CRC4 multiframing is found within 8ms. Together with FMR2.AXRA = 1 this ...