SAB82538H-10 Infineon Technologies AG, SAB82538H-10 Datasheet
SAB82538H-10
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SAB82538H-10 Summary of contents
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ICs for Communications Enhanced Serial Communication Controller with 8 Channels ESCC8 SAB 82538 SAF 82538 Version 2.2 User’s Manual 03.95 ...
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Edition 03.95 This edition was realized using the software ‚ system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other ...
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SAB 82538 SAF 82538 Revision History: Current Version: 03.95 Previous Version: User’s Manual 01.94 Page (in Page Subjects (changes since last revision) Version (in new 01.94) version RD/DS Description 14 14 RES pin number ...
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Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (cont’d) 2.3.4.10 Receive Address Handling (version 2 upward .72 2.4 Asynchronous Serial Mode . . ...
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Table of Contents (cont’d) 3.3.2 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction The Enhanced Serial Communication Controller ESCC8 (SAB 82538 data communication device with eight serial channels. It has been designed to implement high-speed communication links and to reduce hardware and software overhead needed for serial synchronous/asynchronous communications. Each ...
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Enhanced Serial Communication Controller (ESCC8) Preliminary Data 1 General Features Serial Interface Eight independent full duplex serial channels – On chip clock generation or external clock source – On chip DPLL for clock recovery of each channel – Eight independent ...
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Statistical multiplexing Continuous transmission bytes possible Programmable Preamble (8 bit) with selectable repetition rate (HDLC/SDLC and BISYNC) Data rate Mbit/s Master clock mode with data rate Mbit/s Protocol Support (HDLC ...
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Pin Configuration of ESCC8 (top view) Semiconductor Group P-MQFP-160 10 SAB 82538 SAF 82538 ...
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Pin Definitions and Function Pin No. Symbol Input (I) Output (O) 92 … … … 30, D0 … D15 I/O 33 … ALE I Note: All unused input pins have to be ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 95 RD/ WR/R Semiconductor Group Function Read Enable (Siemens/Intel bus mode) This signal indicates a read operation. When the ESCC8 is selected ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 81 RES I 93 BHE/BLE I 82 WIDTH I Semiconductor Group Function Reset A high signal on this pin forces the ESCC8 into reset state. During Reset the ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 105 DTACK oD 104 INT O/oD Semiconductor Group Function Data Transfer Acknowledge During a bus cycle (read/write, asynchronous bus), this signal indicates that ESCC8 is ready for data ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 98 INTA I Semiconductor Group Function Interrupt Acknowledge If the interrupt is acknowledged via pin INTA, an interrupt vector is output on D0…D7. All interrupt sources are organized ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 101 IE0 I/O 100 IE1 I 99 IE2 I Semiconductor Group Function Interrupt Enable The function depends on the selected cascading mode: Slave mode: IE0-2 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 1 DRT0 O 2 DRT1 3 DRT2 4 DRT3 5 DRT4 6 DRT5 7 DRT6 8 DRT7 160 DRR0 O 159 DRR1 DRR2 158 157 DRR3 156 DRR4 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 73 DACK0 I 74 DACK1 75 DACK2 76 DACK3 77 DACK4 78 DACK5 79 DACK6 80 DACK7 14 RXD0 I 16 RXD1 20 RXD2 (O/oD) 22 RXD3 112 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 41 RTS0 O 42 RTS1 43 RTS2 44 RTS3 45 RTS4 46 RTS5 47 RTS6 48 RTS7 134 CTS0/CxD0 I 133 CTS1/CxD1 132 CTS2/CxD2 131 CTS3/CxD3 130 CTS4/CxD4 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol Input (I) Output (O) 13 TXD0 O/oD 15 TXD1 19 TXD2 21 TXD3 113 TXD4 111 TXD5 109 TXD6 107 TXD7 9 TXCLK0 I/O 10 TXCLK1 11 TXCLK2 12 TXCLK3 118 TXCLK4 ...
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Pin Definitions and Function (cont’d) Pin No. Symbol 63 XTAL1 64 XTAL2 152 145 PA0 … PB0 … 7 142 135 PC0 … PD0 … 3 18, 32, 61 102, 114, 143 ...
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Logic Symbol Figure 1 ESCC8 Logic Symbol Semiconductor Group 22 SAB 82538 SAF 82538 ...
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Functional Block Diagram Figure 2 Functional Block Diagram SAB 82538 Semiconductor Group 23 SAB 82538 SAF 82538 ...
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The ESCC8 (SAB 82538) comprises eight completely independent full-duplex serial interfaces which support HDLC/SDLC, BISYNC and ASYNC protocols. Layer-1 functions are performed by means of internal oscillator, Baud Rate Generator (BRG), Digital Phase Locked Loop (DPLL), and Time-Slot Assignment circuits ...
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System Integration 1.4.1 General Aspects Figure 3 General System Integration of ESCC8 Figure 3 gives a general overview of system integration of ESCC8. The ESCC8’s bus interface consists of an 8/16-bit bidirectional Data bus (D0-D15), nine Address Line inputs ...
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Environment 1.4.2.1 ESCC8 with SAB 80188 Microprocessor A system with minimized additional hardware expense can be build up with a SAB 80188 microprocessor as shown in figure 4. Figure 4 ESCC8 with SAB 80188 CPU The ESCC8 is connected ...
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This solution supports applications with a high speed data rate in one serial channel with minimum hardware expense making use of the on-chip peripheral functions of the 80188 (chip select logic, interrupt controller, DMA controller). 1.4.2.2 ESCC8 with 80386 In ...
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ESCC8 with MC 68020, 68030 Figure 6 gives an example of interfacing the ESCC8 to a 32-bit Motorola microprocessor. Some glue logic is necessary. The signal BUS LOW ENABLE (BLE) has to be decoded out of transfer size information ...
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Interrupt Cascading The ESCC8 supports two cascading schemes which can be selected by programming the IPC register: Slave Mode Interrupt outputs of several devices (slaves) are connected to a priority resolving unit (e.g. interrupt controller). The slave which is ...
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Figure 8 Interrupt Cascading (Slave Mode) in Motorola Bus Mode Semiconductor Group 30 SAB 82538 SAF 82538 ...
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Daisy Chaining If selected via IPC register the Interrupt Enable pins IE0, IE1 are used for building a Daisy Chain by connecting the Interrupt Enable Output (IE0) of the higher priority device to the Interrupt Enable Input (IE1) of the ...
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Figure 10 Interrupt Cascading (Daisy Chaining) in Motorola Bus Mode For Motorola type microprocessor systems the maximum available settling time for the chain is much shorter: from the beginning of the INTA cycle to the falling edge of signal DS. ...
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Functional Description 2.1 General The ESCC8 distinguishes itself from other communication controllers by its advanced characteristics. The most important are: Eight independent serial channels. Support of HDLC, SDLC, BISYNC/MONOSYNC and Asynchronous protocols. Support of layer-2 functions (HDLC mode). In ...
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FIFO buffers for efficient transfer of data packets. A further speciality of ESCC8 are the 64-byte deep FIFO buffers used for the temporary storage of data packets transferred between the serial communications interface and the parallel system bus. Because of ...
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Link Configurations Figure 11 Point-to-Point Configuration Figure 12 Point-to-Multipoint Configuration Figure 13 Multimaster Configuration Semiconductor Group 35 SAB 82538 SAF 82538 ...
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Microprocessor Interface 2.2.1 Register Set The communication between the CPU and the ESCC8 is done via a set of directly accessible registers. The interface may be configured as Siemens/Intel or Motorola type with a selectable data bus width of ...
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Table 2 Data Bus Access (16-Bit Motorola Mode) BLE A0 Register Access 0 0 FIFO word access Register word access (even addresses Register byte access (odd addresses Register byte access (even addresses transfer ...
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Data Transfer Modes Data transfer between the system memory and the ESCC8 for all eight channels is controlled by either interrupts (Interrupt Mode), or independently from CPU, using the ESCC8's 16-channel DMA interface (DMA Mode). After RESET, the ESCC8 ...
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The structure of the interrupt status registers is shown in figure 14. Figure 14 ESCC8 Interrupt Status Registers Each interrupt indication of registers ISR0, ISR1 and PIS can be selectively masked by setting the corresponding bit in the corresponding mask ...
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Second level: Channel classification The second level considers the current priority of all channels. Especially for version 2 upward, selection is performed between – Fixed priority level assignment (version 1: channel 0 has highest and channel 7 lowest priority; version ...
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Note: Parallel ports have always lowest priority. Version 2 upward provides dynamic adjustment of channel priorities by programming ...
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Interrupt priority mode 2: Rotating priority of 8 channels With IVA.ROT = 1 and IPC.ROTM = 0 the interrupt priority rotation mode is selected. After an interrupt has been serviced the priorities of all eight channels are rotated cyclically so ...
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Interrupt priority mode 3: Rotating priority of 7 channels With IVA.ROT = 1 and IPC.ROTM = 1 the priority adjustment is performed only on 7 channels while one channel is fixed to the highest priority level. As described in “Interrupt ...
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Figure 15 Structure of Interrupt Vector Note: For IVA.EDA = 1 the interrupt vector format for version 2 is identical to version 1. Semiconductor Group 44 SAB 82538 SAF 82538 ...
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Interrupt Polling After ESCC8 has requested an interrupt by activating its INT pin, the CPU must first read the Global Interrupt Status register GIS to identify parallel port and/or channel related interrupt indications: Channel related interrupts are indicated via ...
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Implementation of the interrupt service routines should consider the two selectable interrupt vector modes (bit IVA.EDA): Interrupt vector mode 1 (EDA = 0) Interrupt vector includes: device address, version 2: parallel port indication, channel identification, interrupt group (+): fastest interrupt ...
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Subsequent actions depend on the indicated interrupt group (similar to vector mode 1): If one of interrupt groups indicated, no reading of channel assigned interrupt status registers is necessary; the corresponding interrupt indication is reset after ...
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Masked interrupt statuses are only stored internally and they become visible when the mask is withdrawn. In version 2 upward, an additional mode can be selected via bit IPC.VIS. In this mode, masked interrupt status bits still neither generate an ...
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DMA Interface The ESCC8 comprises a 16-channel DMA interface for fast and efficient data transfers. For all serial channels, a separate DMA Request output for transmit (DRT) and receive direction (DRR) as well as a DMA Acknowledgement (DACK) input ...
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FIFO Structure In all transmit and receive direction 64-byte deep FIFOs are provided for the intermediate storage of data between the serial interface and the CPU interface. The FIFOs are divided into two halves of 32-bytes. Only one half ...
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Figure 18 FIFO Word Access (Motorola Mode) Semiconductor Group 51 SAB 82538 SAF 82538 ...
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HDLC/SDLC Serial Mode 2.3.1 Operating Modes The HDLC controller of each channel can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and ...
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Non-Auto-Mode (MODE: MDS1, MDS0 = 01) Characteristics: address recognition, arbitrary window size. All frames with valid addresses (address recognition identical to auto-mode) are forwarded directly via the RFIFO to the system memory. The HDLC control field, data in the I-field ...
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Receive Data Flow (Summary) The following figure gives an overview of the management of the received HDLC frames in the different operating modes. Figure 19 Receive Data Flow of ESCC8 Semiconductor Group 54 SAB 82538 SAF 82538 ...
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Transmit Data Flow Two different types of frames can be transmitted: – frames and – transparent frames as shown below. Figure 20 Transmit Data Flow of ESCC8 For I-frames (command XIF via CMDR register), the address and control fields are ...
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Procedural Support (Layer-2 Functions) When operating in the auto mode, the ESCC8 offers a high degree of protocol support. In addition to address recognition, the ESCC8 autonomously processes all (numbered) S- and I-frames (prerequisite window size 1) with either ...
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Figure 21 Processing of Received Frames in Auto Mode Semiconductor Group 57 SAB 82538 SAF 82538 ...
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Transmission of Frames The ESCC8 autonomously transmits S commands and S responses in the auto mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit ...
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Figure 22 Timer Procedure / Poll Cycle Semiconductor Group 59 SAB 82538 SAF 82538 ...
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Examples The interaction between ESCC8 and the CPU during transmission and reception of I-frames is illustrated in figure 23, the flow control with RR/RNR during reception of I-frames in figure 24, and during transmission of I-frames in figure 25. Both ...
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Figure 25 Flow Control/Reception Figure 26 S Commands/Protocol Error Semiconductor Group 61 SAB 82538 SAF 82538 ...
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Half-Duplex SDLC-NRM Operation The LAP controllers of the eight serial channels can be configured to function in a half- duplex Normal Response Mode (NRM), where they operate as a slave (secondary) station, by setting the NRM bit in the ...
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After the frame has been transmitted (with the final bit set), the XFIFO is inhibited and the ESCC8 waits for the arrival of a positive acknowledgement. Since the on-chip timer of the ESCC8 must be operated in the external mode ...
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Figure 28 Data Reception/Transmission Figure 29 Data Transmission (no Error) Semiconductor Group 64 SAB 82538 SAF 82538 ...
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Figure 30 Data Transmission (Error) 2.3.2.3 Error Handling Depending on the error type, erroneous frames are handled according table 3. Table 3 Error Handling Frame Type Error Type I CRC error Aborted Unexpected N(S) Unexpected N(R) S CRC error Aborted ...
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SDLC Loop As a special variant of IBM’s SDLC protocol the SDLC Loop is used to connect several Secondary (= slave) Stations to one Primary (= master) Station. Different from standard HDLC, a reserved bit sequence is defined as ...
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After reception of an EOP sequence a Secondary can go to the ON Loop state. As opposed to the Off Loop State, all data is forwarded to the next station with one bit delay Secondary is requested (polled) ...
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Transmission of Frames Sending frames is only possible in the Active On Loop state. Here, transmission can start with the XTF command. If necessary, Flags as Interframe Timefill are inserted before the current frame begins (the modified EOP and the ...
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Extended Transparent Transmission and Reception When programmed in the extended transparent mode via the MODE register (MDS1, MDS0 = 11), each channel of the ESCC8 performs fully transparent data transmission and reception without HDLC framing, i.e. without FLAG insertion ...
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Continuous Transmission (DMA Mode only) If data transfer from system memory to the ESCC8 is done by DMA (DMA bit in XBCH set), the number of bytes to be transmitted is usually defined via the Transmit Byte Count registers ...
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One Bit Insertion Similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the HDLC protocol, the ESCC8 offers a completely new feature of inserting/deleting a one after seven consecutive zeros in the transmit/receive data stream, if the ...
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Receive Address Handling (version 2 upward) Mask for Address Detection The Receive Address Low/High Byte (RAL1/RAH1) can be masked by setting the corresponding bits in the mask registers (AML/AMH) to allow extended broadcast address recognition. This feature is applicable ...
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Asynchronous Serial Mode 2.4.1 Character Frame Character framing is achieved by special Start and Stop bits. Each data character is preceded by one Start bit and terminated by one or two Stop bits. The character length is selectable from ...
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Oversampling (3 samples) around the nominal bit center in conjunction with majority decision is provided for every received bit (including Start Bit). The synchronization lasts for one character, the next incoming character causes a new synchronization to be performed. As ...
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Data Transmission The selection of asynchronous or isochronous operation has no further influence on the transmitter. The bit clock rate is solely a dividing factor for the selected clock source. Transmission of the contents of XFIFO starts after the ...
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A received character is considered to be recognized as a valid XON or XOFF character – correctly framed (correct length), – if its bits match the ones in the XON or XOFF registers over the programmed character ...
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Flow Control for Received Data After writing a character value to register TIC (Transmit Immediate Character) its contents are inserted in the outgoing character stream Immediately upon writing this register by the microprocessor if the transmitter is in IDLE state. ...
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Character Oriented Serial Mode (MONOSYNC/BISYNC) 2.5.1 Data Frame Character oriented protocols achieve synchronization between transmitting and receiving station by means of special SYN characters. Two examples are the MONOSYNC and IBM’s BISYNC procedures. BISYNC has two starting SYN characters ...
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Data Reception The receiver is generally activated by setting the RAC bit in the MODE register. Additionally, the CD signal may be used to control data reception. After issuing the HUNT command, the receiver monitors the incoming data stream ...
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Data Transmission Transmission of data written to XFIFO is initiated after the Transmit Frame command (XF) is issued (the LSB is sent out first). Additionally, the CTS signal may be used to control data transmission. Further data is requested ...
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Special Functions 2.5.4.1 Preamble Transmission If enabled via register CCR3, a programmable 8-bit pattern (register PRE) is transmitted with a selectable number of repetitions after Interframe Timefill transmission is stopped and a new frame is ready to be sent ...
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Serial Interface (Layer-1 functions) The eight serial interfaces of the ESCC8 provide eight fully independent communication channels, supporting layer-1 functions to a high degree by various means of clock generation and clock recovery. Note: Since the eight serial channels ...
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The transmit clock pins (TxCLK) may also output clock signals in certain clock modes if enabled via CCR2.TOE. The clocking source for the DPLL’s is always the internal BRG; the scaling factor (divider) of the BRG can be programmed through ...
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Clock Mode 1 (Re./Trm. Strobes) Externally generated, but identical receive and transmit clocks are supplied via RxCLK. In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK. These strobe signals work on a per ...
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Depending to the value programmed via those bits, the receive/transmit window (time- slot) starts with a delay of 1 (minimum delay 512 clock periods following the frame synchronization signal and is active for the number of clock periods ...
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Summary The features of the different clock modes are summarized in table 5. Table 5 Clock Modes of ESCC8 Channel Clock Sources Configur OSC – OSC OSC 1 X OSC – OSC RxCLK 2b ...
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Restrictions for frequency ratios between receive frequency (fr), transmit frequency (fx) and master clock frequency (fm): Normal mode; clock mode 0, 2a, and 6a: fr/fx < 3 (*) Master clock mode: fm/fx cycle (*); fr/fm < 3 (**) (*) for ...
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The following functions have been implemented to facilitate a fast and reliable synchronization: – Interference Rejection and Spike Filtering In the case where two or more edges appear in the data stream within a time period of 16 reference clocks, ...
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Figure 36 DPLL Algorithm for NRZ and NRZI Coding with Phase Shift Enabled (CCR3.PSD = 0) Figure 37 DPLL Algorithm for NRZ and NRZI Encoding with Phase Shift Disabled (CCR3.PSD = 1) Semiconductor Group 89 SAB 82538 SAF 82538 ...
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Figure 38 DPLL Algorithm for FM0, FM1 and Manchester Coding To supervise correct function when using bi-phase encoding, a status flag and a maskable interrupt inform about synchronous/asynchronous state of the DPLL. Semiconductor Group 90 SAB 82538 SAF 82538 ...
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Bus Configuration Beside the point-to-point configuration, the ESCC8 effectively supports point-to- multipoint (pt-mpt or bus) configurations by means of internal idle and collision detection/ collision resolution methods pt-mpt configuration, comprising a central station (master) and several peripheral ...
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Collisions During the transmission, the data transmitted compared with the data case of a mismatch (1 sent and 0 detected, or vice versa) data transmission is immediately aborted, and idle (logical ...
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Priority (HDLC/SDLC Mode Only) To ensure that all competing stations are given a fair access to the transmission medium, once a station has successfully completed the transmission of a frame given a lower level of priority. This ...
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Functions of RTS Output In clock modes 0, 1 and 4, the RTS output can be programmed via CCR2 (SOC bits active when data (frame or character) is being transmitted. This signal is delayed by one clock ...
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Data Encoding The ESCC8 supports the following coding schemes for serial data: – Non-Return-To-Zero (NRZ) – Non-Return-To-Zero-Inverted (NRZI) – FM0 (also known as Bi-Phase Space) – FM1 (also known as Bi-Phase Mark) – Manchester (also known as Bi-Phase) NRZ: ...
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Figure 41 FM0 and FM1 Data Encoding Manchester: In the first half of the bit cell the physical signal level corresponds to the logical value of the data bit. At the center of the bit cell this level is inverted. ...
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Modem Control Functions (RTS/CTS, CD) 2.6.5.1 RTS/CTS Handshaking The ESCC8 provides two pins (RTS, CTS) per serial channel supporting the standard RTS-modem handshaking procedure for transmission control. A transmit request will be indicated by outputting logical “0” on the ...
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Figure 43 RTS – CTS Handshaking Beyond this standard RTS function, signifying a transmission request of a frame (Request To Send), the RTS output may be programmed for a special function via SOC1, SOC0 bits in the CCR2 register, provided ...
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Test Mode To provide for fast and efficient testing, the ESCC8 can be operated in a test mode by setting the TLP bit in the MODE register. The on-chip serial input and output (T D-R D) are connected, generating ...
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Operational Description 3.1 Reset The ESCC8 is forced into the reset state if the RES pin is set “high” for at least 5 microseconds. During RESET, the ESCC8 is temporarily in the power-up mode, and a subset of the ...
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Register Reset Value MODE 00 H IMR0 FF H IMR1 FF H PIM FF H IPC 00 H PCR FF H IVA 00 H PRE 00 H XBCH 00 H STAR 48 H AML/MXN 00 H AMH/MXF 00 H TSAX ...
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Initialization After Reset the CPU has to write a minimum set of registers and an optional set dependent on the required features and operating modes. First, the serial mode, the configuration of the serial port and the clock mode ...
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Table 6 Initialization of ESCC8 (cont’d) Item Serial Mode Specific Features HDLC/SDLC ASYNC BISYNC User Demands Modem control lines Parallel Port Interrupt features DMA features Timer (external mode) Semiconductor Group Registers Comment MODE, TIMR refer XAD1, XAD2 to RAH1, RAH2 ...
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Table 7 HDLC Specific Register Setup Address Mode Operating Mode Auto Non Auto Transparent Semiconductor Group 2 Byte Address Field (MODE.ADM = 1) RAH2 RAH2 RAL1 RAL2 AML AMH RAH2 RAH2 RAL1 RAL2 AML AMH RAH1 RAH2 AMH 104 SAB ...
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Operational Phase After having performed the initialization, the CPU switches each individual channel of the ESCC8 into operational phase by setting the PU bit in the CCR0 register. Initially, the CPU should bring the transmitter and receiver into a ...
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ASYNC: The transmission of character(s) can be started by issuing a XF command via the CMDR register. The ESCC8 will repeatedly request for the next data block by means of a XPR interrupt as soon as no more than 32 ...
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The activities at both serial and CPU interface during frame transmission (supposed frame length = 70 bytes) are shown in figure 45. Figure 45 Interrupt Driven Transmission Sequence Example (HDLC) 3.3.1.2 DMA Mode Prior to data transmission, the length of ...
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Figure 46 DMA Driven Transmission Sequence Example (HDLC) 3.3.2 Data Reception 3.3.2.1 Interrupt Mode Also 2 32 byte FIFO buffers (receive pools) are provided for each channel in receive direction. There are different interrupt indications concerned with the reception of ...
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Table 8 Status Information after RME Interrupt Length of message (bytes) Address combination and/or Address field Control field Type of frame (COMMAND / RESPONSE) CRC result (good / bad) Valid frame (yes / no) ABORT sequence recognized (yes / no) ...
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Figure 47 Interrupt Driven Reception Sequence Example (HDLC) 3.3.2.2 DMA Mode If the RFIFO contains 32 bytes, the ESCC8 autonomously requests a block data transfer by DMA by activating the DRR line for as long as the start of the ...
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Figure 48 DMA Driven Reception Sequence Example (HDLC) Semiconductor Group 111 SAB 82538 SAF 82538 ...
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Detailed Register Description In the register description the register addresses are specified by an “offset” relative to the “base addresses”, which are 000, 040, 080, 0C0, 100, 140, 180, 1C0 for the eight channels, respectively. 4.1 Status/Control Registers in ...
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Table 9 Register Addresses in HDLC Mode (cont’d) Address (A8… A0) Channel 036 076 0B6 0F6 037 077 0B7 0F7 038, 078, 0B8, 0F8, 138, 178, 1B8, 1F8 039, 079, 0B9, 0F9, 139, 179, 1B9, 1F9 ...
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DMA Controlled Data Transfer (DMA Mode) Selected if DMA bit in XBCH is set. If the RFIFO is filled up to its threshold level, the ESCC8 autonomously requests a block data transfer by DMA by activating the DRRn line until ...
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Status Register (READ) Value after RESET STAR XDOV XFW XRNR RRNR XDOV… Transmit Data Overflow More than 32 bytes have been written to the XFIFO. This bit is reset by: – a transmitter reset command XRES – ...
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CTS… Clear To Send State This bit indicates the state of the CTS pin. 0… CTS is inactive (high) 1… CTS is active (low) WFA… Wait For Acknowledgment (significant in auto-mode only). Indicates the “Wait for I frame Acknowledgment” status ...
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If XREP is set to one together with XTF and XME (write 2A ESCC8 repeatedly transmits the contents of the XFIFO (1… 32 bytes) without HDLC framing fully transparently, i.e. without FLAG, CRC or Bit Stuffing. The cyclic transmission is ...
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Preamble Register (WRITE) Value after RESET PRE PR7 This register defines the pattern which is sent out during preamble transmission (refer to register CCR3). Note: It should be taken into consideration that Zero Bit Insertion is disabled ...
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RDO… Receive Data Overflow A data overflow has occurred during reception of the frame. Additionally, an interrupt can be generated (refer to ISR1.RDO/ IMR1.RDO). CRC… CRC Compare/Check 0… CRC check failed; received frame contains errors. 1… CRC check o.k.; received ...
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Mode Register (READ/WRITE) Value after RESET MODE MDS1 MDS0 ADM MDS1… MDS0… Mode Select The operating mode of the HDLC controller is selected. 00… auto-mode 01… non auto-mode 10… transparent mode 11…extended transparent mode ADM… Address Mode ...
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TMD… Timer Mode Determines the operating mode of the timer. 0… external mode The timer is controlled by the CPU and can be started at any time by setting the STI bit in CMDR. 1… internal mode The timer is ...
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Timer Register (READ/WRITE) 7 TIMR CNT VALUE… (5 bits) Sets the time period (VALUE + 1) 1 where k – is the timer resolution factor which is either 32 768 or 512 clock cycles dependent on the ...
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XAD1 constitutes the high byte of the 2-byte address field. Bit 1 must be set to 0. According to the ISDN LAPD protocol, bit 1 is interpreted as the C/R (COMMAND/ RESPONSE) bit. ...
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Receive Address Byte High Register 1 (WRITE) 7 RAH1 In operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in RAH1 and RAH2. In versions 2 and ...
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Receive Address Byte High Register 2 (WRITE) 7 RAH2 RAH2… Value of second individual high address byte. MCS… Modulo Count Select (valid in auto-mode only!) The MCS bit determines the HDLC control field format. 0… basic operation, one-byte control field ...
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Extended Transparent Modes READ Access only: (Write access has no influence) RAL1 contains the current data byte assembled from the R is by-passed (fully transparent reception without HDLC framing). In versions 2 upward, this register can be ...
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Note 1: S-frames are handled automatically and are not transferred to the microprocessor. Note 2: For U-frames (bit 0 of RHCR = 1) the control field the modulo 8 case. Note 3: For I-frames (bit 0 of ...
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Transmit Byte Count Low (WRITE) 7 XBCL XBC7 Together with XBCH (bits XBC11…XBC8) this register is used in DMA Mode only, to program the length (1…4096 bytes) of the next frame to be transmitted. In terms of the value xbc, ...
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Transmit Byte Count High (WRITE) Value after RESET: 000 xxxxx 7 XBCH DMA NRM DMA… DMA Mode Selects the data transfer mode of ESCC8 to/from System Memory. 0… Interrupt controlled data transfer (Interrupt Mode). 1… DMA controlled data transfer (DMA ...
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Channel Configuration Register 0 (READ/WRITE) Value after RESET CCR0 PU MCE Note: Unused bits have to be set to logical “0”. PU… Switches between power up and power down mode 0… power down (standby) 1… power up ...
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Channel Configuration Register 1 (READ/WRITE) Value after RESET CCR1 SFLG GALP SFLG… Enable Shared Flags If this bit is set, the closing FLAG of a preceding frame simultaneously becomes the opening FLAG of the following frame. GALP… ...
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ODS… Output Driver Select Defines the function of the transmit data pin (T 0… pin is an open drain output. 1… pin is a push-pull output. Note: This feature is also valid for pin R function ...
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Channel Configuration Register 2 (READ/WRITE) Value after RESET The meaning of the individual bits in CCR2 depends on the clock mode selected via CCR1 as follows: 7 CCR2 clock mode SOC1 SOC0 0a, 1 clock mode BR9 BR8 ...
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SSEL… Clock Source Select Selects the clock source in clock modes and 7 (refer to table 5). TOE… TxCLK Output Enable 0… T CLK pin is input. 1… T CLK pin is switched to output function ...
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EPT… Enable Preamble Transmission This bit enables transmission of a preamble. The preamble is started after Interframe Timefill transmission has been stopped and a new frame transmitted. The preamble consists of an 8-bit pattern repeated a number ...
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PSD… DPLL Phase Shift Disable Only applicable in the case of NRZ and NRZI encoding. If this bit is set to “1”, the Phase Shift function of the DPLL is disabled. In this case the windows for Phase Adjustment are ...
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Transmit Channel Capacity Register (WRITE) This register is only used in clock mode 5! Value after RESET XCCR XBC7 XBC7 – XBC0… Transmit Bit Number Count, Bit 7-0 Defines the number of bits to be transmitted within ...
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VN3 – VN0… Version Number of Chip 0… Version 1 1… Version 2 Baud Rate Generator Register (WRITE) 7 BGR BR7 BR7 – BR0… Baud Rate, Bit 7-0 Together with bits BR9, BR8 of CCR2, determines the division factor of ...
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Address Mask Low (WRITE) (Version 2 upwards) Value after RESET AML AML7 The Receive Address Low Byte (RAL1) can be masked by setting corresponding bits in this mask register to allow extended broadcast address recognition. This feature ...
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CII… Channel Interrupt Indication Set if at least one interrupt source of any channel is active. CN2 – CN0… Channel Number (0.. least one interrupt source is active (bit CII is set), these bits point to the channel ...
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T7 – T6… Device Address These bits define the value of bits 6 and 7 of the interrupt vector which is sent out on the data bus (D0… D7) during the interrupt acknowledge cycle. T5… Device Address Version 1: Device ...
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Interrupt Port Configuration (READ/WRITE) Value after RESET IPC VIS ROTM SLA2 SLA1 SLA0 CASM Note: Unused bits have to be set to logical “0”. IPC is accessible via eight channel addresses (039 VIS… Masked Interrupts Visible (version ...
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IC1, IC0… Interrupt Port Configuration These bits define the function of the interrupt output stage (pin INT): IOC1 Interrupt Status Register 0 (READ) Value after RESET ISR0 RME RFS All bits are reset when ...
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RSC… Receive Status Change (significant in auto-mode only) A status change (receiver ready/receiver not ready) of the remote station has been detected by receiving a RR/RNR supervisory frame. The actual status can be read from the STAR register (RRNR bit). ...
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Interrupt Status Register 1 (READ) 7 ISR1 EOP OLP/ RDO All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding interrupt vector is output. Note: If bit IPC.VIS is set to “1”, interrupt statuses in ...
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This bit is set – if the last bit of the current frame is completely sent out on T XFIFO is empty (non-auto mode, transparent modes). – I-Frame is completely sent out on T acknowledgment has been received ...
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In case an XMR interrupt has occured, an ALLS interrupt is generated one clock period later automatically. XPR... Transmit Pool Ready A data block bytes can be written to the transmit FIFO. XPR enables the fastest ...
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Port Value Register Port A...D (READ/WRITE) 7 PVRA PVR7 PVRB PVR7 PVRC PVR7 PVRD 0 0 Note: Unused bits have to be set to logical “0”. Each PVR register is accessible via two channel addresses. Each of the above bits ...
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Port Interrupt Status Register Port A...D (READ) 7 PISA PIS7 PISB PIS7 PISC PIS7 PISD 0 0 Each PIS register is accessible via two channel addresses. Each of the above bits is assigned to the corresponding Universal Port pin with ...
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Port Interrupt Mask Register Port A...D (WRITE) Value after RESET PIMA PIM7 PIMB PIM7 PIMC PIM7 PIMD 0 0 Note: Unused bits have to be set to logical “0”. Each PIM register is accessible via two channel ...
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Port Configuration Register Port A...D (READ/WRITE) Value after RESET PCRA PCR7 PCRB PCR7 PCRC PCR7 PCRD 0 0 Note: Unused bits have to be set to logical “0”. Each PCR register is accessible via two channel addresses. ...
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Channel Configuration Register 4 (READ/WRITE) (Version 2 upwards) Value after RESET CCR4 0 0 Note: Unused bits have to be set to logical “0”. RFT1, RFT0 … RFIFO Threshold Level The size of the accessible part of ...
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Status/Control Registers in ASYNC Mode 4.2.1 Register Addresses Table 10 Register Addresses in ASYNC Mode Address (A8 … A0) Channel 000 040 080 0C0 … … … … 01F 05F 09F 0DF 020 060 0A0 ...
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Register Definitions Receive FIFO (READ) RFIFO (offset: 00…1F) Received data stored in RFIFO (LSB is received first) can be organized in one of two selectable ways (refer to figure 49): – pure data character length of ...
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Interrupt Controlled Data Transfer (Interrupt Mode) Selected if DMA bit in XBCH is reset bytes/16 words of received data can be read from the RFIFO following a RPF or a TCD interrupt depending on the selected RFIFO ...
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DMA Mode Selected if DMA bit in XBCH is set. Prior to any data transfer, the actual byte count to be transmitted must be written to the XBCH, XBCL registers by the user. Correct transmission of data in the case ...
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TEC… TIC Executing This status bit indicates that transmission instruction of currently programmed TIC (Transmit Immediate Character) is accepted but not completely executed. Further access to register TIC is only allowed after STAR.TEC has been reset by the ESCC8. Note: ...
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Command Register (WRITE) Value after RESET CMDR RMC RRES RFRD Note: Unused bits have to be set to logical “0”. The maximum time between writing to the CMDR register and the execution of the command is 2.5 ...
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ESCC8 by DMA. Serial data transmission starts as soon as 32 bytes/16 words are stored in the XFIFO or the Transmit Byte Counter value is reached. XRES… Transmitter Reset XFIFO is cleared of any data and IDLE (logical ...
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RTS… Request To Send Defines the state and control of RTS pin. 0… The RTS pin is controlled by the ESCC8 autonomously. RTS is activated when data transmission starts and deactivated when transmission is completed. 1… The RTS pin is ...
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XON Character (READ/WRITE) Value after RESET XON XON7 This register is used to specify the XON character. It can be used in conjunction with the interrupt status ISR1.XON for automatic in-band flow control (if MODE.FLON = “0”). ...
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Termination Character Register (READ/WRITE) Value after RESET TCR TCR7 TCR7–TCR0… Termination Character If enabled via register RFC the received data stream is monitored for the occurrence of a programmed “termination character”. When such a character is found, ...
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STOP… Stop Bit This bit defines the number of Stop bits generated by the transmitter: 0…1 Stop bit. 1…2 Stop bits. PAR1, PAR0… Parity Format If parity check/generation is enabled by setting PARE, these bits define the parity type: 00… ...
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RFIFO Control Register (READ/WRITE) Value after RESET RFC 0 DPS Note: Unused bits have to be set to logical “0”. DPS… Disable Parity Storage Only valid if parity check/generation is enabled via DAFO.PARE and character length is ...
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RFTH1, RFTH0… RFIFO Threshold Level These bits define the level up to which RFIFO is filled with valid data: RFTH1 the threshold level is reached, the RPF interrupt is generated if enabled. After RPF ...
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Transmit Byte Count Low (WRITE) 7 XBCL XBC7 Together with XBCH (bits XBC11…XBC8) this register is used in DMA Mode only, to program the length (1…4096 bytes) of the next data block to be transmitted. In terms of the value ...
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CAS… Carrier Detect Auto Start When set, a high on the CD pin enables the corresponding receiver and data reception is started. When not set, if not in Clock Mode the CD pin can be used as ...
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Channel Configuration Register 0 (READ/WRITE) Value after RESET CCR0 PU MCE Note: Unused bits have to be set to logical “0”. PU… Switches between power up and power down mode 0… power down (standby) 1… power up ...
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Channel Configuration Register 1 (READ/WRITE) Value after RESET CCR1 0 0 Note: Unused bits have to be set to logical “0”. ODS… Output Driver Select Defines the function of the transmit data pins (T DA, T DB) ...
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Channel Configuration Register 2 (READ/WRITE) Value after RESET The meaning of the individual bits in CCR2 depends on the clock mode selected via CCR1 as follows: 7 CCR2 clock mode 0a, 1 SOC1 SOC0 clock mode 0b, 2, ...
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BDF... Baud Rate Division Factor 0…The division factor of the baud rate generator is set to 1 (constant). 1…The division factor is determined by BR9 - BR0 bits in CCR2 and BRG registers. SSEL... Clock Source Select Selects the clock ...
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Time-Slot Assignment Register Transmit (WRITE) This register is only used in clock mode 5! Value after RESET TSAX TSNX… Time-slot Number Transmit Selects one possible time-slots ( which data ...
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Receive Channel Capacity Register (WRITE) This register is only used in clock mode 5! Value after RESET RCCR RBC7 RBC7– RBC0… Receive Bit Count, Bit 7-0 Defines the number of bits to be received within a time-slot: ...
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Baud Rate Generator Register (WRITE) 7 BGR BR7 BR7– BR0… Baud Rate, bits 7-0 Together with bits BR9, BR8 of CCR2, determines the division factor of the baud rate generator. In terms of the value division factor ...
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Mask XON Character (WRITE) (Version 2 upwards) Value after RESET MXN MXN7 This register is used to masked single bit positions of the XON character. Refer to the description of the XON register. The number of significant ...
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Global Interrupt Status Register (READ) Value after RESET GIS PIA PIB This status register points to pending – channel assigned interrupts (ISR0_x, ISR1_x) – universal port interrupts (PISA…D). GIS is accessible via eight channel addresses (038 H ...
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Interrupt Vector Address (WRITE) Value after RESET IVA T7 T6 Note: Unused bits have to be set to logical “0”. IVA is accessible via eight channel addresses ( 1F8 H ). Version 2 upward provides ...
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T4– T2… Device Address Extension In Interrupt vector mode 2 (bit EDA set) these bits define the value of bits the interrupt vector which is sent out on the data bus (D0…D7) during the interrupt acknowledge ...
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ROTM… Rotating Interrupt Priority Mode (version 2 upward) Together with bit IVA.ROT the interrupt priority mode is selected. 0 … With IVA.ROT = 1 the priorities of all 8 serial channels are rotated cyclically after an interrupt has been serviced. ...
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Interrupt Status Register 0 (READ) Value after RESET ISR0 TCD TIME PERR FERR PLLA CDSC RFO All bits are reset when ISR0 is read. Additionally, TCD and RPF are reset when the corresponding interrupt vector is output. ...
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PLLA… DPLL Asynchronous This bit is only valid when the receive clock is supplied by the DPLL and FM0, FM1 or Manchester data encoding is selected set when the DPLL has lost synchronization. Reception is disabled (IDLE is ...
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Interrupt Status Register 1 (READ) Value after RESET ISR1 BRK BRKT ALLS XOFF All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding interrupt vector is output. Note: If bit IPC.VIS is ...
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Interrupt Mask Register 0, 1 (WRITE) Value after RESET IMR0 TCD TIME PERR FERR PLLA CDSC RFO IMR1 BRK BRKT ALLS XOFF Each interrupt source can generate an interrupt signal at port INT (characteristics ...
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Port Value Register Port A...D (READ/WRITE) 7 PVRA PVR7 PVRB PVR7 PVRC PVR7 PVRD 0 0 Note: Unused bits have to be set to logical “0”. Each PVR register is accessible via two channel addresses. Each of the above bits ...
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Port Interrupt Status Register Port A...D (READ) 7 PISA PIS7 PISB PIS7 PISC PVR7 PISD 0 0 Each PIS register is accessible via two channel addresses. Each of the above bits is assigned to the corresponding Universal Port pin with ...
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Port Interrupt Mask Register Port A...D (WRITE) Value after RESET PIMA PIM7 PIMB PIM7 PIMC PIM7 PIMD 0 0 Note: Unused bits have to be set to logical “0”. Each PIM register is accessible via two channel ...
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Port Configuration Register Port A...D (READ/WRITE) Value after RESET PCRA PCR7 PCRB PCR7 PCRC PCR7 PCRD 0 0 Note: Unused bits have to be set to logical “0”. Each PCR register is accessible via two channel addresses. ...
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Status/Control Registers in BISYNC Mode 4.3.1 Register Addresses Table 11 Register Addresses in BISYNC Mode Address (A8 … A0) Channel 000 040 080 0C0 … … … … 01F 05F 09F 0DF 020 060 0A0 ...
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Register Definitions Receive FIFO (READ) RFIFO (offset: 00…1F) Received data stored in RFIFO (LSB is received first) can be organized in one of two selectable ways (refer to figure 50): – pure data character length of ...
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Interrupt Controlled Data Transfer (Interrupt Mode) Selected if DMA bit in XBCH is set to “0” bytes/16 words of received data can be read from the RFIFO following a RPF or a TCD interrupt depending on the ...
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Interrupt Mode Selected if DMA bit in XBCH is reset bytes/16 words of transmit data can be written to the XFIFO following an XPR interrupt. DMA Mode Selected if DMA bit in XBCH is set. Prior to ...
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CEC… Command Executing 0… no command is currently executed, the CMDR register can be written to. 1… a command (written previously to CMDR) is currently executed, no further command can be temporarily written in CMDR register. Note: CEC will be ...
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RFRD… Receive FIFO Read Enable The CPU can have access to RFIFO by issuing the RFRD command before threshold level or the end condition (TCD) are fulfilled. After issuing the RFRD command, the CPU has to wait for TCD interrupt, ...
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Preamble Register (WRITE) Value after RESET PRE PR7 This register defines the 8-bit pattern which is sent out during preamble transmission (refer to register CCR3). Mode Register (READ/WRITE) Value after RESET MODE 0 0 ...
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TRS… Timer Resolution Selects the resolution of the internal timer (factor register): k 0… 768 k 1… = 512 TLP… Test Loop Input and output of the BISYNC channels are internally connected. (e.g. transmitter channel 0 - receiver ...
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SYN Character Register Low, High (READ/WRITE) Value after RESET: 00 SYNL SYNH In conjunction with bit BISNC and bit SLEN the SYN character can be specified: – MONOSYNC mode (BISNC = 0) The SYN character is defined ...
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Data Format (READ/WRITE) Value after RESET DAFO 0 0 Note: Unused bits have to be set to logical “0”. PAR1, PAR0… Parity Format If parity check/generation is enabled by setting PARE, these bits define the parity type: ...
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RFIFO Control Register (READ/WRITE) Value after RESET: 00H 7 RFC 0 DPS SLOAD RFDF RFTH1 RFTH0 Note: Unused bits have to be set to logical “0”. DPS… Disable Parity Storage Only valid if parity check/generation is enabled via DAFO.PARE and ...
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RFDF… RFIFO Data Format 0… only data bytes (character plus optional parity bit) are stored. 1… additionally to every data byte, an attached status byte is stored. RFDF = 0 – character 5 – 8 bit or ...
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CPU. To indicate that this RFIFO pool can be released, an RMC command has to be issued. TCDE… Termination Character Detection Enable When this bit is set, the received data stream is monitored for “termination character” (TCR register). ...