MPC9653A Freescale Semiconductor, Inc, MPC9653A Datasheet
MPC9653A
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MPC9653A Summary of contents
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... VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running at either the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F The MPC9653A has a differential LVPECL reference input along with an external feedback input ...
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... V CC 3⋅25 k PLL_EN VCO_SEL BYPASS MR/ GND QFB GND PLL_EN BYPASS VCO_SEL Figure 2. MPC9653A 32-Lead Package Pinout (Top View) MPC9653A 2 ÷ Ref & 1 ÷ 2 VCO 1 PLL 200-500 MHz FB Note 1. PLL will lock @ 145 MHz Figure 1. MPC9653A Logic Diagram 24 23 ...
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... Control Default PLL_EN 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs ...
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... Functional operation is obtained when the crosspoint is within the V CMR and the input swing lies within the The MPC9653A is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V MPC9653A meets the V and V ...
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... PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/ ÷ 8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/ bypass mode, the MPC9653A divides the input reference clock. 5. The input frequency f must match the VCO frequency range divided by the feedback divider ratio FB: f REF 6 ...
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... APPLICATIONS INFORMATION 500 MHz for stable and optimal operation. Two operating frequency ranges are supported 62.5 MHz and 50 to 125 MHz. Table 7 the MPC9653A. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the input frequency is within the specified PLL reference frequency range. Operation Ratio ...
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... Figure 5, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653A clock driver is effectively doubled due to its capability to drive multiple lines. = [-17ps...117ps] + [-150ps...150ps] + [(10ps @ -3) ...
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... Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9653A output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs ...
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... Reference GND t (PD) , static phase (PD) offset) Test Reference –T mean| JIT(∅ for a controlled edge with respect Figure 13. I/O Jitter –1/f | JIT(PER Figure 15. Period Jitter 2.4 0.55 MPC9653A CMR = –1 ÷ ...
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... PIN 1 INDEX E1 DETAIL D 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ ( (L1) DETAIL AD MPC9653A 10 PACKAGE DIMENSIONS 4X 0. 32X 0.1 C BASE PLATING METAL 0. SECTION F 0.25 GAUGE PLANE θ ...
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... Advanced Clock Drivers Device Data Freescale Semiconductor NOTES MPC9653A 11 ...
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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC9653A Rev. 4 10/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...