MPC9653A Freescale Semiconductor, Inc, MPC9653A Datasheet

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MPC9653A

Manufacturer Part Number
MPC9653A
Description
3.3 V 1:8 LVCMOS PLL Clock Generator
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.
3.3 V 1:8 LVCMOS PLL Clock
Generator
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 125 MHz and output skews less than 150 ps the
device meets the needs of the most demanding clock applications.
Features
Functional Description
input reference clock. Normal operation of the MPC9653A requires the connec-
tion of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to
62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the ref-
erence clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal
VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a
low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F
as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-
pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes
the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close
the phase locked loop, enabling the PLL to recover to normal operation.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an
effective fanout of 1:16. The device is packaged in a 7x7 mm
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and
The MPC9653A utilizes PLL technology to frequency lock its outputs onto an
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
1:8 PLL based low-voltage clock generator
32-lead Pb-free Package Available
Supports zero-delay operation
3.3 V power supply
Generates clock signals up to 125 MHz
PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
Maximum output skew of 150 ps
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32-lead LQFP packaging
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC953 and MPC9653
2
32-lead LQFP package.
PLL CLOCK GENERATOR
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
MPC9653A
ref
3.3 V LVCMOS 1:8
Pb-FREE PACKAGE
LOW VOLTAGE
= 36.25 MHz.
CASE 873A-03
CASE 873A-03
FA SUFFIX
AC SUFFIX
Rev 4, 10/2004
MPC9653A

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MPC9653A Summary of contents

Page 1

... VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running at either the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F The MPC9653A has a differential LVPECL reference input along with an external feedback input ...

Page 2

... V CC 3⋅25 k PLL_EN VCO_SEL BYPASS MR/ GND QFB GND PLL_EN BYPASS VCO_SEL Figure 2. MPC9653A 32-Lead Package Pinout (Top View) MPC9653A 2 ÷ Ref & 1 ÷ 2 VCO 1 PLL 200-500 MHz FB Note 1. PLL will lock @ 145 MHz Figure 1. MPC9653A Logic Diagram 24 23 ...

Page 3

... Control Default PLL_EN 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs ...

Page 4

... Functional operation is obtained when the crosspoint is within the V CMR and the input swing lies within the The MPC9653A is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V MPC9653A meets the V and V ...

Page 5

... PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/ ÷ 8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/ bypass mode, the MPC9653A divides the input reference clock. 5. The input frequency f must match the VCO frequency range divided by the feedback divider ratio FB: f REF 6 ...

Page 6

... APPLICATIONS INFORMATION 500 MHz for stable and optimal operation. Two operating frequency ranges are supported 62.5 MHz and 50 to 125 MHz. Table 7 the MPC9653A. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the input frequency is within the specified PLL reference frequency range. Operation Ratio ...

Page 7

... Figure 5, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653A clock driver is effectively doubled due to its capability to drive multiple lines. = [-17ps...117ps] + [-150ps...150ps] + [(10ps @ -3) ...

Page 8

... Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9653A output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs ...

Page 9

... Reference GND t (PD) , static phase (PD) offset) Test Reference –T mean| JIT(∅ for a controlled edge with respect Figure 13. I/O Jitter –1/f | JIT(PER Figure 15. Period Jitter 2.4 0.55 MPC9653A CMR = –1 ÷ ...

Page 10

... PIN 1 INDEX E1 DETAIL D 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ ( (L1) DETAIL AD MPC9653A 10 PACKAGE DIMENSIONS 4X 0. 32X 0.1 C BASE PLATING METAL 0. SECTION F 0.25 GAUGE PLANE θ ...

Page 11

... Advanced Clock Drivers Device Data Freescale Semiconductor NOTES MPC9653A 11 ...

Page 12

... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MPC9653A Rev. 4 10/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...

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