CY7C1353B Cypress Semiconductor Corporation., CY7C1353B Datasheet
CY7C1353B
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CY7C1353B Summary of contents
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... The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to en- able consecutive Read/Write operations with data being trans- ferred on every clock cycle ...
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... V 20 DDQ DDQ Document #: 38-05266 Rev. ** PRELIMINARY 100-Pin TQFP CY7C1353B CY7C1353B DDQ DDQ ...
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... Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE , and CE 2 Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE and CE 1 Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE and CE CY7C1353B DDQ A ...
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... DNU - Functional Overview The CY7C1353B is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN) ...
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... OE. Burst Write Accesses The CY7C1353B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ad- dress, as described in the Single Write Access section above ...
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... Valid Linear Burst Sequence Fourth First Address Address Ax+1, Ax Ax+ CY7C1353B CLK Comments x X L-H I/Os three-state following next rec- ognized clock. X L-H Clock Ignored, all operations sus- pended. X L-H Address Latched. L-H Address Latched, data presented two valid clocks later. X L-H Burst Read Operation ...
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... IN DDQ Max Device Deselected, or 8.5-ns cycle, 117 MHz > DDQ 10-ns cycle, 100 MHz 1/t MAX CYC 15-ns cycle, 66 MHz 20-ns cycle, 50 MHz 25-ns cycle, 40 MHz CY7C1353B Ambient [8] Temperature DDQ 0°C to 70°C 3.3V 5% Min. Max. Unit 3.135 3.465 3.135 3.465 2.4 0.4 2.0 V 0.3V DD ...
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... Document #: 38-05266 Rev. ** PRELIMINARY Test Conditions T = 25° MHz 3. 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1353B Max ALL INPUT PULSES 3.0V GND Symbol TQFP Typ. Units 28 °C °C/W JC Unit Notes ...
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... Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 8.5 10 117 100 1.9 1.9 1.9 1.9 2.0 2.0 0.5 0.5 7.5 8.5 1.5 1.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 1.5 4.2 1.5 5.0 3.0 3.0 [10, 12, 4.2 5.0 [10, 12, 13 [12] 4.2 5.0 is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1353B -66 -50 -40 15.0 20.0 25 5.0 6.0 7.0 5.0 6.0 7.0 2.0 2.0 2.5 0.5 1.0 1.0 11 12.0 14.0 1.5 1.5 1.5 2.0 2.0 2.5 0.5 1.0 1.0 2.0 2.0 2.5 0.5 1.0 1.0 2.0 2.0 2.5 0.5 1.0 1.0 2.0 2.0 2.5 0.5 1.0 1.0 2.0 2.0 2.5 0.5 1.0 1.0 1.5 5.0 1 ...
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... CHZ Out Out In to define a Write Cycle (see Write Cycle Description table and CE . All Chip Selects need to be active in order to select UNDEFINED = DON’T CARE CY7C1353B t t CENH CENS RA6 RA7 t CHZ Out Out Page ...
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... CHZ DH Q1+2 Q1+3 D2 Out Out In Out t DS defines a write cycle (see Write Cycle Description table). [1:0] , and CE . All Chip Enables need to be active in order to select UNDEFINED = DON’T CARE CY7C1353B RA3 t CLZ Q3 D2+2 D2+3 D2+1 Out input signals. [1:0] Page Q3+1 Out ...
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... Switching Waveforms OE Timing Ordering Information Speed (MHz) Ordering Code 117 CY7C1353B-117AC 100 CY7C1353B-100AC 66 CY7C1353B-66AC CY7C1353B-66BGC 50 CY7C1353B-50AC CY7C1353B-50BGC 40 CY7C1353B-40AC Shaded areas contain advance information. Document #: 38-05266 Rev. ** PRELIMINARY OE t EOHZ Three-state I/O’s t EOLZ Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05266 Rev. ** PRELIMINARY CY7C1353B 51-85050-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 119-Lead PBGA ( 2.4 mm) BG119 CY7C1353B 51-85115-*A Page ...
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... Document Title: CY7C1353B 256Kx18 Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05266 Issue REV. ECN NO. Date ** 114137 03/18/02 Document #: 38-05266 Rev. ** PRELIMINARY Orig. of Change DSG Change from Spec number: 38-00950 to 38-05266 CY7C1353B Description of Change Page ...