DSP56311 Freescale Semiconductor, Inc, DSP56311 Datasheet

Page 1

... Figure 1). The DSP56311 performs 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. © ...

Page 2

... Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications DSP56311 Technical Data, Rev. 8 pin is active when RESET Voltage Freescale Semiconductor ...

Page 3

... Features Table 1 lists the features of the DSP56311 device. Feature • 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O • Object code compatible with the DSP56000 core with highly parallel instruction set • ...

Page 4

... IP telephony Product Documentation The documents listed in Table 2 are required for a complete description of the DSP56311 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website ...

Page 5

... Signals/Connections The DSP56311 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1. Power ( Ground (GND) Clock PLL Address bus ...

Page 6

... Interface (SCI) Port SCLK TIO0 3 Timers TIO1 TIO2 TCK TDI OnCE/ TDO JTAG Port TMS TRST DE Signals Identified by Functional Group DSP56311 Technical Data, Rev. 8 After Reset IRQA IRQB IRQC IRQD RESET Multiplexed Port B Bus GPIO HAD[0–7] PB[0–7] HAS/HAS PB8 HA8 ...

Page 7

... Reset External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an external clock. Crystal Output—Connects the internal crystal oscillator output to an external crystal external clock is used, leave XTAL unconnected. DSP56311 Technical Data, Rev. 8 Signal Description Power 1-3 ...

Page 8

... Input Input PINIT Input Input NMI Input 1.5 External Memory Expansion Port (Port A) Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri- states the relevant Port A signals: 1.5.1 External Address Bus State During Signal Name Type A[0–17] ...

Page 9

... Transfer Acknowledge—If the DSP56311 is the bus master and there is no external bus activity, or the DSP56311 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states ( .infinity) can be added to the wait states inserted by the bus control register (BCR) by keeping TA deasserted ...

Page 10

... Bus Request—Asserted when the DSP requests bus mastership deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independently of whether the DSP56311 is a bus master or a bus slave. Bus “parking” allows deasserted even though the DSP56311 is the bus master. ...

Page 11

... When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after powerup. DSP56311 Technical Data, Rev. 8 Interrupt and Mode Control Signal Description 1-7 ...

Page 12

... HI function is selected, these signals are lines 0–7 of the bidirectional multiplexed Address/Data bus. Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Signal Description Freescale Semiconductor ...

Page 13

... Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HRD) after reset. Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Host Interface (HI08) Signal Description 1-9 ...

Page 14

... Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. DSP56311 Technical Data, Rev. 8 Signal Description Freescale Semiconductor ...

Page 15

... Receive Shift Register. SRD0 is an input when data is received. Port C 4—The default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SRD0 through the Port C Control Register. DSP56311 Technical Data, Rev. 8 Signal Description 1-11 ...

Page 16

... Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register. DSP56311 Technical Data, Rev. 8 Signal Description Signal Description Freescale Semiconductor ...

Page 17

... Port E 1—The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal TXD through the Port E Control Register. DSP56311 Technical Data, Rev. 8 Serial Communication Interface (SCI) Signal Description Signal Description ...

Page 18

... The Wait processing state does not affect the signal state. 1.11 Timers The DSP56311 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56311 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events ...

Page 19

... JTAG and OnCE Interface The DSP56300 family and in particular the DSP56311 support circuit-board test strategies based on the IEEE® Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals ...

Page 20

... Signals/Connections 1-16 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 21

... Specifications The DSP56311 is fabricated in high-density CMOS with transistor-transistor logic (TTL) compatible inputs and outputs. 2.1 Maximum Ratings This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if ...

Page 22

... SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 2-2 Table 2-2. Thermal Characteristics 1,2 1,3 1,3 1 DSP56311 Technical Data, Rev. 8 MAP-BGA Symbol Unit Value ° C/W θJA ° C/W θ ...

Page 23

... V ± 0 –40°C to +100 ° the high V value may cause additional power consumption (DC current). To minimize ILX should be no lower than IHX should be no higher than 0.1 × V ILX CCQH DSP56311 Technical Data, Rev Electrical Characteristics 7 Min Typ Max 1.7 1.8 1.9 3.0 3.3 3.6 2.0 — ...

Page 24

... IH Table 2-2. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal’s transition. DSP56311 output levels are measured with the production test machine V Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed ...

Page 25

... External Clock Operation The DSP56311 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1 . EXTAL XTAL R C XTAL1 C Fundamental Frequency Crystal Oscillator If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by setting XTLD (PCTL Register bit 16 = 1— ...

Page 26

... PLL capacitor (connected between the PCAP pin and V PCAP listed above. 2-6 Table 2-5. Clock Operation Characteristics Table 2-6. PLL Characteristics 1 ) PCAP DSP56311 Technical Data, Rev. 8 150 MHz Symbol Min Max Ef 0 150 157.0 µ 157.0 µ 273.1 µ ...

Page 27

... Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing 3 5 (WS + 3.75) × T (WS + 3.25) × T (WS + 3.5) × T (WS + 3.5) × × T (WS + 2.5) × T PLC × ET PLC × ET DSP56311 Technical Data, Rev Electrical Characteristics 6 150 MHz Expression Min Max — — 26.0 Minimum: 50 × ET 333.3 — ...

Page 28

... T is not constant, and their width may vary, so timing may vary 1.8 V ± 0 –40°C to +100° pF DSP56311 Technical Data, Rev (Continued) 150 MHz Expression Min Max Minimum: × PDF + (128K − 13.6 — C PLC/2) × × ...

Page 29

... Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI Freescale Semiconductor 9 8 Reset Value Figure 2-3. Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General-Purpose I/O Figure 2-4. External Fast Interrupt Timing DSP56311 Technical Data, Rev Electrical Characteristics First Fetch 2-9 ...

Page 30

... Operating Mode Select Timing 24 25 Recovery from Stop State Using IRQA 26 25 Recovery from Stop State Using IRQA Interrupt Service DSP56311 Technical Data, Rev IRQA, IRQB, IRQC, IRQD, NMI V IL First Instruction Fetch First IRQA Interrupt ...

Page 31

... [WS ≥ 2] 1.25 × ≤ WS ≤ 7] 2.25 × T [WS ≥ 8] 0.25 × T — [2 ≤ WS ≤ 3] –0.25 × T [WS ≥ 4] DSP56311 Technical Data, Rev Electrical Characteristics 150 MHz 1 Unit Min Max − 4.0 22 − 4.0 69.3 — – 3.0 2.0 — ...

Page 32

... T 1.75 × T — 2.75 × T — — (WS + 0.25) × T — 1.25 × T — 2.25 × 0.25 × T — — to 0.5 × CCQH CCQH DSP56311 Technical Data, Rev. 8 150 MHz 1 Min Max 1.25 × T — 8 ≤ WS ≤ 7] 2.25 × T — 15.0 C [WS ≥ 8] − 4.0 11.0 — ≤ WS ≤ 7] − ...

Page 33

... Freescale Semiconductor 100 113 116 105 104 Figure 2-10. SRAM Read Access 100 107 101 102 114 108 Figure 2-11. SRAM Write Access DSP56311 Technical Data, Rev Electrical Characteristics 117 106 118 119 Data In 103 119 118 109 Data Out 2-13 ...

Page 34

... Wait states 3 Wait states 2 Wait states 4 Wait states DRAM Page Mode Wait State Selection Guide DRAM Page Mode Timings, Three Wait States Symbol CAC t AA DSP56311 Technical Data, Rev. 8 Chip frequency (MHz) 120 1,2,3 100 MHz 4 Expression Min Max 4 × T 40.0 — ...

Page 35

... The number of wait states for Page mode access is specified in the DRAM Control Register. 2. The refresh period is specified in the DRAM Control Register. 3. The asynchronous delays specified in the expressions are valid for the DSP56311. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example for read-after-read or write-after-write sequences) ...

Page 36

... The number of wait states for Page mode access is specified in the DRAM Control Register. 2. The refresh period is specified in the DRAM Control Register. 3. The asynchronous delays specified in the expressions are valid for the DSP56311. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example × T for read-after-read or write-after-write sequences) ...

Page 37

... Column Column Address Address 143 132 133 153 154 Data In Data In DRAM Page Mode Read Accesses DSP56311 Technical Data, Rev Electrical Characteristics 136 135 138 142 Last Column Address 147 148 156 Data Out 136 135 138 ...

Page 38

... RAC t CAC OFF RAS t RSH t CSH t CAS t RCD t RAD t CRP ASR DSP56311 Technical Data, Rev. 8 Chip Frequency (MHz) 1,2 100 MHz 3 Expression Unit Min Max 12 × T 120.0 — 6.25 × T − 7.0 — 55 3.75 × T − 7.0 — 30 4.5 × T − 7.0 — ...

Page 39

... WP 11.75 × RWL 10.25 × CWL DHR t WCS t CSR t RPC t ROH DSP56311 Technical Data, Rev Electrical Characteristics 1,2 (Continued) 100 MHz 3 Expression Unit Min Max 1.75 × T − 4.0 13.5 — 0.75 × T − 4.0 3.5 — 5.25 × T − 4.0 48.5 — ...

Page 40

... WCR t WP 15.75 × RWL 14.25 × CWL DHR t WCS t CSR t RPC t ROH DSP56311 Technical Data, Rev. 8 1,2 100 MHz 3 Expression Unit Min Max 16 × T 160.0 — 8.25 × T − 5.7 — 76 4.75 × T − 5.7 — 41 5.5 × T − 5.7 — ...

Page 41

... Row Address Column Address 172 176 177 191 160 159 158 192 DRAM Out-of-Page Read Access DSP56311 Technical Data, Rev Electrical Characteristics 162 164 174 179 178 193 161 Data In 2-21 ...

Page 42

... DRAM Out-of-Page Write Access 157 162 163 190 170 165 189 177 Figure 2-18. DRAM Refresh Access DSP56311 Technical Data, Rev. 8 157 162 164 166 174 176 Column Address 175 180 186 195 Data Out 162 Freescale Semiconductor ...

Page 43

... Asynchronous Bus Timings 250 250+251 Asynchronous Bus Arbitration Timing , for some time after BB assertion to the time this assertion is exposed to other BB BG input active to another BG DSP56311 Technical Data, Rev Electrical Characteristics 150 MHz Expression Min Max 2.5 × — × 18.3 — ...

Page 44

... Delay from write data strobe deassertion to host request assertion for “Last Data Register” write 2-24 Table 2-14. Host Interface Timings 8,11 after “Last Data Register” reads , DSP56311 Technical Data, Rev. 8 1,2,12 150 MHz Expression Min Max T + 6.5 13.1 — C 6.5 — 2.5 × 4.4 20.8 — C 8.7 — 2.5 × 4.4 20.8 — C 10.9 — ...

Page 45

... Register” read or write (HROD=1, open drain host request) Notes: 1. See the Programmer’s Model section in the chapter on the HI08 in the DSP56311 User’s Manual . 2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. ...

Page 46

... HRW 317 HDS 328 332 327 326 H[7–0] 340 341 HA[2–0] 336 337 330 HCS 317 HRD 328 332 327 326 H[7–0] 340 341 DSP56311 Technical Data, Rev. 8 333 337 318 319 329 338 333 318 319 329 338 Freescale Semiconductor ...

Page 47

... Freescale Semiconductor HA[2–0] 336 337 331 HCS 336 HRW 320 HDS 324 H[7–0] 340 341 HA[2–0] 336 337 331 HCS 320 HWR 324 H[7–0] 340 341 DSP56311 Technical Data, Rev Electrical Characteristics 333 337 321 325 339 333 321 325 339 2-27 ...

Page 48

... Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 336 322 HAS 323 317 HRD 334 335 327 329 HAD[7–0] Address 326 340 341 DSP56311 Technical Data, Rev. 8 337 337 318 319 328 Data 338 337 318 319 328 Data 338 Freescale Semiconductor ...

Page 49

... Address Data 340 341 Write Timing Diagram, Multiplexed Bus, Single Data Strobe , 336 322 HAS 323 320 HWR 334 324 335 Data Address 340 341 DSP56311 Technical Data, Rev Electrical Characteristics 337 337 321 325 339 337 321 325 339 2-29 ...

Page 50

... ACC t ACC t ACC t ACC t ACC = 1.8 V ± 0 –40°C to +100 ° determined by the SCI clock control register and T SCC DSP56311 Technical Data, Rev. 8 150 MHz Min Max 8 × T 53.3 — − 10.0 16.7 — /2 − 10.0 16.7 — − 10.0 6.7 — − 0.5 × T 10.0 — ...

Page 51

... Data Valid a) Internal Clock 400 402 401 407 408 Data Valid 409 410 Data Valid b) External Clock SCI Synchronous Mode Timing 411 412 413 414 415 Data Valid SCI Asynchronous Mode Timing DSP56311 Technical Data, Rev Electrical Characteristics 2-31 ...

Page 52

... TXC rising edge to FST out (word-length-relative) low 450 TXC rising edge to FST out (word-length) high 2-32 Table 2-16. ESSI Timings 4, 6 Symbol Expression t SSICC 4 × × DSP56311 Technical Data, Rev. 8 150 MHz Cond- 5 ition Min Max 6 × T 40.0 — × T 53.4 — − 10.0 16.7 — ...

Page 53

... Freescale Semiconductor Table 2-16. ESSI Timings (Continued Symbol 1.8 V ± 0 –40°C to +100 ° pF DSP56311 Technical Data, Rev Electrical Characteristics 150 MHz Cond- Expression 5 ition Min Max — 31 — 17 — ...

Page 54

... Normal mode, the output flag state is asserted for the entire frame period. 2-34 430 432 446 447 450 454 454 452 First Bit 459 457 453 461 458 460 462 Figure 2-31. ESSI Transmitter Timing DSP56311 Technical Data, Rev. 8 451 455 Last Bit 456 461 See Note Freescale Semiconductor ...

Page 55

... Table 2-17. Timer Timing Expression 2 × 2 × 2 –40°C to +100 ° 480 481 TIO Timer Event Input Restrictions DSP56311 Technical Data, Rev Electrical Characteristics 438 440 Last Bit 443 445 150 MHz Unit Min Max 15.4 — ns 15.4 — ...

Page 56

... Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of the GPIO data register. 2-36 Table 2-18. GPIO Timing Expression Minimum: 6.75 × pF. L 492 493 Valid 494 Figure 2-34. GPIO Timing DSP56311 Technical Data, Rev. 8 100 MHz Unit Min Max — 8.5 ns 0.0 — ns 8.5 — ns 0.0 — ...

Page 57

... Freescale Semiconductor is not available). Table 2-19. JTAG Timing Characteristics × 3); maximum 22 MHz 1.8 V ± 0 –40°C to +100 ° pF DSP56311 Technical Data, Rev Electrical Characteristics -cycle instruction and that there are no e All frequencies Unit Min Max 0.0 22.0 MHz 45.0 — ...

Page 58

... Output Data Valid Boundary Scan (JTAG) Timing Diagram 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid Test Access Port Timing Diagram DSP56311 Technical Data, Rev. 8 502 V M 503 V IH 505 V IH 509 Freescale Semiconductor ...

Page 59

... TRST (Input) 2.4.12 OnCE Module TimIng No. Characteristics 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56311 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time = 3.3 V ± 0 1.8 V ± 0 Note: V CCQH CC DE ...

Page 60

... Specifications 2-40 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 61

... Packaging This section includes diagrams of the DSP56311 package pin-outs and tables showing how the signals described in Chapter 1 are allocated for the package. The DSP56311 is available in a 196-pin molded array plastic-ball grid array (MAP-BGA) package. Freescale Semiconductor DSP56311 Technical Data, Rev 3-1 ...

Page 62

... GND EXTAL CLKOUT CCP CCQH RESET CAS GND AA3 V P CCQL PCAP GND AA2 XTAL V P1 CCC DSP56311 MAP-BGA Package, Top View DSP56311 Technical Data, Rev D14 D11 D13 D10 D12 CCD GND ...

Page 63

... BCLK CLKOUT CCQH CCP CAS RESET BCLK V AA3 GND CCQL XTAL AA2 GND CCC P1 DSP56311 MAP-BGA Package, Bottom View DSP56311 Technical Data, Rev. 8 Package Description IRQB TDO TMS SC11 NC B IRQD TRST TDI SC12 SRD1 IRQC IRQA ...

Page 64

... C10 D12 C11 V CCD C12 D6 C13 D3 C14 D4 D1 PINIT/NMI D2 SC01 or PC1 GND D5 GND D6 GND D7 GND D8 GND DSP56311 Technical Data, Rev. 8 Ball Signal Name No. D9 GND D10 GND D11 GND D12 D1 D13 D2 D14 V CCD E1 STD0 or PC5 E2 V CCS E3 SRD0 or PC4 E4 GND E5 ...

Page 65

... HRRQ/HRRQ, or PB15 J2 HRW, HRD/HRD, or PB11 J3 HDS/HDS, HWR/HWR, or PB12 J4 GND J5 GND J6 GND J7 GND J8 GND J9 GND J10 GND J11 GND J12 A8 J13 A7 DSP56311 Technical Data, Rev. 8 Package Description Ball Signal Name No. J14 CCS K2 HREQ/HREQ, HTRQ/HTRQ, or PB14 K3 TIO2 K4 GND K5 GND K6 GND K7 GND K8 GND ...

Page 66

... CCQL 2 N10 BCLK N11 BR N12 V CCC N13 AA0/RAS0 N14 A0 and GND that support the PLL, other GND signals do not support individual P P1 DSP56311 Technical Data, Rev. 8 Ball Signal Name No H5, HAD5, or PB5 P3 H3, HAD3, or PB3 P4 H1, HAD1, or PB1 P5 PCAP P6 GND P1 ...

Page 67

... A9 D17 B8 D18 C8 D19 A8 D2 D13 D20 B7 D21 B6 D22 C6 D23 A6 D3 C13 D4 C14 D5 B13 D6 C12 D7 A13 D8 B12 DSP56311 Technical Data, Rev. 8 Package Description Ball Signal Name No. D9 A12 DE D3 EXTAL M8 GND D4 GND D5 GND D6 GND D7 GND D8 GND D9 GND D10 GND D11 GND E4 GND ...

Page 68

... GND L6 GND L7 GND L8 GND L9 GND L10 GND L11 GND N6 P GND DSP56311 Technical Data, Rev. 8 Ball Signal Name No HA0 M3 HA1 M1 HA10 L1 HA2 M2 HA8 M1 HA9 M2 HACK/HACK J1 HAD0 M5 HAD1 P4 HAD2 N4 HAD3 P3 HAD4 N3 HAD5 P2 HAD6 ...

Page 69

... N7 RD M12 RESET N5 RXD F1 SC00 F3 SC01 D2 SC02 C1 SC10 F2 SC11 A2 SC12 B2 SCK0 H3 SCK1 G1 SCLK G2 SRD0 E3 SRD1 B1 STD0 E1 DSP56311 Technical Data, Rev. 8 Package Description Ball Signal Name No. STD1 C2 TA P10 TCK C3 TDI B3 TDO A4 TIO0 L3 TIO1 L2 TIO2 K3 TMS A3 TRST B4 TXD G3 V H12 CCA V K12 ...

Page 70

... Packaging 3.2 MAP-BGA Package Mechanical Drawing Figure 3-3. DSP56311 Mechanical Information, 196-pin MAP-BGA Package 3-10 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 71

... Design Considerations This section describes various areas to consider when incorporating the DSP56311 device into a system design. 4.1 Thermal Design Considerations An estimate of the chip junction temperature Equation Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θ power dissipation in package ...

Page 72

... T – has been defined – CAUTION this high-impedance circuit. pin. and V CC DSP56311 Technical Data, Rev )/P . This value gives a better estimate pin on the DSP and from the V CC and V GND CC ...

Page 73

... Table 2-7), the device circuitry can RESET uninitialized state that may result in significant power consumption and heat-up. Designs should minimize this condition to the shortest possible duration. • Ensure that during power-up, and throughout the DSP56311 operation, V the V voltage level. CC • ...

Page 74

... MHz, this skew is between − 1.4 ns and +3.2 ns. 4-4 – × × × 3 5.48 mA max) value reflects the typical possible switching of the internal buses on best- ⁄ ⁄ ( MHz = I – – typF2 typF1 DSP56311 Technical Data, Rev value CCItyp and for a EXTAL CLKOUT Freescale Semiconductor ...

Page 75

... PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. Freescale Semiconductor DSP56311 Technical Data, Rev. 8 PLL Performance Issues and EXTAL CLKOUT ...

Page 76

... The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. 4-6 is 0.5 percent. If the rate of change of the frequency of EXTAL DSP56311 Technical Data, Rev For small MF (MF < 10) CLKOUT is slow EXTAL ...

Page 77

... Power Consumption Benchmark The following benchmark program evaluates DSP56311 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. ;************************************************************************** ;************************************************************************** ;* ;* CHECKS ...

Page 78

... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 dc $6C6657 dc $C2A544 dc $A3662D dc $A4E762 dc $84F0F3 A-2 ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 79

... XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 Freescale Semiconductor DSP56311 Technical Data, Rev. 8 A-3 ...

Page 80

... YDAT_END ;************************************************************************** ; ; EQUATES for DSP56311 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** A-4 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 81

... Host Command Interrupt Enable ; Host Flag 2 ; Host Flag 3 ; Host Receive Data Full ; Host Receive Data Empty ; Host Command Pending ; Host Flag 0 ; Host Flag 1 ; Host Port GPIO Enable ; Host Address 8 Enable ; Host Address 9 Enable ; Host Chip Select Enable DSP56311 Technical Data, Rev. 8 A-5 ...

Page 82

... Timer Interrupt Rate ; SCI Clock Polarity ; SCI Error Interrupt Enable (REIE) ; Transmitter Empty ; Transmit Data Register Empty ; Receive Data Register Full ; Idle Line Flag ; Overrun Error Flag ; Parity Error ; Framing Error Flag ; Received Bit 8 (R8) Address DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 83

... Word Length Control Mask (WL0-WL7) ; Select SC1 drive enable (SSC1) ; Serial Output Flag Mask ; Serial Output Flag 0 ; Serial Output Flag 1 ; Serial Control Direction Mask ; Serial Control 0 Direction ; Serial Control 1 Direction ; Serial Control 2 Direction ; Clock Source Direction DSP56311 Technical Data, Rev. 8 A-7 ...

Page 84

... Receive Data Register Full ; SSI Transmit Slot Bits Mask A (TS0-TS15) ; SSI Transmit Slot Bits Mask B (TS16-TS31) ; SSI Receive Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Bits Mask B (RS16-RS31) ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 85

... SSI1 Interrupt Priority Level (low) ; SSI1 Interrupt Priority Level (high) ; SCI Interrupt Priority Level Mask ; SCI Interrupt Priority Level (low) ; SCI Interrupt Priority Level (high) ; TIMER Interrupt Priority Level Mask ; TIMER Interrupt Priority Level (low) ; TIMER Interrupt Priority Level (high) DSP56311 Technical Data, Rev. 8 A-9 ...

Page 86

... Direction Bit ; Data Input ; Data Output ; Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag ; Prescaler Source Mask ; Timer Control 0 ; Timer Control 1 ; Timer Control 2 ; Timer Control 3 ; DMA Status Register ; DMA Offset Register 0 ; DMA Offset Register 1 DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 87

... DMA Destination Space Mask (DDS-DDS1) ; DMA Destination Memory Space 0 ; DMA Destination Memory Space 1 ; DMA Address Mode Mask (DAM5-DAM0) ; DMA Address Mode 0 ; DMA Address Mode 1 ; DMA Address Mode 2 ; DMA Address Mode 3 ; DMA Address Mode 4 ; DMA Address Mode 5 ; DMA Three Dimensional Mode DSP56311 Technical Data, Rev. 8 A-11 ...

Page 88

... EFCOP ALU Control Register ; EFCOP Data Base Address ; EFCOP Coefficient Base Address ; EFCOP Decimation/Channel Register ; PLL Control Register ; Division Factor Bits Mask (DF0-DF2) ; XTAL Range select bit ; XTAL Disable Bit ; STOP Processing State Bit ; PLL Enable Bit DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 89

... Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1) ; Address Attribute Pin Polarity ; Program Space Enable ; X Data Space Enable ; Y Data Space Enable ; Address Muxing ; Packing Enable ; Number of Address Bits to Compare Mask (BNC0-BNC3) ; Address to Compare Bits Mask (BAC0-BAC11) ; mask for CORE-DMA priority bits Carry ; Overflow DSP56311 Technical Data, Rev. 8 A-13 ...

Page 90

... Bus Release Timing ; Address Tracing Enable bit in OMR. ; Stack Extension space select bit in OMR. ; Extensed stack UNderflow flag in OMR. ; Extended stack OVerflow flag in OMR. ; Extended WRaP flag in OMR. ; Stack Extension Enable bit in OMR. ;leave user definition as is. DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 91

... ESSI0 Transmit last slot ; ESSI1 Receive Data ; ESSI1 Receive Data w/ exception Status ; ESSI1 Receive last slot ; ESSI1 Transmit data ; ESSI1 Transmit Data w/ exception Status ; ESSI1 Transmit last slot ; SCI Receive Data ; SCI Receive Data With Exception Status ; SCI Transmit Data DSP56311 Technical Data, Rev. 8 A-15 ...

Page 92

... INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF A-16 ; SCI Idle Line ; SCI Timer ; Host Receive Data Full ; Host Transmit Data Empty ; Default Host Command ; EFilter input buffer empty ; EFilter output buffer full ; last address of interrupt vector space DSP56311 Technical Data, Rev. 8 Freescale Semiconductor ...

Page 93

...

Page 94

...

Page 95

...

Page 96

... Tai Po Industrial Estate Tai Po, N.T. Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Order No.: DSP56311 Rev. 8 2/2005 Core Pin Frequency Solder Spheres Count (MHz) 196 150 ...