CY7C1325-100AC Cypress Semiconductor Corporation., CY7C1325-100AC Datasheet
CY7C1325-100AC
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CY7C1325-100AC Summary of contents
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... Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation 256K x 18 Synchronous Functional Description The CY7C1325 is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... 100-Lead TQFP CY7C1325 CY7C1325 DDQ DDQ BYTE0 DDQ V SS ...
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... Bidirectional Data Parity lines. These behave identical to DQ These signals can be used as parity bits for bytes 0 and 1 respectively. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 3 CY7C1325 are also loaded into the burst [1:0] are also loaded into the burst [1:0] ...
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... Maximum access delay from the clock rise ( 7.5 ns (117-MHz device). CDV The CY7C1325 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... The device must be deselected prior to entering the 01 “sleep” mode inactive for the duration of t LOW. 5 CY7C1325 Second Third Fourth Address Address Address ...
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... CY7C1325 ADV WE OE CLK L-H High L-H High L-H High L-H High L-H High ...
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... DD ZZ < 0.2V 2t CYC DC Input Voltage Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Ambient Range Temperature + 0.5V DD Com’l 0°C to +70°C 7 CY7C1325 BWE BWS BWS ...
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... Device Deselected – 0. 0.3V, IN DDQ inputs switching MAX, Max Device Deselected – 0. 0.3V inputs static Test Conditions T = 25° MHz 5. CY7C1325 7C1325 Min. Max. 2.4 2.0 0.4 0.7 2 0.3V 1 0.3V –0.3 0.8 –0.3 0 –30 5 –5 30 –5 5 –300 8 ...
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... OUTPUT 2. GND INCLUDING JIGAND [9] SCOPE 1325–3 (b) [10] -117 Min. Max. Min. 8.5 10 3.0 4.0 3.0 4.0 2.0 2.0 0.5 0.5 7.5 2.0 2.0 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3 [11, 13] 3.5 [11, 13 3.5 /I =–2/2 mA (min). CLZ 9 CY7C1325 ALL INPUT PULSES 90% 90% 10% 10% 2.5 ns 2.5 ns 1325–4 -100 -90 -50 Max. Min. Max. Min. Max. Unit 11 20 4.5 4.5 4.5 4.5 2.0 2.0 0.5 0.5 8.0 8.5 11.0 2.0 2.0 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3.5 3.5 3 3.5 3.5 3 3.5 3.5 3.5 ...
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... GW to define a write cycle (see Write Cycle Descriptions table). [1:0] 15. WDx stands for Write Data to Address X. Burst Write ADSP ignored with CE inactive masks ADSP UNDEFINED = DON’T CARE 10 CY7C1325 Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High-Z 3a ...
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... RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP DOH DON’T CARE = UNDEFINED 11 CY7C1325 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... C t ADH t ADVH t WES ADSP ignored with CE HIGH 1 t EOHZ Q(B) D(C) (B+2) (B+1) (B+3) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select CY7C1325 ADH t CEH t CEH t WEH Q(D) (C+1) (C+2) (C+3) t DOH t CHZ ...
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... RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data- stands for Data-out CYC ADH t CEH t WES ADSP ignored with CE HIGH 1 Q(D) and CE . All chip selects need to be active in order to select DON’T CARE = UNDEFINED 13 CY7C1325 WEH D (E) D (F) D (H) D (G) D(C) t DOH t CHZ ...
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... Timing Diagrams (continued) OE Switching Waveforms OE t EOHZ three-state I/Os t EOV t EOLZ 14 CY7C1325 ...
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... ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Notes: 17. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 18. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active CCZZ Three-state 15 CY7C1325 t ZZREC ...
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... Ordering Information Speed (MHz) Ordering Code 117 CY7C1325-117AC 100 CY7C1325-100AC 80 CY7C1325-80AC 50 CY7C1325-50AC Document #: 38-00652-B Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...