MC68HC000FN20 Freescale Semiconductor, Inc, MC68HC000FN20 Datasheet

Page 1

... Freescale Semiconductor, Inc. Applications Information Low Power on the SCM68000 (EC000 Core) The SCM68000 (EC000 core) has been redesigned to provide fully static and low power operation. This document describes the recommended method for placing the SCM68000 into a low-power mode to reduce the power consumption to its quiescent value mode described below will be routinely tested as part of the SCM68000 test vectors provided by Freescale ...

Page 2

... Freescale Semiconductor, Inc. ADDRESS_MATCH ASB ASB QB CLB RESTARTB RESETB Figure 2. Low-Power Circuitry for 8-bit data bus 2.) Execute the STOP instruction. The external circuitry shown in Figure 1 and Figure 2 will count the num- ber of bus cycles starting with the write to the low-power address and will stop the processor’s clock on the first falling edge of the system clock after the bus cycle that reads the immediate data of the STOP instruction ...

Page 3

... Freescale Semiconductor, Inc. CLK CPU_CLK ASB RWB DTACKB BRB BGB BGACKB Figure 4. Clock Stop Timing with Bus Arbitration for 16-bit Data Bus After the previous steps are completed, the SCM68000 will remain in the low-power mode until the appropriate interrupt is recognized. External logic will also have to poll IPLB2– ...

Page 4

... Freescale Semiconductor, Inc. 4.) If the SCM68000 was put into a three-state condition the BGACKB signal (used for 3-wire bus arbitra- tion) or the BRB signal (used for 2-wire bus arbitration) must be negated before the processor can begin executing instructions. An example trap routine follows: TRAP_x MOVE ...