CS4297A-JQ Cirrus Logic, Inc., CS4297A-JQ Datasheet
CS4297A-JQ
Specifications of CS4297A-JQ
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CS4297A-JQ Summary of contents
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... AC ’97 interface, implements a cost effective, superior quality, audio solution. The CS4297A surpasses PC 99 and AC ’97 2.1 audio quality standards. ORDERING INFO CS4297A-KQ 48-pin TQFP CS4297A-JQ 48-pin TQFP ANALOG INPUT MUX AND OUTPUT MIXER PCM_DATA GAIN / MUTE CONTROLS MIXER / MUX SELECTS PCM_DATA This document contains information for a new product ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 CS4297A ...
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... Figure 2. Codec Ready from Startup or Fault Condition ........................................................... 8 Figure 3. Clocks ........................................................................................................................ 8 Figure 4. Data Setup and Hold.................................................................................................. 9 Figure 5. PR4 Powerdown and Warm Reset ............................................................................ 9 Figure 6. Test Mode .................................................................................................................. 9 Figure 7. AC-link Connections ................................................................................................ 10 Figure 8. Mixer Diagram.......................................................................................................... 12 Figure 9. AC-link Input and Output Framing ........................................................................... 13 Figure 10. Line Input (Replicate for Video and Aux) ...............................................................35 ........................................................28 CS4297A 41 3 ...
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... Figure 17. Alternate Line Output as Headphone Output .........................................................37 Figure 18. Stereo Output.........................................................................................................37 Figure 19. Voltage Regulator ..................................................................................................38 Figure 20. S/PDIF Output........................................................................................................39 Figure 21. Conceptual Layout for the CS4297A......................................................................40 Figure 22. Pin Locations for the CS4297A ..............................................................................41 Figure 23. CS4297A Reference Design ..................................................................................48 LIST OF TABLES Table 1. Mixer Registers .........................................................................................................19 Table 2. Analog Mixer Output Attenuation ..............................................................................21 Table 3 ...
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... A-D 0.91 A-D 0.091 D-A 0.91 (Note 4) FR A-A 20 D A-A 90 A-A 85 D-A 85 A-D 85 SNR D-A - THD+N A-A - D-A - A (Note 4) - (Note (Note 4) - (Note 4) - 2.0 refers to the digital output pin loading. DL CS4297A ambient =100 kΩ/ AL CS4297A-JQ Typ Max Min Typ Max 1.00 - 0.91 1.00 - 1.00 - 0.91 1.00 - 0.10 - 0.091 0.10 - 1.0 1.13 0.91 1.0 1.13 - 20,000 20 - 20,000 - 20,000 20 - 20,000 - 20,000 20 - 20,000 ...
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... Supply Pins) (Power Applied) (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 (AVss = DVss = 0 V) Symbol Min 0.65 x DVdd ih V 0.90 x DVdd 0.99 x DVdd -10 -10 - (Note 4) - CS4297A Min Typ Max - 3.0 - Min Typ Max -0.3 - 6.0 -0.3 - 6.0 -0 ...
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... T clk_low F sync T sync_period T sync_high T sync_low isetup T ihold T irise T ifall (Note 4) T orise (Note 4) T ofall T s2_pdown T 1.0 sync_pr4 T 162.8 sync2clk setup2rst (Note 4) T off CS4297A = 25° C, ambient Typ Max Unit µ µs - 40.0 - µs - 62.5 - µ 12.288 - MHz - 81 750 40.7 45 ...
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... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY Figure 2. Codec Ready from Startup or Fault Condition BIT_CLK T orise SYNC T irise 8 T rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd clk_high clk_low clk_period T ifall T T sync_high sync_low T sync_period Figure 3. Clocks CS4297A T rst2clk T ifall ...
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... Slot 1 SDATA_OUT Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don’t Care T s2_pdown Figure 5. PR4 Powerdown and Warm Reset T setup2rst T off Figure 6. Test Mode CS4297A T ihold T T sync_pr4 sync2clk Hi-Z 9 ...
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... During each audio frame, data is passed bi-direc- tionally between the CS4297A and the controller. The input frame is driven from the CS4297A on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line. The con- troller is also responsible for issuing reset com- mands via the RESET# signal ...
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... Section 4, Register Inter- face. 2.3 Output Mixer The CS4297A has two output mixers, illustrated in Figure 8. The stereo output mixer sums together the analog inputs to the CS4297A, including the PC_BEEP and PHONE signals, according to the settings in the volume control registers. The stereo output mix is sent to the LINE_OUT and ALT_LINE_OUT pins on the CS4297A ...
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... ANALOG STEREO 3D OUTPUT OUTPUT MIXER MIXER STEREO TO MONO MIXER Σ 1/2 Σ STEREO TO MONO MIXER 1/2 Figure 8. Mixer Diagram CS4297A BYPASS BUFFER DAC DIRECT MASTER MODE VOLUME OUTPUT MUTE BUFFER ALT LINE VOLUME OUTPUT MUTE BUFFER MONO OUT MONO SELECT ...
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... On the next rising edge of BIT_CLK, the first bit of Slot 0 is driven by the controller on the SDATA_OUT pin. On the next falling edge of BIT_CLK, the CS4297A latches this data in, as the first bit of the frame. 20.8 µ s (48 kHz) ...
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... AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4297A from the AC ’97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4297A is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’ ...
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... See Figure 9 for bit frame positions. RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the CS4297A. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’ to access CS4297A registers. 3.1.3 Command Data Port (Slot 2) ...
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... AC-Link Audio Input Frame In the serial data input frame, data is passed on the SDATA_IN pin from the CS4297A to the AC ’97 con- troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus- trates the serial port timing. ...
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... ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Reg- ister (Index 5Eh). The definition of each slot can be found in Table 7 on page 29 CS4297A Reserved ...
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... SYNC assertion. 18 Upon loss of synchronization with the controller, the CS4297A will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4297A will ignore all register reads and writes and will discontinue the transmission of PCM cap- ture data ...
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... Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Table 1. Mixer Registers CS4297A Default 0 0 ID4 MR5 MR4 MR3 MR2 MR1 MR0 0 MR5 MR4 MR3 MR2 MR1 MR0 0 MM5 MM4 MM3 MM2 MM1 MM0 ...
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... The data in this register is read-only data. Any write to this register causes a Register Reset to the default state of the audio (Index 00h - 38h) and vendor spe- cific (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4297A. 4.2 Master Volume Register (Index 02h) ...
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... Level 000000 000000 0 dB 000001 000001 -1.5 dB … … ... 011111 011111 -46.5 dB 100000 011111 -46.5 dB ... ... ... 111111 011111 -46.5 dB Table 2. Analog Mixer Output Attenuation D10 CS4297A MR5 MR4 MR3 MR2 MR1 MM5 MM4 MM3 MM2 MM1 D0 MR0 D0 MM0 21 ...
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... The total range is + -34.5 dB gain. See Table 4 on page 24 for further details. Default 8008h. This value corresponds gain and Mute ‘set’. 22 D10 D10 CS4297A PV3 PV2 PV1 PV0 GN4 GN3 GN2 GN1 ...
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... This value corresponds gain and Mute ‘set’. D10 20dB Gain Level GN[4:0] 20dB = 0 20dB = 1 00000 +12.0 dB +32.0 dB 00001 +10.5 dB +30.5 dB … … ... 00111 +1.5 dB +21.5 dB 01000 0.0 dB +20.0 dB 01001 -1.5 dB +18.5 dB … … ... 11111 -34.5 dB -14.5 dB Table 3. Microphone Input Gain Values CS4297A GN4 GN3 GN2 GN1 D0 GN0 23 ...
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... Table 4. Analog Mixer Input Gain Values Register Index Function 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume Table 5. Stereo Volume Register Index CS4297A GR4 GR3 GR2 GR1 D0 GR0 ...
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... Video Input 011 Aux Input 100 Line Input 101 Stereo Mix 110 Mono Mix 111 Phone Input Table 6. Input Mux Selection D10 GL2 GL1 GL0 0 0 CS4297A SR2 SR1 GR3 GR2 GR1 D0 ...
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... General Purpose Register (Index 20h). Default 0000h. This value corresponds to minimum spatial enhancement added to the output signal. 26 D10 MIX MS LPBK 0 D10 CS4297A stereo enhancement. This ...
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... The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular section of the CS4297A is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the powerdown functions ...
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... ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4297A is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4297A is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins. AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link slot to audio DAC mapping is supported ...
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... Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is ‘set’, the CS4297A will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4297A expects to sample SYNC ‘ ...
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... When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4297A. The Fs bit is merely an indicator to the S/PDIF receiver. L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘ ...
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... Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ character. DID[2:0] Device ID. With a value of DID[2:0] = 001, these bits specify the audio codec is a CS4297A. REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’. ...
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... This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 7. Once deasserted, all of the CS4297A registers will be reset to their default power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. 32 5.1.2 Warm AC ’ ...
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... The PR[6:0] bits in this register control the internal powerdown states of the CS4297A. Power- down control is available for individual subsections of the CS4297A by asserting any PRx bit or any combination of PRx bits. Most powerdown states can be resumed by clearing the corresponding PRx bit. Table 10 shows the mapping of the power con- trol bits to the functions they manage. When PR0 is ‘ ...
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... Table 11. Powerdown PR Function Matrix I (mA) I DVdd DVdd [DVdd=3.3 V] [DVdd 30.1 24.5 21.0 22.1 22.1 18.9 19.3 11 µA 27 µA 24.5 11 µA 27 µ DVdd/Rload/2 DVdd CS4297A Analog AC Internal Link Clock Off • • • • • (mA) I (mA) AVdd 49.4 37.9 43.4 37.9 38.1 29.0 39.6 31.3 39.9 10.7 45 µA 34.8 35.5 37.9 45 µA 43.4 36.2 450 µA ...
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... N165: CS4297A/CS4299 EMI Reduction Techniques [5]. 6.1 Analog Inputs All analog inputs to the CS4297A, including CD_GND, should be capacitively coupled to the input pins. Unused analog inputs should be tied to- gether and connected through a capacitor to analog ground or tied to the Vrefout pin directly. The max- ...
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... The design also sup- ports the recommended advanced frequency re- sponse for voice recognition as specified in PC 99. Note the microphone input to the CS4297A has an integrated pre-amplifier. Using the 20dB bit in the Microphone Volume Register (Index 0Eh) the pre-amplifier gain can be set dB. ...
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... Figure 16 shows a design for a modem connection where the output is fed from the CS4297A MONO_OUT pin through a divider. The divider ratio shown does not attenuate the signal, providing an output voltage output voltage is desired, the resistors can be re- placed with appropriate values, as long as the total load on the output is kept greater than 10 kΩ ...
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... The analog power pins, AVdd1 and AVdd2, supply power to all the analog circuitry on the CS4297A. The +5 V analog supply should be generated from a linear voltage regulator (7805 type) connected to a +12 V supply. This helps iso- late the analog circuitry from noise typically found digital supplies ...
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... CS4297A ground potential and de- grading performance. The digital ground pins should be connected to the digital ground plane and kept separate from the analog ground connections of the CS4297A and any other external analog cir- R S/PDIF_OUT 1 SPDO/SDO2 DVdd 3 ...
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... AFLT2 REFFLT AVdd2 Via to Analog Ground Digital Ground Via to Digital Ground Pin 1 0.1 µF DVss1 Y5V 0.1 µF DVss2 Y5V Figure 21. Conceptual Layout for the CS4297A CS4297A Via to +5VA 1 µF 0.1 µF Y5V AVss1 AVdd1 Via to Analog Ground Analog Ground DVdd2 Via to +5VD or +3.3VD ...
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... DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP Figure 22. Pin Locations for the CS4297A CS4297A LINE_OUT_R 36 LINE_OUT_L 35 FLTO 34 FLTI 33 FLT3D 32 BPCFG 31 AFLT2 30 AFLT1 29 Vrefout 28 REFFLT ...
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... AC-coupled, with separate AC-coupling caps, to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4297A intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry ...
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... VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4297A intended to be used for the audio signal output of a video device. The maximum allowable input internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate AC-coupling caps, to analog ground ...
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... Analog Reference, Filters, and Configuration REFFLT - Internal Reference Voltage, Input, Pin 27 This signal is the voltage reference used internal to the CS4297A. A 0.1 µF and a 1.0 µF (must not be larger than 1 µF) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin. ...
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... Power Supplies DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9 Digital supply voltage for the AC-link section of the CS4297A. These pins can be tied digital or to +3.3 V digital. The CS4297A and controller AC-link should share a common digital supply DVss1, DVss2 - Digital Ground, Pins 4 and 7 Digital ground connection for the AC-link section of the CS4297A ...
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... Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4297A. DAC Refers to a single Digital-to-Analog converter in the CS4297A. “DACs” refers to the stereo pair of Digital-to-Analog converters. The CS4297A DACs have 20-bit resolution defined as dB relative to full-scale. The “ ...
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... SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4297A operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level ...
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... REFERENCE DESIGN DVdd2 9 DVdd1 1 GND AVdd2 AVdd1 AVss2 AVss1 XTL_OUT XTL_IN FLTO FLTI CS4297A ...
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... Version 6.0, February 1998 3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.0, February 1998 4) Cirrus Logic, AN134: AES and S/PDIF Recommended Transformers, Version 2, April 1999 5) Cirrus Logic, AN165: CS4297A/CS4299 EMI Reduction Techniques, Version 1.0, September 1999 ® 6) Intel , Audio Codec ’97 Component Specification, Revision 2.1, May 1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm ® ...
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... Controlling dimension is mm. JEDEC Designation: MS022 ∝ L INCHES NOM MAX 0.055 0.063 0.004 0.006 0.009 0.011 0.354 0.366 0.28 0.280 0.354 0.366 0.28 0.280 0.020 0.024 0.24 0.030 4° 7.000° CS4297A A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 0.40 0.50 BSC 0.60 0.45 0.60 0.00° ...
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Notes • ...
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