CS89712-CB Cirrus Logic, Inc., CS89712-CB Datasheet
CS89712-CB
Related parts for CS89712-CB
CS89712-CB Summary of contents
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... ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operat- ing systems like embedded Linux. The CS89712 Ethernet port includes on-chip RAM and 10BASE-T transmit and receive filters. ORDERING INFO CS89712-CB 10BASE-T ETHERNET PLL INTERNAL DATA BUS ARM720T 32 ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS89712 DS502PP2 ...
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... Pin Diagram .................................................................................................. 142 5.2 256-Ball PBGA Ball Listing ............................................................................................. 143 5.3 External Signal Functions 5.4 Output Bi-Directional Pins ............................................................................................... 151 5.5 256 PBGA Package Dimensions .................................................................................... 153 6. ELECTRICAL/THERMAL INFO ........................................................................................... 154 6.1 Absolute Maximum Ratings ............................................................................................ 154 6.2 DC Characteristics .......................................................................................................... 154 6.3 AC Characteristics .......................................................................................................... 157 6.4 I/O Buffer Strength & Characteristics .............................................................................. 169 7. ORDERING INFORMATION ................................................................................................ 170 DS502PP2 .......................................................................................... 147 CS89712 3 ...
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... LEDDRV PHDIN CS[n] RxD1/2 WORD TxD1/2 ADCCLK CS[2] ADCCS CS[3] ADCOUT ADCIN SMPCLK RXD- EXTL1 RXD+ TXD- EXTL2 TXD+ Figure 1. A CS89712–Based System CS89712 CL1 LCD MODULE CL2 FM M KEYBOARD POWER SUPPLY UNIT AND POR COMPARATORS RUN DC-TO-DC CONVERTERS CODEC/SSI2/ DAI IR LED AND PHOTODIODE ...
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... Operating at 74 MHz, the CS89712 delivers about 2.1 MIPS sustained (74 MIPS peak). The CS89712 contains the following features: • ARM720T processor with: - ARM7TDMI CPU core (supporting the Thumb instruction set and with enhanced multiplier) running at a dynamic clock ...
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... Commercial 0 - 70C operating temperature. The CS89712 design is optimized for low power dissipation and is fabricated on a fully static 0.25 micron CMOS process available in a 256-ball PBGA package. A maximum configured system using the CS89712 ...
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... RUN signal is driven low, therefore this signal can be used externally in the system to power down other system modules. Whenever the CS89712 is in the Standby State, the external address and data buses are forced low in- ternally by the RUN signal. This is done to prevent peripherals that are powered down from draining ...
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... Also, the internal peripheral’s signals get set to their Reset State. When first powered, or reset by the nPOR (Power On Reset, active low) signal, the CS89712 is forced into the Standby State. This is known as a cold re- set, and when leaving the Standby State after a cold reset, external wake up is the only way to wake up the device ...
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... BATOK. From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock run- ning, the CS89712 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point ...
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... CS89712: nPOR (Power On Reset), nPWRFL, and nURESET. If any of these are active, a system reset is generated internally. This will reset all internal registers in the CS89712 except the RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be preserved DD through a user reset or power fail condition ...
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... CS89712 leaving it in the Standby State. The nSTBY and RUN signals are high when the CS89712 is in the Operating or Idle States and low when in the Standby State. The main system clock is valid when nSTBY is high. The nSTBY signal will disable any peripheral block that is clocked from the master clock source (i ...
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... Ethernet port after each reset (except EEPROM reset). The CS89712 Ethernet operates with any of six standard EEPROMs shown in Ethernet Port Register Register Descriptions Address Contents 0020h 0300h I/O Base Address 0022h XXXX XXXX Interrupt Number XXXX X100 0102h ...
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... Table 5. EEPROM Configuration Block Example words, and a checksum value. All words in the Re- set Configuration Block are read sequentially by the Ethernet port after each reset, starting with the header and ending with the checksum. Each group of configuration data is used to program an Ether- CS89712 Description 13 ...
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... Reset Configuration Block. (The EE- PROM address of the checksum value can be deter- mined by dividing the value stored in the Link Byte by two.) The checksum value is the 2’s comple- ment of the 8-bit sum (any carry out of eighth bit is CS89712 Figure 3 for DS502PP2 ...
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... A) is set. EEPROMOK is First Word of a Group of Words Number of Words 9-bit PacketPage Address in Group Figure 3. Group Header CS89712 Determining EEPROM Size Loading Configuration Data Table EEPROM Read-out Completion 2 ...
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... The crystal frequency drift should be less than 100 ppm over the operating temperature range. Alternatively, a digital clock source can be used to drive the MOSCIN pin of the CS89712. With this approach, the voltage levels of the clock source should match that of the V CS89712’s pads (i.e. the supply voltage level used to drive all of the non-V CS89712) ...
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... Lowest Undefined Instruction, Software Interrupt Table 6. Exception Priority Handling The CS89712 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt re- quest (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. Of these, seventeen are mapped to the IRQ input and five sources are mapped to the FIQ input ...
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... All other interrupt sources (i.e., exter- nal interrupt source) must be held active until its re- spective service routine starts executing. See Section 3.13, “End Of Interrupt Locations” for more details. Table 7, Table 8, and Table 9 allocation of interrupts in the CS89712. CS89712 show the names and DS502PP2 ...
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... Synchronous serial interface 1 end of transfer interrupt Name KBDINT Key press interrupt SS2RX Master / slave SSI 16 bytes received SS2TX Master / slave SSI 16 bytes transmitted UTXINT2 UART2 transmit FIFO empty interrupt URXINT2 UART2 receive FIFO full interrupt Name 0 DAIINT DAI interface interrupt CS89712 Comment Comment Comment 19 ...
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... If the FASTWAKE bit is set, then there will be a latency of between 250 sec to 500 sec. Whenever the CS89712 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low ...
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... Selection of the Boot ROM option is determined by the state of the nMEDCHG pin during a power on reset. If nMEDCHG is high while nPOR is active, then the CS89712 will boot from an external mem- ory device connected to CS[0] (normal boot mode). If nMEDCHG is low, then the boot will be from the on-chip ROM ...
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... Table 12. CS89712 Memory Map in External Boot Mode 22 MMU should be programmed to generate an abort exception for access to this area. Chip Select CS[7] Internal peripherals are addressed through a set of (Internal only) internal registers from address 0x8000.0000 to CS[6] 0x8000 ...
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... Memory and I/O Expansion Interface Six separate linear memory or expansion segments are decoded by the CS89712, two of which can be reserved for two PC Cards, each interfacing to a separate single CL-PS6700 device. Each segment is 256 Mbytes in size. Two additional segments (in addition to these six) are dedicated to the on-chip SRAM and ROM ...
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... SDRAMs. Smaller devices may only have one bank, so BA1 may not be needed. Arrangement of SDRAMs 8 Mbytes 16 Mbytes CS89712 USDQM is connected to 32 Mbytes 64 Mbytes ...
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... Table 15. SDRAM Configurations (SDRAM 16-Bit Memory Interface) DS502PP2 Arrangement of SDRAMs 4 Mbytes 8 Mbytes CS89712 Mbytes 32 Mbytes 64 Mbytes ...
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... SYSCON2). For efficient, low power operation, both address and data are carried on the lower 16 bits of the CS89712 data bus. Accesses are initiated by a write or read from the area of memory allocat- ed for nCS4 or nCS5. The memory map within ...
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... The CS89712 can ac- cess the registers in the CL-PS6700, regardless of the state of the PRDY signal. If the CS89712 needs to access the PC CARD via the CL-PS6700, it waits until the PRDY signal is high before initiat- ing a transfer request ...
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... If DMA is enabled within the CL-PS6700, it will assert its PDREQ signal to make a DMA request. This can be connected to one of the CS89712’s external interrupts and be used to interrupt the CPU for servicing the DMA request. Each of the CL-PS6700 devices can generate an in- terrupt PIRQ ...
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... The big-endian / little-endian bit in the ARM720T control register sets whether the CS89712 treats words in memory as being stored in big endian or little endian format. Memory is viewed as a linear collection of bytes numbered up- wards from zero. Bytes hold the first stored word, bytes the second, and so on ...
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... The additional RI input, and RTS and DTR output modem control lines are not explicitly supported but can be implemented using GPIO ports in the CS89712. UART2 has only the RX and TX pins. UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control). ...
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... SSIRXFR SSIRXFR = RX frame sync; Input DS502PP2 2.17 Synchronous Serial Interfaces The CS89712 has the synchronous serial interfaces shown in (DAI, CODEC, and SSI2) pins are multiplexed to- gether. On power up, both the DAISEL and SER- SEL register bits are low, enabling the master / slave SSI2 to these pins (and configuring it for slave mode operation to avoid external contention) ...
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... Codec Sound Interface The codec interface allows direct connection of a telephony type codec to the CS89712. It provides all the necessary clocks and timing pulses. It also performs a parallel to serial conversion or vice ver the data stream to or from the external codec device. The interface is full duplex and contains two separate data FIFOs (16 deep by 8-bits, one for the receive data, another for the transmit data) ...
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... Digital audio data is transferred, full duplex, via separate transmit and receive data lines. The bit clock frequency is programmable to Figure 6. Portion of the CS89712 Block Diagram Showing Multiplexed Feature DS502PP2 128 fs. The sample frequency (fs) is now programmable from 8-48Khz using either the on- chip PLL (73 ...
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... DAIEN[16] (H) I2SF64[0] (L) DAIEN[16] (H) I2SF64[0] (H) DAIEN[16] (L) DAIEN[16] (L) Clock Source Sample (MHz) Frequency (KHz) 73.728 8 11.2896 11.025 73.728 16 11.2896 22.025 73.728 24 73.728 32 11.2896 44.1 73.728 48 CS89712 SYSCON2 (X) (X) (X) SERSEL[0] (L) (X) SERSEL[0] (H) 128 fs Divisor 64 fs Divisor (AUDDIV) (AUDDIV ...
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... SDATAI - MSB Figure 8. CS89712 - Digital Audio Interface Timing – MSB / Left Justified format frame synchronization. Each transition of LRCK delineates the left and right halves of an audio sam- ple. When LRCK transitions from high-to-low the next 16 bits make up the right side of a sample. ...
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... In the default mode, the device is compatible with the MAXIM MAX148/9 in external clock mode. Similar SPI- or Microwire-compatible devices can connect directly to the CS89712. • In the extended mode and with negative-edge triggering selected (the ADCCON and ADC- CKNSEN bits are set, respectively, in the SYSCON3 register), this device can be inter- faced to Analog Devices’ ...
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... Hence, there will be a delay before the new value programmed to the enable bits can be read back. The timing diagram for this interface can be found in Section 6.3. Master 7211 Slave 7211 SSIRXFR SSIRXFR SSITXFR SSITXFR SSICLK SSICLK SSITXDA SSIRXDA SSIRXDA SSITXDA CS89712 Figure 9. 37 ...
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... RX and TX frame sync control lines (SSITXFR and SSIRXFR). Hence, the RX path may bear a greater data throughput than the TX path, or vice versa. Residual bit valid 00 New RX byte received New RX byte received 01 Figure 10. Residual Byte Reading CS89712 11 Pop FIFO DS502PP2 ...
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... To dis- able the clock, the TX section is turned off. In Master mode, the CS89712 does not support the discontinuous clock. 2.17.4.5 Error Conditions RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2 register ...
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... On exit from Snooze State, the CS89712 enters the Doze State. In Doze State, all of the CS89712, ex- cept the LCD controller, is operating normally. The DRAM is taken out of self-refresh and normal CAS before RAS (CBR) refreshes start ...
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... Timer Counters Two identical timer counters are integrated into the CS89712. These are referred to as TC1 and TC2. Each timer counter has an associated 16-bit read / write data register and some control bits in the sys- 8 bits/byte) / (640 x tem control register ...
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... This mode can be used to produce a pro- grammable frequency to drive the buzzer (i.e., with TC1) or generate a periodic interrupt. The formula is F=(500 kHz) / (n+1). 2.20 Real-Time Clock The CS89712 contains a 32-bit Real-Time Clock (RTC). This can be written to and read from in the Pixel 1 Pixel 2 Pixel 3 Pixel 4 Gray scale Gray scale ...
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... The voltage for the crystal must be 2 0.2 V. DS502PP2 Alternatively, a digital clock source can be used to drive the RTCIN pin of the CS89712. With this ap- proach, the voltage levels of the clock source should match that of the V CS89712’s pads (i.e., the supply voltage level used ...
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... Ethernet port’s internal memory. The Ethernet port then checks the CRC, and depending on the configuration, informs the processor that a frame has been received. In the second phase, the receive frame is transferred into host memory. CS89712 DS502PP2 ...
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... AD7 - AD0 used with ’C56 ELSEL OP1 OP0 AD7 AD6 Description Figure 12. EEPROM Command Register Format CS89712 ’CS56, ’C66 and ’CS66 AD5 AD4 AD3 AD2 AD1 AD0 AD5 - AD0 used with ’C46 and ’CS46 45 ...
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... HCB0 bit (SelfCTL register, Bit E) is set. To configure it for software control, the HC0E bit must be set. HC0E HCB0 (Bit C) (Bit Table 27. LINKLED/HC0 Pin Operation CS89712 Execution EEPROM Type Time all 25 µs all 10 ms all 10 ms ‘CS46, ‘C46 9 µ ...
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... V when the pin is low. 2.26 Media Access Control Engine 2.26.1 Overview The CS89712’s Ethernet Media Access Control (MAC) engine is fully compliant with the IEEE 802.3 Ethernet standard (ISO/IEC 8802-3, 1993). It handles all aspects of Ethernet frame transmission ...
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... If a frame is received with a bad CRC, the CRCer- ror bit (RxEvent register, Bit C) is set. If the CRCerrorA bit (RxCTL register, Bit C) is set, the frame will be buffered by Ethernet port. If the CRCerroriE bit (RxCFG register. Bit C) is set, an interrupt is generated. CS89712 DS502PP2 ...
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... IPG being shortened due to a temporary loss of carrier. grams the two-part deferral process. 2.26.5.3 Simple Deferral In the simple deferral scheme, the IPG timer is started whenever Carrier Sense is deasserted. Once the IPG timer is finished (after 9.6 µs transmit CS89712 Figure 14 dia- 49 ...
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... If a collision is detected while the Ethernet port is transmitting, the MAC responds in one of three ways depending on whether normal collision (within the first 512 bits of transmission late collision (after the first 512 bits of transmission): CS89712 Start Monitoring Network Activity Yes Network ...
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... Ethernet standard algorithm (ISO/IEC 8802-3, 1993). Its primary functions in- clude: Manchester encoding of transmit data; in- forming the MAC when valid receive data is present (Carrier Detection); and, recovering the clock and NRZ data from incoming Manchester- encoded data. CS89712 3, where n is the 51 ...
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... Ethernet port directly to a simple isolation transformer (see the Characteristics/Specifications section for a con- nection diagram). Figure 17 gram of the 10BASE-T transceiver. 2.28.1 10BASE-T Filters The CS89712’s 10BASE-T transceiver includes in- tegrated low-pass transmit and receive filters, elim- ENDEC RXSQL Carrier Detector RX ...
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... Link Pulse Generator. 10BASE-T Transceiver Link Pulse RX Squelch Detector RX RX Comparator TX TX Pre- TX Filters Distortion Filter Tuning Figure 17. 10BASE-T Transceiver Packet Less Than 16ms Figure 18. Link Pulse Transmission CS89712 Figure 18 RXD- RX Filters RXD+ TXD- TX Drivers TXD+ Link Link Pulse Pulse 16ms 16ms diagrams 53 ...
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... The CS89712 supports an Extended Range feature that reduces the 10BASE-T receive squelch thresh- old by approximately 6 dB. This allows the CS89712 to operate with 10BASE-T cables that are longer than 100 meters (100 meters is the maxi- mum length specified by the Ethernet standard). The exact additional distance depends on the qual- ity of the cable and the amount of electromagnetic noise in the surrounding environment ...
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... Basic Receive Operation Receive operations occur in the following order (in this example, interrupts are enabled to signal the presence of a valid receive frame frame is received by the CS89712, triggering an enabled interrupt. DS502PP2 2) The software reads the Interrupt Status Queue Port and is informed of the receive frame. ...
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... Section 3.17 for more details. An event triggers an interrupt only when the En- ableIRQ bit (17) of the Bus Control register is set. After the CS89712 has generated an interrupt, the first read of the ISQ makes the INTRQ output pin go low (inactive). INTRQ remains low until the null word (0000h) is read from the ISQ, or for 1 ...
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... Which Event report BufEvent type? RxMISS TxCOL None of the above Figure 19. Interrupt Status Queue CS89712 Process applicable RxEvent bits: Extradata, Runt, CRCerror, RxOK. Process applicable TxEvent bits: 16coll, Jabber, Out-of-window, TxOK. Process applicable BufEvent bits: RxDest, Rx128, RxMiss, TxUnderrun, Rdy4Tx, RxDMAFrame, SWint ...
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... The Rx128 bit is cleared by the software reading the BufEvent register (either directly or through the Interrupt Status Queue the CS89712 detecting the incoming frame’s End-of-Frame (EOF) se- quence. Like all Event bits, RxDest and Rx128 are set by the whenever the appropriate event occurs ...
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... BufEvent reg- ister, either directly or through the ISQ. When the CS89712 commits buffer space to a par- ticular held receive frame (termed a committed re- ceived frame), no data from subsequent frames can be written to that buffer space until the frame is freed from commitment ...
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... CPU to reading this counter, and using the count to read the frame out of the Ethernet port at the same time it is being received by the CS89712 from the Ethernet (parallel frame-recep- tion and frame-read-out tasks). Following an RxDest or Rx128 interrupt the regis- ter contains the number of bytes which are avail- able to be read by the CPU ...
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... Multicast frames under a very specific set of conditions. 2.33.3 Broadcast Frames Frames with DA equal to FFFF.FFFF.FFFFh are broadcast frames. In addition, the CS89712 can be configured for Promiscuous Mode, in which case it will accept all receive frames, irrespective of DA. 2.33.4 Destination Address Filter The DA filter is configured by five DA filter bits in the RxCTL register: IAHashA, PromiscuousA, MulticastA, IndividualA, and BroadcastA ...
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... Broadcast Error Runt CRC Broadcast Error Runt CRC Broadcast Error MulticastA IndividualA BroadcastA Table 29. Destination Address Filtering Options CS89712 Bit 9 Bit 8 Hashed RxOK 1 1 Individual 0 1 Adr Individual 0 0 Adr 1 1 Individual 0 1 Adr Individual 0 0 Adr ...
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... Ethernet frame is moved into the Ethernet port’s buffer memory. This phase begins with the software issuing a Transmit Command. This informs the CS89712 that a frame transmitted and tells the chip when (i.e. after 5, 381, or 1021 bytes have been transferred or after the full frame has been transferred to the CS89712) and how the frame should be sent (i ...
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... Address, Source Address, Length field and LLC data). If the frame is less than 64 bytes, including CRC, the CS89712 adds pad bits if configured to do so. Finally, the CS89712 appends the proper 32-bit CRC value. 2.34.2 Transmit Configuration After each reset, the Ethernet port must be config- ured for transmit operation ...
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... If set, the frame can be written. If clear, the soft- ware must continue reading the BusST register and checking Rdy4TxNOW until set. When the CS89712 is ready to accept the frame, software transfers the frame from host RAM to Ethernet port memory Receive/Transmit Data Port. 2.34.7 Transmit in Interrupt Mode In interrupt mode, Rdy4TxiE bit (BufCFG register bit 8) must be set for transmit operation ...
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... Send without pads and without CRC Notes the TxPadDis bit is clear and InhibitCRC is set and the CS89712 is commanded to send a frame of length less than 60 bytes, the CS89712 pads. 2. The CS89712 will not send a frame with TxLength less than 3 bytes There is a transmit under-run while the Tx- Underrun bit (BufEvent register bit 9) is set ...
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... Link Pulse) bursts instead of the original IEEE 802.3 NLP (Normal Link Pulses). If the hub is attempting to auto-negotiate with the CS89712, the CS89712 will never get more than 1 DS502PP2 "valid" link pulse (valid NLP). This is not a prob- lem if the CS89712 is already sending link-pulses, ...
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... Non-Ethernet Registers Table 31 shows the internal non-Ethernet registers of the CS89712 when the CPU is configured to a little endian memory system. differences that occur when the CPU is configured to a big endian memory system for byte-wide ac- cess to Ports A, B, and D. All the internal registers are inherently little endian (i ...
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... PALLSW 0x8000.0580 PALMSW 0x8000.05C0 STFCLR 0x8000.0600 BLEOI 0x8000.0640 MCEOI 0x8000.0680 TEOI 0x8000.06C0 TC1EOI 0x8000.0700 TC2EOI 0x8000.0740 RTCEOI Table 31. CS89712 Internal Registers (Little Endian Mode) DS502PP2 Default RD/WR Size Port A data register Port B data register. — 8 Reserved Port D data register. ...
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... DAIDR2 0x8000.2100 DAISR 0x8000.2200 SYSCON3 0x8000.2240 INTSR3 0x8000.2280 INTMR3 0x8000.22C0 LEDFLSH Table 31. CS89712 Internal Registers (Little Endian Mode) (Continued) Big Endian Mode Name 0x8000.0003 PADR Table 32. CS89712 Internal Registers (Big Endian Mode) 70 Default RD/WR Size — WR — Write to clear UART modem status changed inter- rupt. — ...
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... PDDDR 0x8000.0083 PEDR 0X8000.00C3 PEDDR Table 32. CS89712 Internal Registers (Big Endian Mode) 1. The following register descriptions refer to Little Endian Mode Only. 3.2 Accessing Ethernet Port Registers Registers for the Ethernet port are accessed through two memory ranges; first, a 16-byte window of eight 16-bit registers (shown in at address 0x2000.0300 ...
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... Ethernet Port Pointer. 3.2.1.6 The Ethernet Port Data Ports are used to transfer data to and from any of the CS89712’s internal reg- isters. Port 0 is used for 16-bit operations and Port 0 and 1 are used for 32-bit operations (lower-order word in Port 0). ...
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... Ethernet Status/Control Registers The Status and Control registers are the primary registers used to control and check the status of the Ethernet port in the CS89712. They are organized into two groups: Configuration/Control Registers and Status/Event Registers. All Status and Control Registers are 16-bit words as shown in ...
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... Status and Event Registers Status and Event registers report the status of trans- mitted and received frames, as well as information about the configuration of the CS89712. They are read-only. The Interrupt Status Queue (ISQ special type of Status/Event register located at Ethernet Port offset address 0120h and is the first register the software reads when responding to an Interrupt ...
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... Rdy4Tx (BufEvent) Table 35. Interrupt Enable Bits and Events Accept bits indicate which types of frames will be accepted by the CS89712. Four of these bits have corresponding Interrupt Enable (iE) bits. An Ac- cept bit and an Interrupt Enable bit are independent operations possible to set either, neither, or both bits ...
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... Ethernet Port Locations”). The Accept 76 mechanism is explained in more detail in Section 2.32, “Basic Receive Operation”. 3.2.7 Status/Control Register Summary This section gives a detailed description of each Status and Control register. Bits marked “RSVD” are reserved and must be written with a zero for proper operation of the device. CS89712 DS502PP2 ...
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... Ethernet Port 4 Kbyte Memory Register Map The following Table shows the CS89712 Ethernet Port internal register map: Internal # of Offset Bytes Type Bus Interface Registers 0000h 4 0004h 28 0022h 2 RW 0038h 8 0040h 2 RW 0042h 2 RW 0044h 12 0050h 2 RD 0052h 174 Status and Control Registers ...
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... Reserved Logical Address Filter (hash table) Individual Address - Reserved RXStatus (receive status) in bytes) CS89712 Cross Reference Note 2 Section 3.19, “Initiate Transmit Registers” , Section 2.34, “Transmit Operation” Section 3.19, “Initiate Transmit Registers” , Section 2.34, “Transmit Operation” Note 2 Section 3.20, “Address Filter Registers” , Section 2.32.7, “ ...
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... The system control register is a 21-bit read / write register which controls all the general configuration of the CS89712, as well as modes etc. for peripheral devices. All bits in this register are cleared by a system reset. The bits in the system control register SYSCON1 are defined in ...
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... Column 3 only driven high all others high impedance Column 4 only driven high all others high impedance Column 5 only driven high all others high impedance Column 6 only driven high all others high impedance Column 7 only driven high all others high impedance Table 37. SYSCON1 CS89712 DS502PP2 ...
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... Note: Even though a keypress will not wake the device, a keypress interrupt will still be generated, if the keyboard interrupt is not masked, and this can be used to wake the device. DS502PP2 Description ADC Sample Frequency (kHz) — SMPCLK 8 32 128 256 Table 37. SYSCON1 (Continued) CS89712 ADC Clock Frequency (kHz) — ADCCLK 128 81 ...
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... Description sec regardless of the selected bit rate). Setting this bit will use Table 37. SYSCON1 (Continued) CS89712 DS502PP2 ...
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... SS2RXEN PC CARD2 PC CARD1 This is an extension of SYSCON1, containing additional control for the CS89712. The bits of this second system control register are defined below. The SYSCON2 register is reset to all 0s on power up. Bit 0 SERSEL:The only affect of this bit is to select either SSI2 or the codec to interface to the external pins ...
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... FBADDR register) then this can be achieved by writ- ing the LCDSNZE bit, which will cause the CL-CS89712 to start fetching DMA data from the main buffer and sync up the display at the end of the following frame. The LCDSNZE bit can never be programmed the CPU — ...
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... VERSN[0] Reserved Reserved Reserved This register allows additional control for the CS89712. The bits of this register are defined in Bit 0 ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16 used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO(7:0) only is used for compatibility with the CL-PS7111 ...
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... PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the nPWRFL input pin cleared by writing to the STFCLR location. 15 CLDFLG: Cold start flag. This bit will be set if the CS89712 has been reset with a power on reset cleared by writing to the STFCLR location. 86 ...
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... Port E[0:1] during power on reset, as shown in the table below. PE[1] (BOOTBIT1 ID: Will always read ‘1’ for the CS89712 device. 30:31 VERID: Version ID bits. These 2 bits determine the version id for the CS89712. Will read ‘10’ for the initial version. DS502PP2 Description PE[0] Boot option (BOOTBIT0) 0 32-bit 1 ...
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... SS2TXFF: Master / slave SSI2 TX FIFO full bit. This will be set if the FIFO is full. This will get cleared when data is removed from the FIFO or the CS89712 is reset. 5 SS2TXUF: Master / slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to trans- mit when TX FIFO is empty ...
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... URXINT1 7 6 EINT3 EINT2 The interrupt status register is a 32-bit read only register. The interrupt status register reflects the current state of the first 16 interrupt sources within the CS89712. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in Table 42. Bit 0 EXTFIQ: External fast interrupt ...
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... This interrupt mask register is a 32-bit read / write register, which is used to selectively enable any of the first 16 interrupt sources within the CS89712. The four shaded interrupts all generate a fast interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual address 0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will cause a jump to processor virtual address 0000 ...
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... URXINT2 This register is an extension of INTSR1, containing status bits for backward compatibility with CL-PS7111. The in- terrupt status register also reflects the current state of the new interrupt sources within the CS89712. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in ...
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... INTSR3 Interrupt Status Register 3 (address 0x8000.2240) 7:1 Reserved This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of the CS89712. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in Bit 0 DAIINT: DAI interface interrupt. The cause must be determined by reading the DAI status regis- ter ...
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... SYSFLG1 register. All bits in the memory configuration register are cleared by a system reset, and the state of the BOOTBIT bits are determined by Port E bits 0 and 1 on the CS89712 during power-on reset. The state of PE[1] and PE[0] determine whether the CS89712 is going to boot from either 32-bit-wide, 16-bit-wide or 8- bit-wide ROMs ...
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... Table 47. Values of the Wait State Field at 36 MHz Description Table 48. MEMCFG CS89712 No. of Wait States Sequential Wait States Wait States Random Sequential ...
Page 95
... The flash rate is determined by the LEDFLSH[1:0] bits, in the following way: LEDFLSH[5:2] 0000 0001 0010 DS502PP2 5:2 Duty ratio LEDFLSH[1:0] Flash Period (sec Table 49. LED Flash Rates Duty Ratio LEDFLSH[5:2] (time on: time off) 01:15 1000 02:14 1001 03:13 1010 Table 50. LED Duty Ratio CS89712 1:0 Flash rate Duty Ratio (time on: time off) 09:07 10:06 11:05 95 ...
Page 96
... The width of each SDRAM. ‘00’=>4bits, ‘01’=>8bits, ‘10’=>16 bits, ‘11’=>32 bits. 9. Control over the SDRAM clock. ‘0’=> SDRAM clock is permanently enabled except when in standby mode. ‘1’=>SDRAM clock stops when the CS89712 is put into inactive mode i.e., SDACTIVE = ‘0’, or when in standby mode. 10. ...
Page 97
... An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz master clock. Note: The CS89712 monitors the power supply input pins (i.e., BATOK and NEXTPWR) to determine which of the above fields to use. 8:11 Drive 1 pump ratio: This 4-bit field controls the “ ...
Page 98
... The overrun error bit is not associated with any single character and so is not stored in the FIFO. If this bit is set, the entire contents of the FIFO is invalid and should be cleared. This error bit is cleared by reading the UARTDR register PARERR FRMERR Description Table 53. UARTDR1-2 UART1-2 CS89712 7:0 RX data DS502PP2 ...
Page 99
... FIFOEN: Set to enable FIFO buffering of RX and TX data. Clear to disable the FIFO (i.e., set its depth to one byte). DS502PP2 FIFOEN XSTOP EVENPRT Description Bit Rate Running From the PLL Clock — 115200 76800 57600 38400 19200 14400 9600 2400 1200 110 CS89712 13 12 11:0 PRTEN BREAK Bit rate divisor 99 ...
Page 100
... LCD Line length = (640 / 16) – 0x27 hex. The minimum value that can be programmed into this register (i.e not a legal value). 100 Description Word Length 5 bits 6 bits 7 bits 8 bits Table 54. UBRLCR1-2 UART1-2 (Continued) 24:19 18:13 Pixel prescale Line length Description Table 55. LCDCON CS89712 12:0 Video buffer size DS502PP2 ...
Page 101
... Pixel rate (MHz) = 36.864 / (Pixel prescale + 1) The pixel prescale value can be expressed in terms of the LCD size by the formula: When the CS89712 is operating @ 18.432 MHz: Pixel prescale = (36864000 / (Refresh Rate x Total pixels in display)) – 1 Refresh Rate is the screen refresh frequency ( avoid flicker) The value should be rounded down to the nearest whole number and zero is illegal and will result in no pixel clock ...
Page 102
... Pixels Lit 0 0% 1/9 11.1% 1/5 20.0% 4/15 26.7% 3/9 33.3% 2/5 40.0% 4/9 44.4% 1/2 50.0% 1/2 50.0% 5/9 55.6% 3/5 60.0% 6/9 66.7% 11/15 73.3% 4/5 80.0% 8/9 88.9% 1 100% Table 56. Grayscale Value to Color Mapping CS89712 11:8 7:4 Grayscale Grayscale Grayscale value for pixel value for pixel value for pixel value 2 value 1 value 0 11:8 7:4 Grayscale Grayscale Grayscale value for pixel value for pixel value for pixel value 10 value 9 value 8 % Step Change 11.1% 8.9% 6.7% 6.6% 6.7% 5.4% 5.6% 0.0% 5.6% 5.4% 6 ...
Page 103
... ADC. When the ADCCON control bit in the SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the ADC Configuration Extension field for sending to the ADC. DS502PP2 13 12:8 SMCKEN Frame length 13 12:7 SMCKEN Frame length Description Table 57. SYNCIO CS89712 7:0 ADC Configuration Byte 6:0 ADC Configuration Length 103 ...
Page 104
... RTCEOI RTC Match End of Interrupt (address 0x8000.0740) A write to this location will clear the RTC match interrupt 3.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt (address 0x8000.0780) A write to this location will clear the modem status changed interrupt. 104 Description Table 57. SYNCIO (Continued) CS89712 DS502PP2 ...
Page 105
... Notes: 1. Before entering the Standby State, the LCD Controller should be disabled. The LCD controller should be enabled on exit from the Standby State the CS89712 is attempting to get into the Snooze/Standby State when there is a pending interrupt request, it will not enter into the low power mode. The instruction will get executed, but the processor will ignore the command ...
Page 106
... FIFO service requests. Each of these status condi- tions signal an interrupt request to the interrupt controller. The status register also flags when the transmit FIFOs are not full when the receive FIFOs are not empty. 106 CS89712 DS502PP2 ...
Page 107
... Right Channel Receive FIFO half-full or more condition does not generate an interrupt (RCRS bit ignored). 1 — Right Channel Receive FIFO half-full or more condition generates an interrupt (state of RCRS sent to interrupt controller). 23 Reserved 24-31 Reserved DS502PP2 RCTM LCRM LCTM Reserved Description Table 58. DAI Control Register CS89712 15-0 ECS DAIEN Reserved 107 ...
Page 108
... When RCTM = 1, the interrupt is enabled and whenever RCTS is set (one) an interrupt request is made to the interrupt controller. Note that programming RCTM = 0 does not affect the current state of RCTS or the Right Channel Transmit FIFO logic’s ability to set and clear RCTS, for it only blocks the generation of the interrupt request. 108 CS89712 DS502PP2 ...
Page 109
... RIGHT CHANNEL DATA: Transmit / Receive Right Channel FIFO Data Read — Bottom of Right Channel Receive FIFO data Write — Top of Right Channel Transmit FIFO data DS502PP2 15-0 Bottom of Right Channel Receive FIFO Read Access 15-0 Top of Right Channel Transmit FIFO Write Access Description CS89712 109 ...
Page 110
... After writing a value to this register, wait until the 110 Description Table 59. DAI Data Register 0 (Continued) Bottom of Left Channel Receive FIFO Read Access Top of Left Channel Transmit FIFO Write Access Description Table 60. DAI Data Register 1 20-16 15 FIFO Channel Select FIFOEN CS89712 15-0 15-0 14-0 Reserved DS502PP2 ...
Page 111
... Right Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI oper- ation is enabled, interrupt request signaled if not masked (if RCTM = 1) Table 62. DS502PP2 Description Table 61. DAI Data Register LCNE LCNF 4 3 LCTURCTU LCRS Description DAI Control, Data and Status Register Locations CS89712 RCNE RCNF RCCELCRO LCTS LCRSRCRS LCTSRCTS 111 ...
Page 112
... Right Channel Receive FIFO is empty 1 — Right Channel Receive FIFO is not empty 10 LCNF: LCNETelecom Transmit FIFO Not Full (read-only) 0 — Left Channel Transmit FIFO is full 1 — Left Channel Transmit FIFO is not full DAI Table 62. 112 Description Control, Data and Status Register Locations (Continued) CS89712 DS502PP2 ...
Page 113
... Left Channel Receive FIFO interrupt request mask (LCRM) bit is cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the ser- DS502PP2 Description Control, Data and Status Register Locations (Continued) CS89712 113 ...
Page 114
... I/O to fill the Left Channel Transmit FIFO. This bit does not request an interrupt. 3.16.6.12 Left Channel Receive FIFO Not Empty Flag (LCNE) This is a read-only bit set when the Left Channel Receive FIFO contains one or more entries of valid 114 CS89712 DS502PP2 ...
Page 115
... FIFO is automatically cleared when DAIDR2 is read or written. This bit does not request an interrupt. 3.16.7 DAI64Fs Control (address 0x8000.2600) The DAI now includes a divider network for the frequency of the clock source. The CS89712 provides for both 128 and 64 times the sample frequency (128 fs and 64 fs) to better support the various MP3 sample rates ...
Page 116
... ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers: 116 F:B A Reserved Reserved Description Table 65. EEPROM Command Bits Least significant byte of the EEPROM data. Least significant byte of the byte count. 5:0 RegNum CS89712 Address 0022h Interrupt number assignment: 0000 0000b = Enable 0000 01xxb = Disable 9 8 OB1 OB0 Table 26. Address 0042h ...
Page 117
... The operation of this bit is independent of the received packet integrity (good or bad CRC). After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM” ...
Page 118
... RxStatus is not cleared when RxEvent is read. See Section 2.32, “Basic Receive Operation” . The value in the RxEvent register is undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set. 118 5:0 F 000100 A 9 Individual Adr Hashed F:A Hash Table Index (see Section 2.32.7, “Receive Ethernet Port Locations” ) Description Table 68. Receiver Event CS89712 E D Extradata Runt 8 RxOK 9 8 Hashed = 1 RxOK = 1 DS502PP2 ...
Page 119
... When clear, frames longer than 1518 bytes are discarded. See Note 1. After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.32.7, “Receive Ethernet Port Locations” ...
Page 120
... RSVD: Reserved. must be a “0” when writing to this register. After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM” ...
Page 121
... RSVD 001000 TxEvent gives the event status of the last packet transmitted. Bit 5:0 001000: These bits provide an internal address used by the CS89712 to identify this as register 8, the Transmitter Event Register. 7:6 RSVD: Reserved. must be a “0” when writing to this register. 8 TxOK: This bit is set if the last packet was completely transmitted (Jabber (Bit A), out-of-win- dow-collision (Bit 9), and 16Coll (Bit F) must all be clear) ...
Page 122
... If InhibitCRC is clear, the CS89712 appends the CRC. If InhibitCRC is set, the CS89712 does not append the CRC After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM” ...
Page 123
... BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from RxDest to Rx128. After reset EEPROM is found by the CS89712, then the register has the following initial state after reset EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EEPROM” ...
Page 124
... Rdy4TxiE (Register B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 2.34, “Transmit Operation” for a description of the transmit bid process.) 9 TxUnderrun: This bit is set if CS89712 runs out of data before it reaches the end of the frame (called a transmit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt. ...
Page 125
... RxMISS actually overflows). The RxMISS counter is cleared when read. Bit 5:0 010000: These bits provide an internal address used by the CS89712 to identify this as register 10, the Receiver Miss Counter. When reading this register, these bits will be 010000, where the LSB corresponds to Bit 0. ...
Page 126
... TxCOL actually overflows). The TxCOL counter is cleared when read. Bit 5:0 010010: These bits provide an internal address used by the CS89712 to identify this as register 12, the Transmit Collision Counter. When reading this register, these bits will be 010010, where the LSB corresponds to Bit 0. ...
Page 127
... RSVD: Reserved; must be a “0” when writing to this register. After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM” ...
Page 128
... PolarityOK LineST reports the status of the Ethernet physical interface. Bit 5:0 010100: These bits provide an internal address used by the CS89712 to identify this as register 14, the Line Status Register. When reading this register, these bits will be 010100, where the LSB corresponds to Bit 0. 7 LinkOK: If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the CS89712 has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms ...
Page 129
... HCB1 is clear, HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this control bit is ignored. After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM” ...
Page 130
... Self Status Register. When reading this register, these bits will be 010110, where the LSB corresponds to Bit 0. 6 3,3VActive: If the CS89712 is operating on a 3.3 V supply, this bit is set. If the CS89712 is operating supply, this bit is clear. 7 INITD: If set, the CS89712 initialization, including read-in of the EEPROM, is complete. ...
Page 131
... Interrupts & Status Queue” ). When cleared, the CS89712 will not generate any interrupts. After reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM” ...
Page 132
... B BusST describes the status of the current transmit operation. Bit 5:0 011000: These bits provide an internal address used by the CS89712 to identify this as register 18, the Bus Status Register. When reading this register, these bits will be 011000, where the LSB corresponds to Bit 0. 7 TxBidErr: If set, the software has commanded the Ethernet port to transmit a frame that the Ethernet port will not send ...
Page 133
... RSVD: Reserved; must be a “0” when writing to this register. At reset EEPROM is found by the CS89712, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EEPROM” . ...
Page 134
... CS89712 does not transmit a frame if TxLength is less than 3. See Section 2.34, “Transmit Operation” . Bit 001001: These bits provide an internal address used to identify this as register 9. When read- ing this register, these bits will be 001001, where the LSB corresponds to Bit 0. TxStart: This pair of bits determines how many bytes are transferred to the CS89712 before the MAC starts the packet transmit process ...
Page 135
... The value of this register must be loaded from external storage, for example, from the EEPROM. See Section 2.24, “Programming the EEPROM” the CS89712 is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. ...
Page 136
... This test mode will enable the main oscillator and will output various buffered clock and test signals derived from the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the CS89712 will be static and isolated from the oscillators, with the ex- ception of the 6-bit ripple counter used to generate 576 kHz and the Real-Time Clock divide chain ...
Page 137
... This mode selected by nTEST0 = 0, nTEST1 = 0, Latched nURESET = 0. This test mode asynchronously disables all output buffers on the CS89712. This has the effect of re- moving the CS89712 from the PCB so that other devices on the PCB can be in-circuit tested. The in- ternal state of the CS89712 is not altered directly by this test mode ...
Page 138
... Loopback/Collision Diagnostic Tests Internal and external Loopback and Collision tests can be used to verify the CS89712’s Ethernet port functionality. Internal tests allow the major digital functions to be tested, independent of the analog functions. During these tests, the Manchester en- coder is connected to the decoder. All digital cir- cuits are operational, and the transmitter and receiver are disabled ...
Page 139
... This behavior can be emulated in software via the ICEBreaker control registers. A more detailed description is available in the ARM Software Development Toolkit User Guide and Reference Manual. The ICEBreaker module and its registers are fully described in the “ARM7TDMI” Data Sheet. CS89712 139 ...
Page 140
... COL COL SMP CLK D Vss D COL Vss A D BUZ COL I TCLK COL CS89712 EECS EE Vss DD SD DOUT I/O 3 CS0 EESK EE N/C DD SDQM DIN 2 3 N/C Vdd CL DD SDQM 2 I N/C Vdd FRM DD SD ...
Page 141
... ROM address lines. Whenever the CS89712 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripher- als that are powered-down from draining current. Also, the internal peripheral’ ...
Page 142
... DAI external clock input M8 O Serial clock output N6 O Chip select for ADC interface T6 O Serial data output R5 I Serial data input N7 O Sample clock output Table 90. External Signal Functions (Continued) CS89712 Description has settled. During normal operation, nPOR Table 91. DS502PP2 ...
Page 143
... Port E I/O (3 bits only). Can be used as general purpose I/O during normal operation. M5 I/O During power-on reset, PE[0] and PE[1] are inputs and are latched by the rising edge of nPOR to select the memory width that the CS89712 will use to read from the boot code storage device (i.e., external 8-bit- wide FLASH bank). J8 I/O During power-on reset, PE[2] is latched by the rising edge of nPOR to enable the PLL clocking mode ...
Page 144
... Drain Output- When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low output is low when the CS89712 detects the presence of valid link pulses. When the HC0E bit is set, the software may drive this pin low by setting the HCBO in the Self Control register. ...
Page 145
... Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be when active. DD[3:0] DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules. Note: Output pins above are bi-directional to enable monitored output to provide accurate control of timing or duration DS502PP2 Table 91. Output Bi-Directional Pins CS89712 145 ...
Page 146
... D1 Pin 1 Indicator TOP VIEW D 17.00 (0.669) 1.00 (0.040 0.50 BOTTOM VIEW R JEDEC #: MO-151 CS89712 0.85 (0.034) ±0.05 (.002) 0.40 (0.016) ±0.05 (.002) 30° TYP 4 Layer 0.56 (0.022) ±0.09 (0.004) 2 Layer 0.36 (0.014) ±0.09 (0.004) SIDE VIEW Pin 1 Corner ...
Page 147
... Symbol Min Typ VIH 1.7 VIL -0.3 VT- 0.8 Vhst 0.1 VOH V – DD 0.2 2.5 2.5 VOL (Note 1) IIN IOZ 25 µ When the pin is driven, there will be no leakage. A. CS89712 0 Max Unit Conditions 2 DDC 0 3.3 V DDIO 0 2.5 V DDC V = 3.3 V DDIO 1.2 V (Typ) 0.4 ...
Page 148
... Min Typ CIN 8 COUT 8 CI/O 8 IDD startup IDD standby TBD IDD TBD snooze TBD IDD idle CS89712 Max Unit Conditions 10.0 pF 10.0 pF 10.0 pF TBD µA Initial 100 ms from power up, Cache disabled, 32 kHz oscilla- tor not stable, POR signal at VIL, all other I/O static, VIH = V ± ...
Page 149
... Standby supply voltage Notes: 4. Power dissipation values can be derived by multiplying the IDD current by 2.5 V Core/OSC or 3.3V I/O. 5. The RTC of the CS89712 should be brought up at room temperature. The RTC OSC will NOT function properly brought up at –40 C. Once operational, it will continue to operate down to – ...
Page 150
... SSITXFR and / or SSIRXFR period Note: All SDRAM 36 MHz timings are for SDRAM operation. The values for 36 MHz include 1 wait state, the 18 MHz values have 0 wait states. 150 = 0 volts over an operating temperature +70 C. The timing SS . Symbol CS89712 18/36 MHz Units Min Max ...
Page 151
... EXBST t TBD - TBD RC t TBD - TBD RAC t TBD - TBD RP t TBD - TBD CAS t TBD - TBD CP t TBD - TBD PC t TBD - TBD CSR t TBD - TBD RAS CS89712 36 MHz Units Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 151 ...
Page 152
... When the CS89712 device implements consecutive reads(e.g., use of the LDM instruction), regardless of the state of the SQAEN bit, the signals nMOE and nCSx will always remain low through the entire multi-read access. They will not toggle in-between each different address access. In order to have these signals toggle, single access read instructions (e ...
Page 153
... ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. Figure 25. Sequential Page Mode Read Cycles with Minimum Wait States DS502PP2 0 t1 tEXRD t3 Data CS89712 tEXBST tEXBST Data in Data in ...
Page 154
... Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. Figure 26. Consecutive Memory Write Cycles with Minimum Wait States 154 tnCSWR Write data t6 t5 CS89712 tADWR Write data DS502PP2 ...
Page 155
... For CAS latency 3, there will be an extra cycle between T4 and T5. Figure 27. SDRAM Read Cycles CAS Latency = 2 DS502PP2 dev CAS lat 2 NOP READ NOP NOP NOP NOP tRCD tRAS auto precharge tRC DI0 DI2 DI1 bank col CS89712 T10 NOP NOP NOP (ACT) tRP DI3 155 ...
Page 156
... dev 1 dev NOP ACT NOP WRITE NOP NOP tRCD tRAS DO0 DO1 DO2 bank bank row row col Figure 29. SDRAM Write Cycles CS89712 T10 T11 NOP NOP NOP NOP NOP (ACT) tRP auto precharge DI1 DI2 DI3 NOP ...
Page 157
... CL[2] low time is doubled during the CL[1] high pulse DS502PP2 T0 T1 CLK CKE all nCS NOP REF NOP tRP auto precharge DQ A10 addr Figure 30. SDRAM Refresh Cycles t20 t17 t18 t21 t19 t22 t23 Figure 31. LCD Controller Timings CS89712 NOP NOP (ACT) tRC1 t15 t16 157 ...
Page 158
... ADCCLK (SCLK) nADCCS (nRFS/TFS) ADCIN DI9 DI8 DI7 (Din) ADCOUT (Dout) W SSICLK W SSI RX/TXFR W SSITXDA W SSIRXDA 158 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Figure 32. SSI1 Interface for AD7811/2 W W W W ' W ' Figure 33. SSI2 Interface Timings CS89712 DO9 DO8 ' ' ' ' ' ' DO1 DO0 DS502PP2 ...
Page 159
... TRX1 t TRX2 t TRX3 t TRX4 t TRX5 t LN1 t LN2 t LN3 t LN4 t LN5 t LN6 t SKS t CCS t DIS t DIH CSH TRX2 t TRX4 Figure 34. 10BASE-T Receive CS89712 Min Typ Max Unit - - ±13 ±13 540 - bits - 270 - 100 200 ns 2 ...
Page 160
... LN1 TXD± RXD± t LN6 LINKLED EESK EECS EEData Out EEData In (Read) 160 t LN2 t LN3 t LN4 Figure 35. 10BASE-T Link Integrity t SKS t CSS t DIH t DIS t DH Figure 36. EEPROM CS89712 t LN5 t CSH t CS DS502PP2 ...
Page 161
... Notes center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor. 2. The Rt and Rr resistors are ±1% tolerance. 3. The CS89712 Ethernet port supports 100 W unshielded twisted pair cables. The proper values of Rt and Rr, for a given cable impedance, are shown below: Cable Impedance ( ) ...
Page 162
... I/O Buffer Strength & Characteristics All I/O buffers on the CS89712 are CMOS thresh- old input bidirectional buffers except the oscillator and power pads. For signals that are nominally in- puts, the output buffer is only enabled during pin test mode. All output buffers are three stated during system (hi-Z) test mode ...
Page 163
... ORDERING INFORMATION The order number for the device is: CS89712 — CB Product Line: Crystal Note: Contact Cirrus Logic for up-to-date information on revisions the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. DS502PP2 Package Type Plastic Ball Grid Array ( mm) ...
Page 164
... Start-of-Frame. SQE Signal Quality Error. SSI Synchronous Serial Interface. TAP Test Access Port. TestCTL Test Control. TLB Translation Lookaside Buffer. TxCFG Transmit Configuration. TxCMD Transmit Command. TxEvent Transmit Event. UTP Unshielded Twisted Pair. Table 93. Acronyms and Abbreviations (Continued) CS89712 DS502PP2 ...
Page 165
... DA to the FCS to be transmitted, or that has been received. • Frame Check Sequence The 32-bit field at the end of a frame that con- tains the cyclic redundancy check result. • Individual Address The specific Ethernet address assigned to a de- vice attached to the Ethernet media. CS89712 165 ...
Page 166
... Moving frame data across the memory bus from the Ethernet port RAM to system RAM. During receive operations, only frame data are transferred (preamble and SFD are stripped off by the CS89712’s MAC engine). The FCS may or may not be transferred, depending on the configuration. Transfers are counted in bytes. • ...
Page 167
... BNE uart_ready_loop 00000044 00000044 ;;; Read the data, store it, and accumulate checksum 00000044 E59C0480 LDR r0, [r12, #Hw_UARTDR1] ; Read data 00000048 E4C80001 STRB r0, [r8 Save it in memory DS502PP2 0x0480 0x04c0 0x00000017 ; 9600 baud divisor = 23 0x0000000b ; 9600 baud divisor = 11 0x00060000 CS89712 167 ...
Page 168
... Have to pad the tail out to 31 words, then the checksum. 00000074 00000074 0000000000 ALIGN 128, -4 0000007C uart_checksum 0000007C 436B74AB DCD 0x436b74ab 00000080 00000080 ASSERT (. - start_of_rom) = 640 ; Check that it’s in the right place 00000080 00000080 END 168 ; Return to caller for secure image ; Align just before end of 128-byte tail CS89712 DS502PP2 ...
Page 169
Notes • ...
Page 170
...