CS4952-CL Cirrus Logic, Inc., CS4952-CL Datasheet
CS4952-CL
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CS4952-CL Summary of contents
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... FAX: (512) 445 7581 http://www.crystal.com Description The CS4952/3 provides full conversion from YCbCr or YUV digital video formats into NTSC & PAL Composite and Y/C (S-video) analog video. Input formats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with sup- port for EAV/SAV codes ...
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... Register Description ...............................................................................................28 Control Register 0 ............................................................................................28 Control Register 1 ............................................................................................29 Control Register 2 ............................................................................................30 DAC Power Down Register ..............................................................................30 Status Register.................................................................................................31 Background Color Register ..............................................................................31 GPIO Control Register .....................................................................................31 GPIO Data Register .........................................................................................32 Chroma Filter Register .....................................................................................32 Luma Filter Register .........................................................................................32 I2C Address Register .......................................................................................32 Subcarrier Amplitude Register .........................................................................33 2 CS4952/53 DS223PP2 ...
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... BOARD DESIGN & LAYOUT CONSIDERATIONS ......................................................... 36 Power and Ground Planes ..................................................................................... 36 Power Supply Decoupling ...................................................................................... 36 VREF Decoupling ................................................................................................... 36 Digital Interconnect ................................................................................................ 36 Analog Interconnect ............................................................................................... 37 Analog Output Protection ....................................................................................... 37 ESD Protection ....................................................................................................... 37 External DAC Output Filter ..................................................................................... 37 DEVICE PINOUT - 44 PLCC ............................................................................................ 38 PLCC Pin Description ............................................................................................ 39 DEVICE PINOUT - 44 TQFP ............................................................................................ 41 TQFP Pin Description ............................................................................................ 42 DS223PP2 CS4952/53 3 ...
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... Power Supplies: Digital Analog Operating Ambient Temperature 4 (AGND, DGND = 0 V, all voltages with respect to 0 V.) Symbol V AA Except Supply Pins Except Supply Pins Power Applied (AGND, DGND = 0 V, all voltages with Symbol Min V 4. CS4952/53 Min Max Units -0.3 6 -50 + +0.3 -0 ...
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... High-Z Digital Outputs - CVBS37/Y/C (Note 1) IO37 CVBS75 (Note 1) IO75 CVBS37/Y/C (Note 1) IB37 CVBS75 (Note 1) IB35 MAT OUT C OUT O DEL T (Note All DACs CVBS75/CVGS37 only CVBS75 only AA CS4952/53 Min Typ Max Units V +0 -0.3 - 0.8 -10 - + 0.4 -10 - +10 32.9 34.7 36.5 16.4 17.3 18.2 64 ...
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... Static Performance DAC Resolution Differential Non-Linearity Integral Non-Linearity Dynamic Performance Differential Gain Differential Phase Signal to Noise Ratio Hue Accuracy Saturation Accuracy 6 (Continued) Symbol DNL INL DB DP SNR CS4952/53 Min Typ Max Units - - 9 Bits -1 ±0.5 +1 LSB -1 ±0.35 +1 LSB - ±0.5 ± ...
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... Symbol F T sph ssu T sds sds sph T vdo T T spl sf 2 Figure Host Port Timing CS4952/53 Min Typ Max 14.82 18.52 22.58 ch 14.82 18.52 22. isu Min Typ Max 100 1000 clk 0.1 0.7 spl 100 sh 100 ...
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... T rah T rda T rdh wpw T wds T wdh T rec T wac rpw rah rda 8-bit Parallel Host Port Timing: Read Cycle T wpw T wac wds T rec Figure 3. CS4952/53 Min Typ Max rdh ...
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... A.C. CHARACTERISTICS: Parameter Reset Timing Reset Pulse Width RESET* DS223PP2 (Continued) Symbol T res T res Figure 4. Reset Timing CS4952/53 Min Typ Max Units 100 ns 9 ...
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... CVBS75 31 RD* 32 WR* CVBS37 CS4952 35 SDA CS4953 36 SCL 33 CLK 8 V[7:0] 7-14 15 FIELD 16 HSYNC*/CB 17 VSYNC* RESET* 6 TEST GND CS4952/ VREFIN 0.1 µ Modulator 75 4 Composite Video Connector S-Video Connector INT 37 40 ISET host interface) ...
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... In both Master and Slave Modes, all timing is sampled and assert- ed with the rising edge of the CLK pin. In most cases the CS4952/3 will serve as the video timing master. The master timing cannot be exter- nally altered other than through the host interface by changing the video display modes: PAL or NTSC and Progressive Scan ...
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... ADDR & XTAL device pins. In this instance the input CLK is continuously compared with the external crystal reference input and the internal timing of the CS4952/3 is automati- cally adjusted so that the color burst frequency re- mains close to the requirements. Controls are provided for phase adjustment of the burst to permit color adjustment and phase com- pensation ...
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... CS4952/3. Control Registers The control and configuration of the CS4952/3 is primarily accomplished through the control regis- ter block. All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during a chip re- set ...
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... Sync Generator uses externally provided horizontal and vertical sync signals to synchronize the internal timing of the CS4952/3. Video data that is sent to the CS4952/3 must be synchronized to the horizontal and vertical sync signals. Figure 6 illustrates horizontal timing for CCIR601 input in Slave Mode. Note that the ...
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... V [7:0] pins. Figure 7 illus- trates horizontal timing for CCIR601 input in Mas- ter Mode. Note that the CS4952/3 expects to receive the first active pixel data on clock cycle 245 (NTSC) when bit SYNC_DLY=0 CONTROL_2 ...
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... HSYNC* VSYNC* FIELD PAL Vertical Timing (even field) Line HSYNC* VSYNC* FIELD 264 265 266 267 265 311 312 313 314 Figure 8. Vertical Timing CS4952/ 268 269 270 271 315 316 317 318 DS223PP2 ...
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... V [7:0] pins is expected between lines 285 through line 525. PAL Interlaced The CS4952/3 supports PAL modes and Combination N where there are 625 total lines per frame and two fixed 312.5 line fields per frame and 25 total frames occuring per second. ...
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... Analog Field 7 624 625 Analog Field 8 312 313 314 315 316 317 Burst Phase = 225 degrees relative to U Figure 10. PAL Video Interlaced Timing CS4952/ 318 319 320 336 337 318 319 320 336 ...
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... Please reference Figure 12 for NTSC interlaced timing. Digital video input is ex- pected to be delivered to the CS4952/3 V [7:0] pins for 240 lines beginning on active video line 22 and continuing through line 261. ...
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... Figure 11. PAL Video Non-Interlaced Progressive Scan Timing 20 VSYNC* Drops Analog Field 1 313 Analog Field 2 312 Analog Field 3 313 Analog Field 4 312 Burst Phase = 225 degrees relative to U CS4952/ DS223PP2 ...
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... Burst begins with negative half-cycle 0 Burst phase = reference phase = 180 relative to B Ancilliary Data 268 Clocks (NTSC) 280 Clocks (PAL) Horizontal Blanking Figure 13. CCIR656 Input Mode Timing CS4952/ ...
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... BKG_COLOR register (0x08). The colorspace of the register is RGB 3:3:2 and is unaffected by gamma correction. The default color following RE- SET is blue. In mode 1 the CS4952/3 supports a single 8-bit 27 MHz CbYCrY source as input on the V [7:0] pins. Input video timing can be CCIR601 master or slave and progressive scan. ...
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... Color Bar Generator enabled the The CS4952/3 is equipped with a color bar genera- tor that is enabled through the CBAR bit of the CONTROL_1 register. The color bar generator works in Master or Slave Mode and has no effect on the video input/output timing ...
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... The GPIO port PDAT [7:0] pins are configured for output GPIO_CTRL_REG [7:0] bits are set. In GPIO out- put mode, the CS4952/53 will output the data in GPIO_DATA_REG [7:0] bit locations onto the corresponding PDAT [7:0] pins when it detects a register address 0x0A through the I ANALOG ...
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... VREF The CS4952/3 can operate with or without the aid of an external voltage reference. The CS4952/3 is designed with an internal voltage reference genera- tor that provides a VREFOUT signal. The internal voltage reference is utilized by electrically con- necting the VREFOUT and VREFIN pins. VRE- FIN can also be connected to an external precision 1 ...
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... When disabled, no current flow from the output. For a complete disable and lower power operation the CVBS37 DAC can be totally shut down via the C_37_PD control register bit in the DAC register (0x08). In this mode turn-on through the control register will not be instantaneous. CS4952/53 load. DS223PP2 ...
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... C bus address for the CS4952/3 is program- mable via register I2C_ADR (0x0F). 8-bit Parallel Interface The CS4952/3 is equipped with a full 8-bit parallel microprocessor write and read control port. Along with the PDAT [7:0] pins the control port interface is comprised of host read RD and host write WR ...
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... Register Description A set of internal registers are available for control- ling the operation of the CS4952/3. The registers extend from internal address 0x00 through 0x3D. Table 5 shows a complete list of these registers and Address 0x00 0x01 0x02 0x03 0x04 0x05 - 0x06 0x07 0x08 0x09 ...
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... MSTR CCIR656 0 0 Function NTSC-M CCIR601 timing (default) NTSC-M RS170A timing PAL-N (non Argentina) CONTROL_1 Read/Write 5 4 C_BW C_LPF_EN 0 0 Function CS4952/53 Default Value = 01h PROG IN_MODE CBCR_UV PAL- PAL-M PAL-N (Argentina) reserved Default Value = 04h ...
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... DAC for chroma output (0: tri-state, 1: enable) 30 CONTROL_2 Read/Write 5 4 RESERVED 0 0 Function DAC Read/Write 5 4 Y_PD C_PD C_75_EN 1 1 Function CS4952/53 Default Value = 00h SYNC_DLY XTAL Default Value = F0h C_37_EN Y_EN load (0: power up, 1: power down) ...
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... DS223PP2 STATUS Read Only 5 4 CC_INT_21 CC_INT_284 0 0 Function BKG_COLOR Read/Write 5 4 BG_COLR 0 0 Function GPIO_CTRL_REG Read/Write 5 4 GPIO_IO 0 0 Function CS4952/53 Default Value = 00h VS_INT FIELD Default Value = 03h Default Value = 00h ...
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... GPIO_DATA mode. C_AMP Read/Write 5 4 C_COEF 0 0 Y_AMP Read/Write 5 4 Y_COEF 0 0 I2C_ADR Read/Write CS4952/53 Default Value = 00h Function Default Value = 80h Function Default Value = 80h Function Default Value = N/A 3 ...
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... Subcarrier synthesis bits 15:8 - Subcarrier synthesis bits 23:16 - Subcarrier synthesis bits 31:24 HUE_LSB Read/Write 5 4 LSB 0 0 Function HUE_MSB Read/Write 5 4 RESERVED 0 0 Function CS4952/53 Default Value = 1Ch Default Value = 3Eh Function Default Value = 00h Default Value = 00h ...
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... INT_EN Read/Write 5 4 RESERVED 0 0 CS4952/53 Default Value = 00h EN_284 Function Default Value = 00h Function Default Value = 00h 3 ...
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... Device ID Register Address 0x3D Bit Number 7 6 Bit Name Default 0 0 Bit Mnemonic 7:4 DEV_ID 0000 device ID for CS4952 0001 device ID for CS4953 3:0 - These bits are reserved and the value they return on a read is not defined DS223PP2 INT_CLR Read/Write 5 4 RESERVED 0 0 Function ...
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... A split analog/digital ground plane should be connected at one point as close as possible to the CS4952/3. A split analog/digital power plane should be connect one point as close as possible to the power en- try point and decoupled properly. ...
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... If microstrip techniques are used, split the analog and digital ground planes and use proper RF decoupling techniques. Analog Interconnect The CS4952/3 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. All un- used analog outputs should be placed in shutdown. ...
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... XTAL ADDR VAA GND GND CS4952/3-CL 11 44-pin 12 PLCC 13 Top View CS4952/ VREFOUT VREFIN ISET VAA GND 40 39 RESET 38 SCL 37 36 SDA 35 INT 34 33 CLKIN PDAT0 28 PDAT1 PDAT2 PDAT3 ...
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... CURRENT Chrominance analog output for driving 37.5 OUT Internal voltage reference output IN External voltage reference input OUT DAC current set OUT Interrupt output, active high IN Active low master reset IN TEST pin. Ground for normal operation supply PS Ground CS4952/53 Description loads loads loads loads 39 ...
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... JEDEC # : MS-018 CS4952/53 e D2/ MILLIMETERS MIN MAX 4.572 3.048 0.533 17.653 16.662 16.002 17.653 16.662 16.002 1.524 DS223PP2 ...
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... CS4952/3- 44-pin 6 28 TQFP 7 27 Top View CS4952/ VREFOUT VREFIN ISET VAA GND RESET SCL SDA INT CLKIN WR RD PDAT0 PDAT1 PDAT2 PDAT3 PDAT4 PDAT5 PDAT6 PDAT7 41 ...
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... CURRENT Chrominance analog output for driving 37.5 OUT Internal voltage reference output IN External voltage reference input OUT DAC current set OUT Interrupt output, active high IN Active low master reset IN TEST pin. Ground for normal operation supply PS Ground CS4952/53 Description loads loads loads loads DS223PP2 ...
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... MAX 0.000 0.065 0.002 0.006 0.012 0.018 0.478 0.502 0.404 0.412 0.478 0.502 0.404 0.412 0.029 0.037 0.018 0.030 0.000 7.000 JEDEC # : MS-026 CS4952/ MILLIMETERS MIN MAX 0.000 1.600 0.050 0.150 0.300 0.450 11.700 12.300 9.900 10.100 11.700 12 ...
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