CS8411-CP Cirrus Logic, Inc., CS8411-CP Datasheet
CS8411-CP
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CS8411-CP Summary of contents
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... Differential or single ended inputs can be decoded. The CS8411 has a configurable internal buffer memory, read via a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. ...
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... TABLE OF CONTENTS CHARACTERISTICS/SPECIFICATIONS ............................................................ 3 ABSOLUTE MAXIMUM RATINGS .............................................................. 3 RECOMMENDED OPERATING CONDITIONS .......................................... 3 DIGITAL CHARACTERISTICS.................................................................... 3 DIGITAL CHARACTERISTICS - RS422 RECEIVERS................................ 4 SWITCHING CHARACTERISTICS - CS8411 PARALLEL PORT............... 4 SWITCHING CHARACTERISTICS - SERIAL PORTS................................ 5 GENERAL DESCRIPTION .................................................................................. 7 Line Receiver .............................................................................................. 7 Clocks and Jitter Attenuation ...................................................................... 7 CS8411 DESCRIPTION ....................................................................................... 8 Parallel Port ................................................................................................ 8 Status and IEnable Registers ..................................................................... 8 Control Registers ...................................................................................... 11 Audio Serial Port ...
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... T A Symbol except RXP, RXN V IH except RXP, RXN V IL (IO = 200 µ (IO = -3.2 mA CS8411/12- CS8411/12- Note 3 Note 3 MCK t j CS8411 CS8412 Min Max 6.0 ± 10 -0.3 VD+ + 0.3 -12 12 -55 125 -65 150 Min ...
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... Vp-p for the differential voltage on RXP to RXN to exceed 200mV. This represents twice the minimum signal level of 200 mVp-p specified in CP340/1201 and IEC-958 (which are not RS-422 compliant). SWITCHING CHARACTERISTICS - CS8411 PARALLEL PORT fixes '-CP' and '-CS - °C for suffixes '-IP' and '-IS'; VD+, VA ± 10%; Inputs: Logic 0 = DGND, A logic 1 = VD+ ...
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... The table above assumes data is output on the falling edge and latched on the rising edge. With the CS8411 the edge is selectable. The table is defined for the CS8411 with control reg. 2 bit 0, SCED, set to one, and for the CS8412 in formats and 7. For the other formats, the table and figure edges must be reversed (i.e.. " ...
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... VA+ VD+ MCK 21 AGND FSYNC SCK SDATA 9 RXP ERF CS8411 10 INT RXN CS 20 FILT RD/ DGND Figure 1. CS8411 Typical Connection Diagram +5V digital +5V analog 0 VA+ VD+ MCK 21 AGND VERF SCK 9 RXP SDATA 10 FSYNC RXN CS8412 13 CS12/FCK 16 C SEL 25 U ERF ...
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... VCO frequency is pulled to its minimum value master, SCK is always MCK divided by four, producing a frequency of 64 × FS. In the CS8411, FSYNC can be programmed divided version of MCK or it can be generated directly from the in- coming data stream. In the CS8412, FSYNC is al- ways generated from the incoming data stream ...
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... Detailed timing for the parallel port can be found in the Switching Characteristics - Parallel Port table. The memory space on the CS8411 is allocated as shown in Figure 5. There are three defined buffer modes selectable by two bits in control register 1. Further information on the buffer modes can be found in the Control Registers section ...
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... DS61F1 19 Bi-phase Decoder De-Multiplexor crc check Figure 4. CS8411 Block Diagram FLAG2 causes an interrupt on the rising edge only. Further information, including timing, on the flags can be found in the Buffer Memory section. The next five CRCE/CRC1, and CSDIF/CRC2, are latches which are set when their corresponding conditions occur, and are reset when SR1 is read ...
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... Figure 6. Status/IEnable Register 1 10 SLIP is only valid when the audio port is in slave mode (FSYNC and SCK are inputs to the CS8411). This flag is set when an audio sample is dropped or reread because the audio data output from the part different frequency than the data received from the transmission line ...
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... INT. ENABLE BITS bits and must be set to zero when writing to this FOR ABOVE register. The CS8411 sets these bits to zero on pow- er-up. Control Registers The CS8411 contains two control registers. Control register1 (CR1), at address 2, selects system level features, while control register 2 (CR2), at address 3, configures the audio serial port ...
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... SCED: ROER, when set, causes the last audio sample to be reread if the error pin, ERF, is active. When out of lock, the CS8411 will output zeros if ROER is set and output random data if ROER is not set. The conditions that activate ERF are those reported in SR2 and enabled in IER2 ...
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... FSYNC and SCK different time- base than the CS8411. If the audio data is read twice or missed, the SLIP bit in SR1 is set. SCED selects the SCK edge to output data on. SCED high causes data to be output on the falling edge, and SCED low causes data to be output on the rising edge ...
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... FSYNC output modes. If the circuit generating SCK and FSYNC is not locked to the master clock of the CS8411, the serial port will eventually be re- read or a sample will be missed. When this occurs, the SLIP bit in SR1 will be set. ...
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... The lower portion of Figure 11 expands the first byte of channel status showing eight pairs of DS61F1 CS8411 CS8412 data, with a pair defined as a frame. This is further expanded showing the first sub-frame (A0) to con- tain 32 bits defined as per the digital audio stan- dards ...
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... Aux Data LSB Audio Data Figure 11. CS8411 Status Register Flag Timing Buffer Mode 1 In buffer mode 1, eight bytes are allocated for chan- nel status data and sixteen bytes for auxiliary data as shown in Figure 5. The user data buffer is the same for all modes. The channel status buffer, loca- tions 08H to 0FH, is divided into two sections ...
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... FLAG2 FLAG1 FLAG0 C.S. Byte 0B 0C C.S. Address 08 FLAG0 C.S. Addr User Addr Figure 12. CS8411 Buffer Memory Write Sequence - MODE 0 FLAG2 FLAG1 FLAG0 C.S. Byte C.S. Address FLAG1 FLAG0 C.S. Addr User Addr Aux. Addr 13,14 17 Figure 13. CS8411 Buffer Memory Write Sequence - MODE 1 ...
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... Four auxiliary data bits are received per audio sample (sub-frame) and, since the auxiliary data is four times larger than the user data, the aux- iliary data buffer on the CS8411 is four times larger allowing FLAG0 to be used to monitor both. FLAG2 FLAG1 FLAG0 C ...
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... Buffer Updates and Interrupt Timing As mentioned previously in the buffer mode sec- tions, conflicts between externally reading the buffer RAM and the CS8411 internally writing to it may be averted by using the flag levels to avoid the section currently being addressed by the part. How- ever, if the interrupt line, along with the flags, is utilized, the actual byte that was just updated can be determined ...
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... PIN DESCRIPTIONS: CS8411 DATA BUS BIT 2 DATA BUS BIT 3 DATA BUS BIT 4 DATA BUS BIT 5 DATA BUS BIT 6 DATA BUS BIT 7 DIGITAL POWER DIGITAL GROUND RECEIVE POSITIVE RECEIVE NEGATIVE FRAME SYNC SERIAL DATA CLOCK ADD BUS BIT 4 / FCLOCK INTERRUPT Power Supply Connections VD+ - Positive Digital Power, PIN 7 ...
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... INT - Interrupt, PIN 14. Open drain output that can signal the state of the internal buffer memory as well as error information resistor to VD+ is typically used to support logic gates. All bits affecting INT are maskable to allow total control over the interrupt mechanism. DS61F1 CS8411 CS8412 21 ...
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... RS422 compatible line receivers. Described in detail in Appendix A. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 1k resistor and 0.047 µF capacitor are required from the FILT pin to analog ground. 22 CS8411 CS8412 DS61F1 ...
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... CS8412 is illustrated in Figure 16. The line receiver and jitter performance are de- scribed in the sections directly preceding the CS8411 sections in the beginning of this data sheet. Audio Serial Port The audio serial port is used primarily to output au- dio data and consists of three pins: SCK, FSYNC, and SDATA ...
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... MCK. The CS8412 comes out of reset at the first block boundary after leaving the reset state recommended to reset the CS8412 after power-up and any time the user performs a system-wide reset. A suggested reset circuit is shown in Appendix B. CS8411 CS8412 M1 M0 Format 0 0 ...
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... MSB LSB Left MSB LSB Left LSB MSB 16 Bits Left MSB LSB 18 Bits Left MSB LSB Figure 17. CS8412 Audio Serial Port Formats CS8411 CS8412 Right MSB LSB Right MSB LSB Right MSB LSB Right MSB LSB Right LSB MSB Right LSB ...
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... Figure 19. Multifunction Pins There are seven multifunction pins which contain either error and received frequency information, or channel status information, selectable by SEL. Right 0 Left 1 Right 31 Figure 19. CBL Timing CS8411 CS8412 Right MSB AUX LSB Right AUX MSB LSB ...
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... CS12 is low, channel status for sub-frame1 is dis- played, and if CS12 is high, channel status for sub- frame 2 is displayed. The contents of Ca-Ce depend upon the C0 professional/consumer bit. The infor- mation reported is shown in Table 7. Pin CS8411 CS8412 F1 F0 Sample Frequency 0 0 Out of Range kHz ± 44.1 kHz ± ...
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... C bit to 0 (copyright pro- tection asserted) and the L bit to1 (original). To support this feature, Ce, in the consumer mode, is defined as IGCAT (ignorant category) which is low for the "general" (0000000) and "A/D converter without copyright information" (01100xx) catego- ries. CS8411 CS8412 DS61F1 ...
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... SCK CS12/FCK 13 16 SEL CBL CS8411 CS8412 VALIDITY + ERROR FLAG FREQ REPORT 2 SERIAL OUTPUT DATA ERROR FLAG SERIAL PORT MODE SELECT 1 SERIAL PORT MODE SELECT 2 ANALOG POWER ANALOG GROUND FILTER MASTER CLOCK SERIAL PORT MODE SELECT 2 SERIAL PORT MODE SELECT 3 ...
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... Ca-Ce pins. These pins are updated with the rising edge of CBL. CS12 - Channel Select, PIN 13. This pin is also dual function and is selected by bringing SEL high. CS12 selects sub-frame1 (when low) or sub-frame2 (when high displayed by channel status pins C0 and Ca through Ce. 30 CS8411 CS8412 DS61F1 ...
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... RS422 compatible line receivers. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 1 k resistor and 0.047 µF capacitor is required from FILT pin to analog ground. DS61F1 CS8411 CS8412 31 ...
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... ORDERING GUIDE Model CS8411 - CP CS8411 - IP CS8411 - CS CS8411 - IS CS8412 - CP CS8412 - IP CS8412 - CS CS8412 - IS * Although the ‘-CP’ and ‘-CS’ suffixed parts are guaranteed to operate over °C, they are tested at 25 °C only. If testing over temperature is desired, the ‘-IP’ and ‘-IS’ suffixed parts are tested over their speci- fied temperature range ...
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... MAX 0.000 0.250 0.015 0.025 0.125 0.195 0.014 0.022 0.030 0.070 0.008 0.014 1.380 1.565 0.600 0.625 0.485 0.580 0.090 0.110 0.580 0.620 0.600 0.700 0.000 0.060 0.115 0.200 0° 15° CS8411 CS8412 SIDE VIEW MILLIMETERS MIN MAX 0.00 6.35 0.38 0.64 3.18 4.95 0.36 0.56 0.76 1.78 0.20 0.36 35.05 39.75 15.24 15.88 12.32 14.73 2.29 2.79 14 ...
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... PLANE e DIM INCHES MIN MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 17.70 0.291 0.299 0.040 0.060 0.394 0.419 10.00 0.016 0.050 0° 8° CS8411 CS8412 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 18.10 7.40 7.60 1.02 1.52 10.65 0.40 1.27 0° 8° DS61F1 ...
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... APPENDIX A: RS422 RECEIVER INFORMATION The RS422 receivers on the CS8411 and CS8412 are designed to receive both the professional and consumer interfaces, and meet all specifications listed in the digital audio standards. Figure 20 illus- trates the internal schematic of the receiver portion of both chips. The receiver has a differential input. ...
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... RCA Phono 75 75 Coax Figure 23. Consumer Input Circuit 36 TTL/CMOS Levels The circuit shown in Figure 24 may be used when external RS422 receivers or TTL/CMOS logic drive the CS8411/12 receiver section. TTL/CMOS CS8411/12 RXP RXN Transformers 0.01 F Please refer to Application Note AN134: AES and S/PDIF Recommended Transformers for further information ...
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... This is accomplished by pulling all four DS61F1 Figure 25. CS8412 Reset Circuit Mode Select pins high. Figure 25 shows a simple circuit to implement this. The OR gates can be 74LS32 type gates. CS8411 CS8412 RESET 37 ...
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