CY7C401-10DMB Cypress Semiconductor Corporation., CY7C401-10DMB Datasheet
CY7C401-10DMB
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CY7C401-10DMB Summary of contents
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... Capable of withstanding greater than 2001V electro- static discharge • Pin compatible with MMI 67401A/67402A Functional Description The CY7C401 and CY7C403 are asynchronous first-in first-out (FIFOs) organized as 64 four-bit words. The CY7C402 and CY7C404 are similar FIFOs organized as 64 five-bit Logic Block Diagram ...
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... CC CC Output Disabled (CY7C403 and CY7C404) [ Max GND CC OUT V = Max OUT Test Conditions MHz 4. CY7C401/CY7C403 CY7C402/CY7C404 Ambient Temperature + 10% – +125 C 5V 10% [2] 7C40X–10, 15, 25 Min. Max. 2.4 0.4 2.0 6.0 –3.0 0.8 –10 +10 – ...
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... Note 10 5 Note Note 11 50 — Note 12 — ) conditions exist. BT –500 mV and V +500 mV levels on the output CY7C401/CY7C403 CY7C402/CY7C404 ALL INPUT PULSES 90% 90% 10 7C40X–10 7C40X–15 7C40X–25 Min. Max ...
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... SO leading edge for each FIFO. This is a solution for any number of FIFOs in parallel. Any of the above solutions will ensure the correct operation of a Cypress FIFO at 25 MHz. The specific implementation is left to the designer and is dependent on the specific application needs. 4 CY7C401/CY7C403 CY7C402/CY7C404 ...
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... PHSO OUTPUT READY t HSO DATA OUT Bubble Through, Data Out To Data In Diagram SHIFT OUT SHIFT IN INPUT READY DATA IN I PLSI t DLIR I/f I PLSO t DLOR SIR 5 CY7C401/CY7C403 CY7C402/CY7C404 I DHIR O t DHOR t SOR t PIR t HIR C401–9 C401–10 C401–11 ...
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... Master Reset Timing Diagram MASTER RESET INPUT READY OUTPUT READY SHIFT IN DATA OUT Output Enable Timing Diagram OUTPUT ENABLE DATA OUT SOR t PMR t DIR t DOR t DSI t LZMR t t HZOE OOE NOTE 10 6 CY7C401/CY7C403 CY7C402/CY7C404 t POR C401–12 C401–13 C401–14 ...
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... AMBIENTTEMPERATURE ( C) NORMALIZED FREQUENCY vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 0.8 0.6 –55 25 AMBIENT TEMPERATURE ( C) NORMALIZED I vs. FREQUENCY 1.1 1.0 0.9 0.8 0.7 0.0 400 600 800 1000 CY7C401/CY7C403 CY7C402/CY7C404 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE =5. = 125 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 ...
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... CY7C401/CY7C403 CY7C402/CY7C404 OR OUTPUT READY SO SHIFT OUT DATA OUT C401–16 SHIFT OUT ...
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... Ordering Code 5 CY7C401–5PC 10 CY7C401–10DC CY7C401–10PC CY7C401–10DMB CY7C401–10LMB 15 CY7C401–15DC CY7C401–15PC CY7C401–15DMB CY7C401–15LMB 25 CY7C401–25DC CY7C401–25PC CY7C401–25DMB CY7C401–25LMB Speed Package (MHz) Ordering Code 5 CY7C402–5PC 10 CY7C402–10DC CY7C402–10PC CY7C402–10DMB CY7C402– ...
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... Molded DIP D4 18-Lead (300-Mil) CerDIP L61 20-Pin Square Leadless Chip Carrier D4 18-Lead (300-Mil) CerDIP P3 18-Lead (300-Mil) Molded DIP D4 18-Lead (300-Mil) CerDIP L61 20-Pin Square Leadless Chip Carrier 10 CY7C401/CY7C403 CY7C402/CY7C404 Operating Range Commercial Military Commercial Military Commercial Military Operating Range Commercial Military ...
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... Max CY7C401/CY7C403 CY7C402/CY7C404 Switching Characteristics Parameters Subgroups 10 10, 11 PHSI 10, 11 PLSI 10, 11 SSI 10, 11 HSI ...
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... Package Diagrams 16-Lead (300-Mil) CerDIP D2 MIL-STD-1835 D- 2 Config.A 20-Pin Square Leadless Chip Carrier L61 MIL-STD-1835 C–2A CY7C401/CY7C403 CY7C402/CY7C404 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-8 Config.A 12 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 16-Lead (300-Mil) Molded DIP P1 18-Lead (300-Mil) Molded DIP P3 CY7C401/CY7C403 CY7C402/CY7C404 ...
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