CY7C4292V-15ASI Cypress Semiconductor Corporation., CY7C4292V-15ASI Datasheet

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CY7C4292V-15ASI

Manufacturer Part Number
CY7C4292V-15ASI
Description
CY7C4292V-15ASI64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and Depth Expansion
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-06021 Rev. *B
Features
Table 1.
Logic Block Diagram
FS1/SEN
• High-speed, low-power, Unidirectional, First-in,
• 1Kx36 (CY7C43643)
• 4Kx36 (CY7C43663)
• 16Kx36 (CY7C43683)
• 0.35-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5 ns read/write cycle
• Low power
FS0/SD
MRS2
First-out (FIFO) memories w/bus matching capabilities
times)
MRS1
CLKA
W/RA
— I
— I
FF/IR
A
MBA
SPM
CSA
ENA
PRS
0–35
RT
AF
CC
SB
= 10 mA
= 100 mA
MBF2
FIFO,
Mail1
Mail2
Reset
Logic
36
Port A
Control
Logic
1K/4K/16K x36 Unidirectional Synchronous
Programmable
Flag Offset
Registers
3901 North First Street
Write
Pointer
Mail2
Register
Dual Ported
Memory
Status
Flag Logic
1K/4K/16K
Mail1
Register
x36
Timing
Mode
Read
Pointer
• Fully asynchronous and simultaneous read and write
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
• Retransmit function
• Standard or FWFT mode user selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
operation permitted
Almost Empty flags
San Jose
FIFO with Bus Matching
CA 95134
Revised December 26, 2002
Port B
Control
Logic
36
CY7C43643
CY7C43663
CY7C43683
408-943-2600
BE/FWFT
MBF1
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
B
0–35

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CY7C4292V-15ASI Summary of contents

Page 1

Features • High-speed, low-power, Unidirectional, First-in, First-out (FIFO) memories w/bus matching capabilities • 1Kx36 (CY7C43643) • 4Kx36 (CY7C43663) • 16Kx36 (CY7C43683) • 0.35-micron CMOS for optimum speed/power • High-speed 133-MHz operation (7.5 ns read/write cycle times) • Low power — ...

Page 2

Pin Configuration W/RA 1 ENA 2 CLKA 3 GND GND ...

Page 3

Pin Definitions Signal Name Description I/O A Port A Data I 0–35 AE Almost Empty O Programmable Almost Empty flag synchronized to CLKA LOW when the Flag (Port B) AF Almost Full Flag O Programmable Almost Full flag ...

Page 4

Pin Definitions (continued) Signal Name Description I/O FS1/SEN Flag Offset I Select 1/Serial Enable FS0/SD Flag Offset I Select 0/Serial Data MBA Port A Mailbox I Select MBB Port B Mailbox I Select MBF1 Mail1 Register O MBF1 is set ...

Page 5

Functional Description The CY7C436x3 is a monolithic, high-speed, low-power, CMOS Unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 133 MHz and has read access times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-port SRAM ...

Page 6

FIFO following a Master Reset would be inconvenient. Big Endian/First-Word Fall-Through (BE/FWFT) This is a dual-purpose pin. At the time of Master Reset, the BE select function is active, permitting a choice of Big or Little Endian byte ...

Page 7

CSB is HIGH or W/RB is LOW. The B lines are active outputs when CSB 0–35 is LOW and W/RB is HIGH. Data is read from the FIFO to the B LOW-to-HIGH ...

Page 8

Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect the new level of fill. Therefore, the Almost empty flag of a FIFO containing (X+1) or more ...

Page 9

Furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations. In this case, only those byte lanes ...

Page 10

BYTE ORDER ON PORT SIZE SIZE SIZE SIZE SIZE Document #: 38-06021 Rev. *B ...

Page 11

Table 2. Flag Programming SPM FS1/SEN Table 3. Port A Enable Function CSA W/RA ENA MBA ...

Page 12

Table 6. Data Size for FIFO Long-Word Reads [9] Size Mode BM SIZE Table 7. Data Size for Word Reads [9] Size Mode BM SIZE Table 8. Data ...

Page 13

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ...................................–65 Ambient Temperature with Power Applied...............................................–55 Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs [11] ...

Page 14

AC Test Loads and Waveforms (- Switching Characteristics Over the Operating Range Parameter Description f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or CLKB CLK t Pulse Duration, CLKA or CLKB ...

Page 15

Switching Characteristics Over the Operating Range (continued) Parameter Description [18] t Skew Time between CLKA and CLKB for EF/OR SKEW1 and FF/IR [18] t Skew Time between CLKA and CLKB for AE SKEW2 and AF t Access Time, CLKA to ...

Page 16

Switching Waveforms Master Reset Loading X and Y with a Preset Value of Eight CLKA CLKB t RSTS MRS1, MRS2 BE/FWFT SPM FS1/SEN, FS0/SD t RSF FF/IR t RSF EF/OR t RSF AE t RSF AF t RSF MBF1 Partial ...

Page 17

Switching Waveforms (continued) Parallel Programming of the Almost Full Flag and Almost Empty Flag Offset Values after Reset [22] (CY Standard and FWFT Modes) CLKA MRS1, MRS2 t t FSS FSH SPM t t FSS FSH FS1/SEN, FS0/SD FF/IR ENA ...

Page 18

Switching Waveforms (continued) Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes) t CLK t CLKH CLKB EF/OR CSB [27] W/RB MBB ENB B t 0–35 EN (Standard Mode 0–35 (FWFT ...

Page 19

Switching Waveforms (continued) Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes) CLKB EF/OR HIGH CSB [27] W/RB MBB ENB t B MDV t 0–8 EN (Standard Mode MDV 0–8 (FWFT ...

Page 20

Switching Waveforms (continued) OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode) CLKA CSA LOW W/RA HIGH t t ENS ENH MBA t t ENS ENH ENA FF/IR HIGH ...

Page 21

Switching Waveforms (continued) EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode) CLKA CSA LOW W/RA HIGH t t ENS ENH MBA t t ENS ENH ENA FF/IR HIGH ...

Page 22

Switching Waveforms (continued) IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode) t CLK t t CLKL CLKH CLKB CSB LOW W/RB HIGH MBB t t ENS ENH ENB EF/OR HIGH 0–35 Previous ...

Page 23

Switching Waveforms (continued) FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode) t CLK t t CLKL CLKH CLKB CSB LOW W/RB HIGH MBB LOW t t ENS ENH ENB EF/OR HIGH ...

Page 24

Switching Waveforms (continued) Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes) CLKA t ENS ENA AF [D–(Y1+1)] Words in FIFO1 CLKB ENB Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes) ...

Page 25

Switching Waveforms (continued) Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) CLKA CSA t ENS [44] W/RA t ENS MBA t ENS ENA 0–35 CLKB MBF1 CSB [27] W/RB MBB ENB t EN ...

Page 26

Switching Waveforms (continued) Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) CLKB CSB [27] W/RB MBB ENB B 0–35 CLKA MBF2 CSA [44] W/RA MBA ENA FIFO2 Output Register 0 35 [47, 48, ...

Page 27

Ordering Information 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching Speed (ns) Ordering Code 7 CY7C43643–7AC 10 CY7C43643–10AC 15 CY7C43643–15AC 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching Speed (ns) Ordering Code 7 CY7C43663–7AC 10 CY7C43663–10AC 15 CY7C43663–15AC 16K x36 ...

Page 28

Package Diagram 128-Lead Thin Plastic Quad Flatpack ( 1.4 mm) A128 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06021 Rev. *B © Cypress Semiconductor Corporation, 2002. ...

Page 29

Document Title: CY7C43643/ CY7C43663/ CY7C43683 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching Document Number: 38-06021 REV. ECN NO. Issue Date ** 106563 05/17/01 *A 117172 09/05/02 *B 122273 12/26/02 Document #: 38-06021 Rev. *B Orig. of Change Description of ...

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