SAB-C541U-1EN Infineon Technologies AG, SAB-C541U-1EN Datasheet
SAB-C541U-1EN
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SAB-C541U-1EN Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C540U / C541U Data Sheet 10.97 ...
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C540U/C541U Data Sheet Revision History : Previous Releases : Page / Chapters Subjects (changes since last revision) Edition 1997-10-01 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! ...
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CMOS Microcontroller Advance Information • Enhanced 8-bit C500 CPU – Full software/toolset compatible to standard 80C51/80C52 microcontrollers • 12 MHz external operating frequency – 500 ns instruction cycle • Built-in PLL for USB synchronization • On-chip OTP program memory ...
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... P-LCC-44 and P-SDIP-52 packages • Power supply voltage range : 4.0V to 5.5V • Temperature Range : Table 1 Ordering Information Type Ordering Code SAB-C540U-EN Q67126-C2042 SAB-C540U-EP Q67120-C2043 SAB-C541U-1EN Q67126-C2001 SAB-C541U-1EP Q67120-C2021 Semiconductor Group three 8-bit ports and one 6-bit port T SAB-C540U = SAB-C541U = ...
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XTAL2 XTAL1 ALE PSEN EA RESET D+ D- Figure 2 Logic Symbol Additional Literature For further information about the C540U/C541U the following literature is available : Title C540U/C541U 8-Bit CMOS Microcontroller User’s Manual C500 Microcontroller Family Architecture and Instruction Set ...
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P1.2 / SCLK V V RESET P3.0 / LED2 P1.3 / SRI P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3 P3 This pin functionality ist not available for the C540U. Figure 3 Pin Configuration ...
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P1.0 / LED0 P1.1 / LED1 P1.2 / SCLK P3.0 / LED2 P1.3 / SRI P3.1 / DADD P3.2 / INT0 P3.3 / INT1 Figure 4 Pin Configuration ...
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Table 2 Pin Definitions and Functions Symbol Pin Numbers P-LCC-44 P-SDIP- P1 14, 41, 12, 34, 44 51, 15 ...
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Table 2 Pin Definitions and Functions Symbol Pin Numbers P-LCC-44 P-SDIP-52 P3.0 - P3 XTAL2 20 23 XTAL1 Input O = Output Semiconductor Group (cont’d) I/O*) Function ...
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Table 2 Pin Definitions and Functions Symbol Pin Numbers P-LCC-44 P-SDIP-52 P2 PSEN 32 38 ALE Input O = Output Semiconductor Group (cont’d) I/O*) ...
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Table 2 Pin Definitions and Functions Symbol Pin Numbers P-LCC-44 P-SDIP-52 P0 CCU SSU ...
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Oscillator Watchdog XTAL2 OSC & Timing XTAL1 ALE PSEN EA Progr. Watchdog RESET Timer (C541U only) Timer 0 Timer 1 SSC (SPI) Interface (C541U only Interrupt Unit 1) P-LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port Figure 5 ...
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CPU The C540U/C541U is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C540U/C541U CPU manipulates operands in the following four address spaces: – KByte on-chip OTP program memory – Totally Kbyte internal/external program memory – Kbyte of external data memory ...
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Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator ...
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... PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general enable bit for the USB clock ...
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The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 9 shows the recommended oscillator circuits for crystal and external clock operation. External Clock Signal Figure 9 Recommended ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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... The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e. ..., are bitaddressable. The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals ...
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... WDTREL Watchdog Timer Reload Register only) 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) The content of this SFR varies with the actual of the step C540U/C541U (eg This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set ...
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Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Pow. PCON Power Control Register Sav. PCON1 Power Control Register 1 Modes USB EPSEL USB Endpoint Select Register Module USBVAL USB Data Register ADROFF USB Address Offset Register ...
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... XX00 means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR is only available in the C541U. Semiconductor Group Bit 6 ...
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... X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR respectively bit is only available in the C541U. 5) These are read-only registers 6) The content of this SFR varies with the actual of the step C517A (e ...
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Table 5 Contents of the USB Device and Endpoint Registers (Addr Addr Register Reset Bit 7 Value EPSEL = 1XXX.XXXX B Device Registers C1 H DCR 000X. SPEED 0000 DPWDR 00 ...
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Table 5 Contents of the USB Device and Endpoint Registers (Addr (cont’d) Addr Register Reset Bit 7 Value EPSEL = 0XXX.X010 B Endpoint 2 Registers C1 H EPBC2 00 H STALL2 ...
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Digital I/O Ports The C540U/C541U in the P-SDIP-52 package has four 8-bit I/O ports. In the P-LCC-44 package port 6-bit I/O port only. Port open-drain bidirectional I/O port, while ports are ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 : Table 6 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler ...
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SSC Interface (C541U only) The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 12 shows the block diagram of the SSC. The central element of the ...
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USB Module The USB module in the C540U/C541U handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB ...
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USB Registers Two different kinds of registers are implemented in the USB module. The global registers (GEPIR, EPSEL, ADROFF, USBVAL) describe the basic functionality of the complete USB module and can be accessed via unique SFR addresses. For reduction of ...
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... Timer 0 Overflow Timer 1 Overflow P3.2 / INT0 IT0 ITCON.0 TCON.0 ITCON.1 P3.3 / INT1 IT1 ITCON.2 TCON.2 ITCON.3 Bit addressable Request Flag is cleared by hardware Figure 15 Interrupt Request Sources (Part 1) Semiconductor Group TF0 000B H ET0 TCON.5 IEN0.1 TF1 001B H ET1 TCON ...
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... EODIE0 EPIR0.1 EPIE0.1 SOD0 SODIE0 EPIR0.0 EPIE0.0 WCOL SCF.1 SSC Interrupts (C541U only) SCF.0 Bit addressable Request flag is cleared by hardware after the corresponding register has been read. Figure 16 Interrupt Request Sources (Part 2) Semiconductor Group EPI0 GEPIR.0 >1 GEPIE0 IEN1.1 EPBC0.4 >1 WCEN SCIEN.1 ...
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... DIRR.2 DIER.2 SUI SUIE DIRR.1 DIER.1 SOFI SOFIE DIRR.0 DIER.0 Bit addressable Request flag is cleared by hardware after the corresponding register has been read. Figure 17 Interrupt Request Sources (Part 3) Table 7 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 ...
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Fail Save Mechanisms The C540U/C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 256 approx. 0.55 s ...
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Oscillator Watchdog The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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EWPD WS (PCON1.7) (PCON1.4) Activity on USB Bus Control P3.2 / INT0 Logic Start / Stop RC f Oscillator RC 3 MHz Start / XTAL1 Stop On-Chip XTAL2 Oscillator Figure 19 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group ...
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Power Saving Modes The C540U/C541U provides two basic power saving modes, the idle mode and the power down mode. – Idle mode In the idle mode the main oscillator of the C540U/C541U continues to run, but the CPU is gated ...
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OTP Memory Operation The C540U/C541U contains a 8k byte one-time programmable (OTP) program memory (C540U : 4k byte). With the C540U/C541U fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be ...
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Pin Configuration in Programming Mode N. RESET PMSEL0 N.C: PMSEL1 PSEL PRD PALE GND Figure 21 P-LCC-44 Pin Configuration of the C540U/C541U in Programming Mode (Top View) Semiconductor Group ...
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PMSEL0 Figure 22 P-SDIP-52 Pin Configuration of the C540U/C541U in Programming Mode (Top View) Semiconductor Group N.C. 1 N.C. 2 N.C. 3 N.C. 4 N.C. 5 N.C. 6 N.C. 7 N. ...
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The following table 9 contains the functional description of all C517A-2E pins which are required for OTP memory programming. Table 9 Pin Definitions and Functions in Programming Mode Symbol Pin Numbers P-LCC-44 P-SDIP-52 RESET 10 12 PMSEL0 11 13 PMSEL1 ...
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Table 9 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Numbers P-LCC-44 P-SDIP-52 XTAL1 21 24 A0/ PSEN 32 38 PROG ...
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Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 23 Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE During this Period Signals are not actively driven ...
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... EA is sampled and latched on reset. An OTP memory read operation is only possible using the OTP verification mode for protection level 1. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using OTP verification mode is disabled. Same as level 2 ...
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Absolute Maximum Ratings Ambient temperature under bias ( Storage temperature ( T ) .......................................................................... – 150 C stg V Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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DC Characteristics V = 4.0V to 5.5V (5V +10%, -20%); CC Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, RESET) Input high voltage to XTAL1 Input high voltage ...
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... XTAL1 driven with CLCH CHCL EA = RESET = Port 0 = Port would be slightly higher if a crystal oscillator is used (appr (idle mode) is measured with all output pins disconnected and with all peripherals disabled; CC XTAL1 driven with CLCH CHCL RESET = ; Port Overload conditions occur if the standard operating conditions are exceeded, ie ...
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AC Characteristics V = 4.0V to 5.5V (5V +10%, -20%); for port 0, ALE and PSEN outputs = 100 pF; L Program Memory Characteristics Parameter ALE pulse width Address setup to ALE Address hold after ALE ALE ...
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AC Characteristics (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data ...
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AC Characteristics (cont’d) External Clock Drive Characteristics Parameter Symbol Oscillator period CLP High time TCL Low time TCL t Rise time t Fall time Oscillator duty cycle DC Clock cycle TCL SSC Interface Characteristics Parameter Clock Cycle Time : Master ...
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ALE PSEN Port 0 Port 2 Figure 24 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 51 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 25 Data Memory Read Cycle Semiconductor Group t LLDV t t LLWL RLRH t RLDV t LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 26 Data Memory Write Cycle TCL XTAL1 Figure 27 External Clock Drive on XTAL1 Semiconductor Group t t LLWL WLWH ...
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SCLK t SCL SCLK t D STO SRI MSB TC Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and ...
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SCLK (CPOL = 1) SCLK (CPOL = 0) SLS t STO (CPHA = 0) STO (CPHA = 1) Figure 29 SSC Slave Mode Timing Semiconductor Group t SCLK DOUT DOUT 7 55 ...
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AC Characteristics of Programming Mode 11 Parameter ALE pulse width PMSEL setup to ALE rising edge Address setup to ALE, PROG, or PRD falling edge Address hold after ALE, ...
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PAW PALE t PMS PMSEL1,0 t A8-A13 Port 2 Port 0 PROG Figure 30 Programming Code Byte - Write Cycle Timing Semiconductor Group PAS PAH t t PCS 57 A0-A7 D0-D7 t PWH t PWW PCH ...
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PAW PALE t PMS PMSEL1,0 t Port 2 Port 0 PRD Notes: PROG must be high during a programming read cycle. Figure 31 Verify Code Byte - Read Cycle Timing Semiconductor Group PAS PAH A8-13 t ...
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PMSEL1,0 Port 0 t PMS PROG PRD Note: PALE should be low during a lock bit read / write cycle. Figure 32 Lock Bit Access Timing PMSEL1,0 Port 2 Port 0 PRD Note: Figure 33 Version Byte Read Timing Semiconductor ...
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OTP Verification Characteristics OTP Verification Mode for Protection Level 1 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 34 OTP Verification Mode ...
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USB Transceiver Characteristics V = 4.0V to 5.5V (5V +10%, -20%); CC Parameter Output impedance (high state) Output impedance (low state) Input leakage current Tristate output off-state current Crossover point Notes : 1) This value includes an external resistor of ...
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Inputs during testing are driven at Timing measurements are made at Figure 35 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port ...
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Crystal Oscillator Mode MHz C Crystal Mode Figure 38 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group Driving from External Source N.C. XTAL2 External Oscillator Signal XTAL1 (Incl. Stray Capacitance) ...
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Plastic Package, P-LCC-44-1 (SMD) (Plastic Leaded Chip Carrier Package) Figure 39 P-LCC-44-1 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 64 C540U ...
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Plastic Package, P-SDIP-52-1 (Plastic Shrink Dual In-Line Package) Figure 40 P-SDIP-52-1 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Semiconductor Group 65 C540U C541U Dimensions in mm 1997-10-01 ...