SAB-C517A-LM Infineon Technologies AG, SAB-C517A-LM Datasheet
SAB-C517A-LM
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SAB-C517A-LM Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C517A Data Sheet 10.97 ...
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C517A Data Sheet Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Edition 10.97 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All ...
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... CMOS Microcontroller Advance Information • Full upward compatibility with SAB 80C517A/83C517A-5 • MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation • Superset of the 8051 architecture with 8 datapointers • On-chip emulation support logic (Enhanced Hooks Technology • ...
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... P-MQFP-100 packages • Temperature Ranges: SAB-C517A SAF-C517A SAH-C517A Table 1 Ordering Information Type Ordering Code SAB-C517A-4RM Q67120-DXXXX SAF-C517A-4RM Q67120-DXXXX SAB-C517A-4R24M Q67120-DXXXX SAF-C517A-4R24M Q67120-DXXXX SAB-C517A-LM Q67127-C1071 SAF-C517A-LM Q67127-C1063 SAB-C517A-L24M Q67127-C1072 Semiconductor Group - -40 to 110 C A Package ...
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Note: Versions for extended temperature ranges – 110 C (SAH-C517A) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer. Port 7 8-bit Analog/ Digital Input ...
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CC4/INT2/P1.4 2 N.C. 3 N.C. 4 N.C. 5 N.C. 6 CC3/INT6/P1.3 7 CC2/INT5/P1.2 8 CC1/INT4/P1.1 9 CC0/INT3/P1 XTAL2 13 XTAL1 14 P2.0/A8 15 P2.1/A9 16 P2.2/A10 17 P2.3/A11 18 P2.4/A12 19 P2.5/A13 ...
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Table 2 Pin Definitions and Functions Symbol Pin Number P-MQFP-100 P1 100 - 100 10 11 Input ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-100 XTAL2 12 XTAL1 13 P2 PSEN 22 ALE Input O = Output Semiconductor Group I/O*) Function – XTAL2 is the ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-100 EA 24 P0.0 - P0.7 26, 27 HWPD 36 P5 Input O = Output Semiconductor Group I/O*) Function ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-100 OWE 45 P6 P8 Input O = Output ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-100 P4 PE/SWD 67 RESET AREF V 79 AGND P7 Input ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-100 P3 25, 28, 29, 32, 43 ...
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Oscillator Watchdog XTAL1 OSC & Timing XTAL2 ALE PSEN 8 Datapointer EA PE/SWD Programmable Watchdog Timer RESET HWPD Timer 0 RO OWE Timer 1 Compare Unit Compare Timer Serial Channel 0 Programmable Baud Rate Generator Serial Channel 1 Programmable Baud ...
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CPU The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C517A CPU manipulates operands in the following five address spaces: – Kbyte of program memory (32K on-chip program memory for C517A-4R) – Kbyte of external data memory – 256 bytes of ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator ...
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Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation. Crystal Oscillator Mode C 3 MHz C Crystal Mode: Figure 7 Recommended Oscillator Circuitries Semiconductor Group Driving from External Source N.C. XTAL1 External Oscillator Signal ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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... SFRs with addresses where address bits 0-2 are 0 (e. … are bitaddressable. The SFRs of the C517A are listed in table 3 and table 4. In table 3 they are organized in groups which refer to the functional blocks of the C517A. Table 4 illustrates the contents of the SFRs in numeric order of their addresses ...
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... TL1 Timer 1, Low Byte TMOD Timer Mode Register 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ‘X’ means that the value is undefined and the location is reserved Semiconductor Group Address Contents after ...
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... Timer 2 Control Register IRCON0 2) Interrupt Request Control Register 0 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ‘X’ means that the value is undefined and the location is reserved Semiconductor Group ...
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... Pow. Sav. PCON 2) Power Control Register Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ‘X’ means that the value is undefined and the location is reserved. Semiconductor Group Address Contents after ...
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... COMSETL COMSETH COMCLRL ‘X’ means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit ...
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... C6 H CCL3 CCH3 T2CON 00 H T2PS C9 H CC4EN ‘X’ means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit ...
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... E0 H ACC CTCON 0X00. T2PS1 – 0000 CML3 ‘X’ means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit ...
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... CMEN CMSEL CCM7 ‘X’ means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit ...
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... If a digital value read, the voltage levels are to be held within the input voltage specifications Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same IL IH time by byte instructions. Nevertheless possible to use port 7 and 8 simultaneously for analog and digital input. However, care must be taken that all bits of P7 and P8 that have an undetermined value caused by their analog function are masked ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 5: Table 5 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 1 ...
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Compare / Capture Unit (CCU) The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. The ...
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The main functional blocks of the CCU are: – Timer 2 with f /12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and OSC overflow interrupt request. f – Compare timer with OSC request. – Compare/(reload/) capture register array ...
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Timer 2 Operation Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. Gated Timer Mode: In gated ...
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Compare Timer Operation The compare timer receives its input clock from a programmable prescaler which provides input f frequencies, ranging from OSC 16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register. The compare ...
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Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches ...
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Compare Register Circuit Compare Reg. 16 Bit Comparator Compare 16 Bit Match Timer Register Timer Circuit Figure 14 Compare Function in Compare Mode 1 Compare Mode 2 In the compare mode 2 the port 5 pins are under control of ...
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Multiplication / Division Unit (MDU) This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are unsigned integer operations. Table 7 describes the five general operations the MDU ...
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For starting an operation, registers MD0 to MD5 and ARCON must be written certain sequence according table 8 and 9. The order the registers are accessed determines the type of the operation. A shift operation is started ...
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Serial Interfaces 0 and 1 The C517A has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit and receive simultaneously. The serial channel 0 is completely ...
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For clarification some terms regarding the difference between “baud rate clock” and “baud rate” should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the ...
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Table 11 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with its dependencies of the control bits BD and SMOD. Table 11 Serial Interfaces - Baud Rate Dependencies Serial Interface Active Control Operating ...
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A/D Converter The C517A provides an A/D converter with the following features: – 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs – 10-bit resolution – Single or continuous conversion mode – Internal ...
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IEN1 ( EXEN2 IRCON0 ( EXF2 P7.7 ADCON1 ( ADCL ADCON0 ( Port 7 Port 8 Clock f /2 OSC Prescaler ÷8, ÷4 ...
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Interrupt System The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D converter, and serial interface 0 and 1) and ...
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... P3.2/ INT0 IT0 TCON.0 RI1 S1CON.0 UART 1 TI1 S1CON.1 A/D Converter Timer 0 Overflow P1.4/ INT2/ CC4 I2FR T2CON.5 Bit addressable Request Flag is cleared by hardware Figure 20 Interrupt Structure, Overview (Part 1) Semiconductor Group IE0 0003 EX0 H TCON.1 IEN0.0 < 0083 H ES1 IEN2.0 IADC 0043 EADC H IRCON0.0 IEN1 ...
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... P3.3/ INT1 IT1 TCON.2 Match in CM0-CM7 P1.0/ INT3/ CC0 I3FR T2CON.5 Timer 1 Overflow Compare Timer Overflow P1.1/ INT4/ CC1 Bit addressable Request Flag is cleared by hardware Figure 21 Interrupt Structure, Overview (Part 2) Semiconductor Group IE1 0013 EX1 H TCON.3 IEN0.2 ICMP0-7 0093 H ECMP IRCON1.0-7 IEN2.2 IEX3 0053 H EX3 IRCON0 ...
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... S0CON.1 Match in COMSET P1.2/ INT5/ CC2 Timer 2 TF2 Overflow IRCON0.6 P1.5/ EXF2 T2EX EXEN2 IRCON0.7 IEN1.7 Match in COMCLR P1.3/ INT6/ CC3 Bit addressable Request Flag is cleared by hardware Figure 22 Interrupt Structure, Overview (Part 3) Semiconductor Group < 0023 ES0 H IEN0.4 ICS 00A3 H ECS CTCON.4 IEN2.4 IEX5 ...
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Table 12 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel 0 Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 ...
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Fail Save Mechanisms The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 512 approx. 1 ...
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Oscillator Watchdog The oscillator watchdog unit serves for four functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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Power Saving Modes The C517A provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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Table 13 Power Saving Modes Overview Mode Entering 2-Instruction Example Idle mode ORL PCON, #01H ORL PCON, #20H Slow Down Mode In normal mode: ORL PCON,#10H With idle mode: ORL PCON,#01H ORL PCON, #30H Software ORL PCON, #02H Power Down ...
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Absolute Maximum Ratings Ambient temperature under bias ( T Storage temperature ( ) .......................................................................... – 150 C stg V Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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... OH1 0 – – – – 10 IL2 I – IL3 I – IL4 C – – for the SAB-C517A for the SAF-C517A for the SAH-C517A Unit Test Condition max. V 0.2 – 0.1 V – CC 0.2 V – 0.3 V – 0.1 V – 0.5 V – 0.5 V – ...
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... CLCH CHCL PE/SWD == ; Port 0 = Port 7 = Port disconnected (idle mode) is measured with all output pins disconnected and with all peripherals disabled; CC XTAL2 driven with CLCH CHCL RESET = V ; HWPD = Port 0 = Port 7 = Port all other pins are disconnected; ...
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3.5 Figure 25 ICC Diagram Table 14 Power Supply Current Calculation Formulas Parameter Symbol Active mode I CC typ I CC max I Idle mode CC typ I CC max I Active ...
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... ADC S ADCC min = 500 OSC CLCL 55 for the SAB-C517A for the SAF-C517A for the SAH-C517A Unit Test Condition Prescaler 8 2) Prescaler 4 ns Prescaler 8 3) Prescaler 4 LSB V +0 ...
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Notes may exceed AIN AGND these cases will be X000 or X3FF H 2) During the sample time the input capacitance C internal resistance of the analog source must allow the capacitance to reach their ...
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... PXIX t *) – 46 PXIZ – PXAV t – 180 AVIV t 0 – AZPL 57 C517A for the SAB-C517A for the SAF-C517A for the SAH-C517A Limit Values Variable Clock 3.5 MHz to 18 MHz CLCL min. max – 40 – CLCL t – 30 – CLCL t – 30 – ...
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AC Characteristics (18 MHz, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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... PXIX t *) – 32 PXIZ – PXAV t – 148 AVIV t 0 – AZPL 59 C517A for the SAB-C517A for the SAF-C517A for the SAH-C517A Limit Values Variable Clock 3.5 MHz to 24 MHz CLCL min. max – 40 – CLCL t – 25 – CLCL t – 25 – ...
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AC Characteristics (24 MHz, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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ALE PSEN Port 0 Port 2 Figure 26 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 61 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 27 Data Memory Read Cycle Semiconductor Group t LLDV t t LLWL RLRH t RLDV LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL t LLAX2 from Port DPL t AVWL Port 2 Figure 28 Data Memory Write Cycle V - 0.5V CC 0 0.1 0.45V Figure 29 External ...
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ROM Verification Characteristics for the C517A-1RM ROM Verification Mode 1 Parameter Address to valid data P1.0-P1.7 P2.0-P2.6 Port 0 Data: Addresses: Figure 30 ROM Verification Mode 1 Semiconductor Group Symbol min. t – AVQV Address t AVQV Data Out P0.0-P0.7 ...
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ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 31 ROM Verification Mode 2 Semiconductor Group Symbol min. t ...
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Inputs during testing are driven at Timing measurements are made at Figure 32 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port ...
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Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) Figure 35 P-MQFP-100-2 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 67 C517A ...