PEB22320N Infineon Technologies AG, PEB22320N Datasheet

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PEB22320N

Manufacturer Part Number
PEB22320N
Description
Primary rate access clock generator and transceiver
Manufacturer
Infineon Technologies AG
Datasheet
ICs for Communications
Primary Rate Access Clock Generator and Transceiver
PRACT
PEB 22320
Version 2.1
Data Sheet 04.95

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PEB22320N Summary of contents

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ICs for Communications Primary Rate Access Clock Generator and Transceiver PRACT PEB 22320 Version 2.1 Data Sheet 04.95 ...

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PEB 22320 Revision History Current Version: 04.95 Previous Version: 05.93 Page Subjects (changes since last revision) 10 Architecture of the PRACT 14 Input Jitter Specification 16 Jitter Attenuator Block Diagram 17 Clock- and Synchronization Table 18 Jitter Attenuation Characteristics 23 ...

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Table of Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Primary Rate Access Clock Generator and Transceiver PRACT Preliminary Data 1 Features • ISDN line interface for 1544 and 2048 kbit/s (T1 and CEPT) • Data and clock recovery • Transparent to ternary codes • Low transmitter output impedance for ...

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Specially designed line interface circuits simplify the tedious task of protecting the device against overvoltage damage while still meeting the return loss requirements. The PRACT is suitable for use in a wide range of voice and data applications such as ...

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Pin Configuration (top view) FSC LS0 XTAL4 XTAL3 LS1 XTAL2 XTAL1 LS2 CLK16M CLK12M SYNC Semiconductor Group PRACT 12 PEB 22320 13 14 ...

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Pin Definitions and Functions Pin Definitions and Functions Pin No. Symbol Input (I) Output ( DD2 2 RL2 CLK4M O 5 CLK4M O 6 FSC O 7 FSC O 8 LS0 ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output ( MODE I 28 XTIN I 29 XTIP I 30 XDIN I 31 XDIP I 32 XCLK I DDD ...

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System Integration Figure 1 shows the architecture of a primary access board for data transmission. It exhibits the following functions: – Line Interface (PEB 22320, PRACT) – Clock and Data Recovery (PEB 22320, PRACT) – Jitter Attenuation (PEB 22320, ...

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Functional Description LL RL1 Receive Receiver Input RL2 XL1 Driver Transmit Output XL2 Figure 2 Functional Block Diagram of the PRACT Semiconductor Group XTAL1 RRCLK Clock & P Data Recovery N Jitter Attenuator & Clock Generator ...

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Receiver 2.1.1 Basic Functionality The receiver recovers data from the ternary coded signal at the ternary interface and outputs unipolar signals at the dual rail interface. One of the lines carries the positive pulses, the other ...

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The receiver is transparent to the logical 1’s polarity and outputs positive logical 1’s on RDOP and negative logical 1’s on RDON. RDON and RDOP are active low and fully bauded. The comparator threshold to detect logical 1’s and logical ...

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Input Jitter Tolerance The PRACT receiver’s tolerance to input jitter complies to CCITT and Bellcore requirements for CEPT and T1 application. Figure 5 shows the curves of the different input jitter specifications stated above as well as the PRACT ...

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Table 2 Jitter Input Tolerance Frequency Hz CCITT G.823 1 2 1.5 192.9 500 2400 1.5 6430 8000 10000 18000 0.2 20000 25000 40000 50000 100000 2.1.4 Jitter Attenuator and Clock Generator The jitter attenuator reduces wander and ...

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The jitter attenuator meets the jitter transfer requirements of the Bellcore TR-NWT 000 499 and Rec. I.431 (refer to figure 7 and table 4). The amount of generated output jitter when no input jitter is shown in table 5. JATT ...

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Table 3 Clock and Synchronization Table Semiconductor Group Functional Description 17 PEB 22320 ...

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CCITT G.735 CCITT I.431 TR-NWT -50 Cat I to PRACT CEPT PRACT T1 -60 0.1 1 Figure 7 Jitter Attenuation Characteristics Table 4 Jitter Transfer Characteristics Frequency CCITT G. 735 Hz CCITT I.431 ...

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Table 4 Jitter Transfer Characteristics (cont’d) Frequency CCITT G. 735 Hz CCITT I.431 200 250 300 350 400 – 19.50 9650 1000 1412 2500 3000 10000 15000 – 19.50 Table 5 Generated Output Jitter Specification Lower Cutoff 20 Hz I.431 ...

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Transmitter 2.2.1 Basic Functionality The transmitter transforms unipolar data to ternary (alternate bipolar) return to zero signals of the appropriate shape. The unipolar data is provided at XDIP (positive pulses) and XDIN (negative pulses), synchronously with the transmit clock ...

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The pulse shape according to CCIT G.703 (1544-kbit/s interface) is achieved by using the same line length selection code as for the lowest T1 cable range. To switch the device into a low power dissipation mode, XDIP and XDIN should ...

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Output Jitter In the absence of any input jitter the PRACT generates the output jitter, which is specified in table 5. Note: The generated output jitter on the line is the same as the output jitter of the system ...

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Master/Slave Selection If the MODE pin is set to high and the SYNC pin is not connected or connected to PRACT works as a master for the system. The VCO’s of the jitter attenuator are centered ( 50 ppm ...

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Operational Description 3.1 Reset After power up resetting the device is necessary to synchronize the internal circuitries. After reset a stabel RCLK is available after 65536 clock cycles. This results CEPT mode and 42.5 ms ...

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Figure 10 Resetting PRACT for CEPT Applications and Setting Local Loop with Jitter Attenuation Figure 11 Resetting PRACT for T1 Applications (max. line length selected) and Setting Remote Loop Note: If the PRACT is initiated for T1 applications the line ...

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Reset Using CS Pin to Latch Programming (a controller is used) Reset is done by setting the pins RL and LL to logical 1 for at least 1 s and latching these values into PRACT by a rising edge ...

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xxx LS0 Start of Reset 2. End of Reset and setting line length code, Regular operation in T1 Mode 3. Changing line length code, Regular operation in T1 Mode with changed line length code ...

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Electrical Specification 4.1 Absolute Maximum Ratings Parameter Voltage on any pin with respect to ground Ambient temperature under bias Storage temperature 4.2 Delay Times 4.2.1 Delay from XDIP/XDIN to XL1/XL2 The delay from XDIP/XDIN to XL1,XL2 is 770 ns ...

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DC Characteristics Characteristics Parameter Symbol V L-input voltage IL V H-input voltage IH L-output voltage H-output voltage OH V H-output voltage OH Input ...

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DC Characteristics (cont’d) Parameter Symbol L-input voltage V XTALIL V H-input voltage XTALIH I Input leakage XTALI current I Operational CC power supply current V L-input voltage IL V H-input voltage IH I Input leakage LI1 I current LI2 I ...

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Recommended Oscillator Circuits XTAL1 (XTAL3) PRACT XTAL2 (XTAL4) Crystal Oscillator mode (slave mode/ master mode) Figure 16 Oscillator Circuits In CEPT mode if an external source is connected to XTAL1, the PRACT works, independent of the MODE pin, in ...

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PRACT Tuning Range 16.384 MHz PLL Crystal specified for C L 150 ppm 100 50 0 -50 -100 -150 14 16 Figure 17 16.384-MHz Crystal Tuning Range Semiconductor Group = PEB ...

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PRACT Tuning Range 12.352 MHz PLL Crystal specified for C L 250 ppm d f 200 f 0 150 100 50 0 -50 -100 -150 -200 -250 6 8 Figure 18 12.352-MHz Crystal Tuning Range Semiconductor Group = 10 pF ...

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AC Characteristics 2.4 2.0 Test Points 0.8 0.45 Figure 19 Input/Output Waveforms for AC Tests Except from the line interface, inputs are driven at 2.4 V for ...

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Parameter RCLK clock period RCLK clock period low RCLK clock period high Dual rail output setup Dual rail output hold XCLK clock period XCLK clock period low XCLK clock period high Dual rail input setup Dual rail input hold Semiconductor ...

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System Clock Interface t CP16L CLK16M CLK4M CLK4M CLK2M CLK2M FSC FSC t CP12L CLK12M XCLK (T1) Figure 21 Timing of the System Clock Interface Semiconductor Group t CP16 t CP16H t CP4 t t CP4L CP4H t CP2 ...

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System Clock Interface Timing Parameter Values Parameter CLK16M period 16 MHz CLK16M period 16 MHz low CLK16M period 16 MHz high CLK4M period 4 MHz CLK4M period 4 MHz low CLK4M period 4 MHz high CLK2M period 2 MHz CLK2M ...

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Microprocessor Interface DATA (JATT, RL, LL, LS0, 1, Figure 22 Timing of the Microprocessor Interface Parameter CS pulse width Data setup time to CS Data hold time from CS Cycle time Semiconductor Group ...

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XTAL Timing XTAL1 XTAL3 Figure 23 Timing of XTAL1/XTAL3 XTAL1/XTAL3 Timing Parameter Values Parameter Clock period of crystal/ clock High phase crystal/clock Low phase of crystal/clock Note external clock is used the PRACT works as a master. ...

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Pulse Templates - Transmitter The PRACT meets both CCITT and T1 pulse template requirements. V=100 % Figure 24 Pulse Template at the Transmitter Output for CEPT Applications Semiconductor Group Electrical Specification 269 ns (244 + ...

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V = 100 -50 % Figure 25 T1 Pulse Shape at the Cross Connect Point Table 8 T1 Pulse Template Corner Points at the Cross Connect Point Maximum Curve (0 0.05) (250, 0.05) (325, 0.80) (325, 1.15) (425, 1.15) (500, ...

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Figure 26 Pulse Shape According to CCITT G.703 4.8 Overvoltage Tolerance To prevent the PRACT from being damaged by overvoltage (i.e. from lightning), external devices like diodes or resistors have ...

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Condition: All other pins grounded Figure 27 Measurement of Overvoltage Stress Figure 28 Tolerated Input Current at the XL1, XL2 Pins Semiconductor Group 100 10 dB/Decade 50 < ...

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Figure 29 Tolerated Input Current at the RL1, RL2 Pins Semiconductor Group dB/Decade 10 R < _ 300 - PEB 22320 ...

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Package Outlines Plastic Package, P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 45 PEB 22320 Package Outlines ...

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