SAB-C505CA-4EM Infineon Technologies AG, SAB-C505CA-4EM Datasheet
SAB-C505CA-4EM
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SAB-C505CA-4EM Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C505 C505C/C505A C505CA Data Sheet 12.97 ...
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Edition 12.97 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for ...
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CMOS Microcontroller Advance Information • Fully compatible to standard 8051 microcontroller • Superset of the 8051 architecture with 8 datapointers • MHz operating frequency – 375 ns instruction cycle time @16 MHz – 300 ns instruction ...
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... Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin • P-MQFP-44 package • Pin configuration is compatible to C501, C504, C511/C513-family • Temperature ranges: SAB-C505 versions SAF-C505 versions SAH-C505 versions SAK-C505 versions Table 1 ...
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... Q67127-C2060 SAF-C505A-4EM Q67127-C2061 SAB-C505CA-4EM Q67127-C1082 SAB-C505CA-4EM Q67127-C2058 Note: The ordering number of the ROM types (DXXXX extension) is defined after program release (verification) of the customer. Versions for the extended temperature range – 110 C (SAH-C505) and – 125 C (SAK-C505) are available on request. ...
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V AREF V AGND XTAL1 XTAL2 RESET EA ALE PSEN Figure 2 Logic Symbol Additional Literature For further information about the C505/C505C/C505A/C505CA the following literature is available: Title C505 8-Bit CMOS Microcontroller User’s Manual C500 Microcontroller Family Architecture and Instruction ...
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P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V AGND P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 ...
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Table 3 Pin Definitions and Functions Symbol Pin Number P1.0-P1.7 40-44,1 Input O = Output Semiconductor Group I/O Function *) I/O Port 8-bit quasi-bidirectional port with ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number RESET 4 P3.0-P3 Input O = Output Semiconductor Group I/O Function *) I RESET A high level ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number P4.0 6 P4.1 28 XTAL2 14 XTAL1 Input O = Output Semiconductor Group I/O Function *) I/O Port 4 I 2-bit quasi-bidirectional port with ...
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... It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal ROM or OTP (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation. 11 C505 / C505C ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number EA 29 P0.0-P0.7 37- AREF V 39 AGND Input O = Output Semiconductor Group I/O Function *) I External ...
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V CC Oscillator Watchdog V SS XTAL1 OSC & Timing XTAL2 RESET CPU 8 Datapointers ALE PSEN Programmable Watchdog Timer EA Timer 0 Timer 1 Timer 2 USART Baudrate Generator Full-CAN Controller Interrupt Unit Converter AREF ...
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CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C505 CPU manipulates operands in the following four address spaces: – On-chip program memory : – Totally Kbyte internal/external program memory – Kbyte of external data memory – 256 bytes of ...
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Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator ...
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Figure 7 shows the recommended oscillator circuits for crystal and external clock operation. External Clock Signal Figure 7 Recommended Oscillator Circuitries Semiconductor Group C XTAL2 MHz C505CA C XTAL1 for crystal ...
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Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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... RMAP must be cleared/set respectively by software. All SFRs with addresses where address bits 0-2 are 0 (e. ..., are bitaddressable. The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505 are listed in table 4 and table 5 ...
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... Page Address Register for Extended on-chip XRAM and CAN Controller SYSCON 2) System Control Register 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR ...
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... Power Control Register Modes PCON1 4) Power Control Register 1 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. ...
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... DB7n Message Data Byte 7 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “ ...
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... IP0 SRELL means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group Bit 7 Bit 6 Bit 5 Bit 4 ...
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... D0 H PSW ADCON0 00X0- 0000 ADDAT means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) C505 / C505A only 4) C505C / C505CA only Semiconductor Group Bit 7 Bit 6 Bit 5 Bit – – ...
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... means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual of the step C505 (eg. 01 ...
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Table 6 Contents of the CAN Registers in numeric order of their addresses (C505C/C505CA only) Addr. Register Content n=1-F H after 2) 1) Reset F700 F701 F702 F704 ...
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Table 6 Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505C/C505CA only) Addr. Register Content n=1-F H after 2) 1) Reset F7n7 H DB0n XX H F7n8 H DB1n XX H F7n9 H DB2n XX H ...
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... The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of a specific port 1 pin is enabled by bits in the SFR P1ANA ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 7 : Table 7 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler ...
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Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C505 provides additional compare/capture/reload features. which allow the selection of the following operating modes: – Compare : PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock) – ...
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag ...
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the ...
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 8. Table 8 USART Operating Modes SCON Mode SM0 SM1 ...
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Timer 1 Overflow Baud Rate Generator f OSC (SRELH SRELL) ÷ 6 Note: The switch configuration shows the reset state. Figure 14 Block Diagram of Baud Rate Generation for the Serial Interface Table 9 below lists the values/formulas for the ...
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CAN Controller (C505C and C505CA only) The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol ...
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The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from ...
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... CAN Controller Software Initialization The very first step of the initialization is the CAN controller input clock selection. A divide-by-2 prescaler is enabled by default after reset (figure 16). Setting bit CMOD (SYSCON.3) disables the prescaler. The purpose of the prescaler selection is: – to ensure that the CAN controller is operable when – ...
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A/D Converter (C505 and C505C only) The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and provides the following features: – 8 multiplexed ...
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IEN1 ( EXEN2 SWDT IRCON ( EXF2 TF2 P1ANA ( EAN7 EAN6 ADCON1 ( ADCL1 ADCL0 ADCON0 ( CLK Port 1 MUX Conversion f OSC Clock Prescaler V AREF ...
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A/D Converter (C505A and C505CA only) The C505 includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation ...
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IEN1 ( EXEN2 SWDT IRCON ( EXF2 TF2 P1ANA ( EAN7 EAN6 ADCON1 ( ADCL1 ADCL0 ADCON0 ( CLK Port 1 MUX Conversion f OSC Clock Prescaler V AREF ...
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Interrupt System The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One interrupt can be generated by the CAN ...
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... Transmit >1 TXIE MCR0 Message Receive RXIE MCR0 Bit addressable Request flag is cleared by hardware Figure 21 Interrupt Structure, Overview Part 1 Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the shaded area of Figure 21 provides the bits/flags. Semiconductor Group IE0 0003 H TCON ...
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... P3.3 / INT1 IT1 TCON.2 P1.0 / AN0 / INT3 / CC0 I3FR T2CON.6 Timer 1 Overflow P1.1 / AN1 / INT4 / CC1 Bit addressable Request flag is cleared by hardware Figure 22 Interrupt Structure, Overview Part 2 Semiconductor Group IE1 0013 H TCON.3 EX1 IEN0.2 IEX3 0053 H EX3 IRCON.2 IEN1.2 IP1.2 TF1 001B H TCON.7 ET1 IEN0 ...
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... USART TI SCON.1 P1.2 / AN2 / INT5 / CC2 Timer 2 TF2 Overflow IRCON.6 P1.5 / AN5 / EXF2 T2EX IRCON.7 EXEN2 IEN1.7 P1.3 / INT6 / CC3 Bit addressable Request flag is cleared by hardware Figure 23 Interrupt Structure, Overview Part 3 Semiconductor Group >1 0023 H ES IEN0.4 IEX5 0063 H IRCON.4 EX5 IEN1.4 IP1.4 >1 002B H ET2 IEN0 ...
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Fail Save Mechanisms The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 192 approx. 412.5 ms ...
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Oscillator Watchdog The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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EWPD WS (PCON1.7) (PCON1.4) P4.1 / RXDC Control P3.2 / INT0 Logic Start / Stop RC f Oscillator RC 3 MHz Start / XTAL1 Stop On-Chip XTAL2 Oscillator Figure 25 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group Power ...
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Power Saving Modes The C505 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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OTP Memory Operation (C505A and C505CA only) The C505A/C505CA contains a 32k byte one-time programmable (OTP) program memory. With the C505A/C505CA fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be ...
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Pin Configuration in Programming Mode N.C. N.C. N.C. N.C. N.C. N.C. N.C. Figure 27 P-MQFP-44 Pin Configuration of the C505A/C505CA in Programming Mode (Top View) Semiconductor Group ...
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The following table 12 contains the functional description of all C505A/C505CA pins which are required for OTP memory programming. Table 12 Pin Definitions and Functions in Programming Mode Symbol Pin Number I/O RESET 4 PMSEL0 5 PMSEL1 7 PSEL 8 ...
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Table 12 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Number I/O P2.0-7 18-25 PSEN 26 PROG 27 EA D7-0 30-37 N.C. 1-3, 6, 11-13, 28, 38- Input O = Output Semiconductor Group ...
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Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 28 Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE During this period signals are not actively driven ...
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... Protection Type The OTP lock feature is disabled. During normal operation of the C505A/C505CA, the state of the EA pin is not latched on reset. During normal operation of the C505A/C505CA, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory sampled and latched on reset ...
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Absolute Maximum Ratings Ambient temperature under bias ( Storage temperature ( T ) .......................................................................... – 150 C stg V Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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... Overload current Programming voltage V Supply current at EA/ CC Notes see next but one page 61 Semiconductor Group for the SAB- versions – for the SAF- versions – 110 C for the SAH- versions – 125 C for the SAK- versions ...
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Power Supply Currents Parameter C505 / Active Mode C505C Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled Power down current C505A Active Mode C505CA Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled ...
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... CC t XTAL1 driven with , ns, 50% duty cycle , Port 0 = RESET = (idle mode) is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with , ns, 50% duty cycle RESET = Port0 = SS 9) ...
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CC max typ Figure 29 ICC Diagram of C505 and C505C C505/C505C: Power Supply Current Calculation Formulas Parameter Symbol Active mode I CC typ I CC max I Idle ...
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CC max typ Figure 30 ICC Diagram of C505A and C505CA C505A : Power Supply Current Calculation Formulas Parameter Symbol Active mode I CC typ I CC max I ...
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... Further timing conditions : t Semiconductor Group for the SAB- versions – for the SAF- versions – 110 C for the SAH- versions – 125 C for the SAK- versions A V – ...
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Notes may exeed V or AIN AGND these cases will During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach their final voltage ...
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... Further timing conditions : t Semiconductor Group for the SAB- versions – for the SAF- versions – 110 C for the SAH- versions – 125 C for the SAK- versions A V – ...
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Notes may exeed V or AIN AGND these cases will be X000 or X3FF H 2) During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach their final voltage ...
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... Interfacing the C505 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group for the SAB- versions – for the SAF- versions – 110 C for the SAH- versions ...
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AC Characteristics (12 MHz, 0.5 Duty Cycle, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data ...
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... Interfacing the C505 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group for the SAB- versions for the SAF- versions A C for all other outputs = 80 pF) ...
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AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to ...
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AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d) External Clock Drive Characteristics Parameter Symbol Oscillator period CLP High time TCL Low time TCL t Rise time t Fall time Oscillator duty cycle DC Clock cycle TCL Note: The ...
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... Interfacing the C505 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group for the SAB- versions – for the SAF- versions A C for all other outputs = 80 pF) ...
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AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data ...
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ALE PSEN Port 0 Port 2 Figure 31 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 75 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 32 Data Memory Read Cycle Semiconductor Group t LLDV t t LLWL RLRH t RLDV t LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 33 Data Memory Write Cycle TCL XTAL1 Figure 34 External Clock Drive on XTAL1 Semiconductor Group t t LLWL WLWH t ...
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AC Characteristics of Programming Mode (C505A and C505CA only 11 Parameter ALE pulse width PMSEL setup to ALE rising edge Address setup to ALE, PROG, or PRD falling edge ...
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PAW PALE t PMS PMSEL1,0 t A8-A14 Port 2 Port 0 PROG Notes: PRD must be high during a programming write cycle. Figure 35 Programming Code Byte - Write Cycle Timing Semiconductor Group PAS PAH t ...
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PAW PALE t PMS PMSEL1,0 t Port 2 Port 0 PRD Notes: PROG must be high during a programming read cycle. Figure 36 Verify Code Byte - Read Cycle Timing Semiconductor Group PAS PAH A8-A14 t ...
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PMSEL1,0 Port 0 t PMS PROG PRD Note: PALE should be low during a lock bit read / write cycle. Figure 37 Lock Bit Access Timing PMSEL1,0 Port 2 Port 0 PRD Note: Figure 38 Version Byte Read Timing Semiconductor ...
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ROM/OTP Verification Characteristics for C505 ROM Verification Mode 1 (C505-2R and C505C-2R only) Parameter Address to valid data P1.0 - P1.7 P2.0 - P2.6 Port 0 Address: P1 Data: Figure 39 ROM Verification Mode ...
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ROM/OTP Verification Characteristics for C505 (cont’d) ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 40 ROM/OTP Verification Mode ...
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Inputs during testing are driven at Timing measurements are made at Figure 41 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port ...
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P-MQFP-44-1 (SMD) (Plastic Metric Quad Flat Package) Figure 44 P-MQFP-44 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 85 C505 / C505C ...