HYB25D512160BE-6 Infineon Technologies AG, HYB25D512160BE-6 Datasheet
HYB25D512160BE-6
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HYB25D512160BE-6 Summary of contents
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... Edition 2004-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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HYB25D512[40/80/16]0B[C/T], HYB25D512[40/80/16]0B[E/F], Revision History: Rev. 1.2 Previous Version: Rev. 1.1 Page Subjects (major changes since last revision) 1 Editorial Change 67 Added AC Timing Table We Listen to Your Comments Any information within this document that you feel is wrong, ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package . . . . . . . . . . . . . 16 Figure 2 Pin Configuration P-TSOPII-66 ...
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Figure 54 Package Outline of P-TFBGA-60-[9/22] (green/non-green Figure 55 ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Double Data Rate SDRAM DDR SDRAM 1 Overview 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data used in capturing data at ...
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Description The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a quad-bank DRAM. The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. ...
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... HYB25D512400BF–5 ×8 HYB25D512800BE–5 ×16 HYB25D512160BE–5 ×4 HYB25D512400BE–6 ×8 HYB25D512800BE–6 ×16 HYB25D512160BE–6 ×4 HYB25D512400BE–7 1) HYB: designator for memory components V 25D: DDR SDRAMs at = 2.5 V DDQ 512: 512-Mbit density 400/800/160: Product variations x4, ×8 and ×16 B: Die revision B ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in Pin#/Buffer# column are explained in in Figure 1 and that of the TSOP package in Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin ...
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Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Data Signals ×4 organization B7, 5 DQ0 I/O D7, 11 DQ1 I/O D3, 56 DQ2 I/O B3, 62 DQ3 I/O Data Strobe ×4 organisation E3, 51 DQS I/O Data ...
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Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Data Strobe ×16 organization E3, 51 UDQS I/O E7, 16 LDQS I/O Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1, 49 ...
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Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type F9, 14, 17, 19 25,43, 50, 53 Table 4 Abbreviations for Pin Type Abbreviation Description ...
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Figure 1 Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package Data Sheet 512Mbit Double Data Rate SDRAM ...
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Figure 2 Pin Configuration P-TSOPII-66-1 Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM Pin Configuration ...
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Table 6 Input/Output Functional Description Symbol Type CK, CK Input CKE Input CS Input RAS, CAS, WE Input DM Input BA0, BA1 Input A0 - A12 Input DQ Input/Output DQS Input/Output N.C. – V Supply DDQ V Supply SSQ V ...
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Block Diagram 512Mbit 128 Mbit ×4 Figure 3 Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM Drivers Read Latch Bank0 Row-Address Latch & Decoder Bank Control Logic Row-Address MUX Refresh Counter Address Register 19 Pin Configuration Receivers Rev. 1.2, 2004-06 ...
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Block Diagram 512Mbit 64 Mbit ×8 Figure 4 Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM Drivers Read Latch Bank0 Row-Address Latch & Decoder Bank Control Logic Row-Address MUX Refresh Counter Address Register 20 Pin Configuration Receivers Rev. 1.2, 2004-06 ...
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Block Diagram 512Mbit 32 Mbit ×16 Figure 5 Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM Drivers Read Latch Bank0 Row-Address Latch & Decoder Bank Control Logic Row-Address MUX Refresh Counter Address Register 21 Pin Configuration Receivers Rev. 1.2, 2004-06 ...
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Functional Description The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mbit Double Data Rate SDRAM is internally configured as a quad-bank DRAM. The 512Mbit Double Data Rate SDRAM uses a ...
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Mode Register Definition The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The ...
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The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is ...
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Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register ...
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Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended ...
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Commands Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to ...
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Auto Pre charge Auto Pre charge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read ...
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Table 8 Truth Table 1a: Commands Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge ...
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Operations 3.5.1 Bank/Row Activation Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, ...
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Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command, as shown on The starting column and bank addresses are provided with the Read command and ...
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CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 BA0, BA1 Figure 9 Read Command Data Sheet 512Mbit Double Data Rate SDRAM HIGH DIS column address BA = ...
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CK CK Command Read Address BA a,COL n DQS Command Read BA a,COL n Address DQS DQ DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements ...
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CK CK Read Command BAa, COL n Address DQS Read Command Address BAa, COL n DQS DQ DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS a-n = data out from bank a, column a-b = data in to bank ...
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CK CK Read Command BA a, COL n Address DQS Read Command Address BA a, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 ...
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Writes Write bursts are initiated with a Write command, as shown in The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is ...
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CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 BA0, BA1 Figure 17 Write Command Data Sheet 512Mbit Double Data Rate SDRAM HIGH DIS column address BA = ...
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CK CK Command BA a, COL b Address DQS Command BA a, COL b Address DQS a-b = data in for bank a, column b. 3 subsequent elements of data in are applied ...
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Write Command Address BAa, COL b DQS Write Command Address BA, COL b DQS a-b = data in for bank a, column b, etc. 3 subsequent elements of data ...
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Write Command Address BAa, COL b DQS a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 ...
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Write Command Address BAa, COL b DQS Write Command Address BAa, COL b t DQS a-b, etc. = data in for bank a, column b, etc. b', etc. = ...
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Write Command Address BAa, COL b DQS Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. 3 subsequent elements of data in ...
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Write Command Address BAa, COL b DQS Command Write BAa, COL b Address DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 ...
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Minimum DQSS, Odd Number of Data (3-bit Write),Interrupting (CAS Latency = 2; Burst Length = Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted ...
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Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied ...
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Write Command Address BA a, COL b DQS Write Command BA a, COL b Address DQS a-b = data in for bank a, column b. 3 subsequent elements of ...
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Write Command Address BA a, COL b DQS Write Command BA a, COL b Address DQS a-b = data in for bank a, column b. An interrupted burst is ...
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Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (Burst Length = Write Command Address BA a, COL b DQS a-b = data in for bank a, column b. An interrupted ...
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Write Command BA a, COL b Address DQS a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is ...
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Pre charge The Pre charge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( issued. ...
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Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as pre charge power-down; if power-down occurs when there is a ...
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Table 10 Truth Table 2: Clock Enable (CKE) Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks ...
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Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not ...
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Table 12 Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active, or ...
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Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking. 9) Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. ...
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Simplified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Write A Figure 33 Simplified State Diagram Data Sheet REFS MRS Idle CKEH Active ACT Power Down CKEH CKEL Row Active Write Write A Read A Write Read ...
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Electrical Characteristics 4.1 Operating Conditions Table 14 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative to SS Voltage on inputs relative Voltage on supply relative Voltage on supply relative to ...
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Electrical Characteristics and DC Operating Conditions Parameter Symbol V Device Supply Voltage DD Device Supply Voltage Output Supply Voltage DDQ V Output Supply Voltage DDQ V Supply Voltage, I/O Supply SS V Voltage SSQ V Input Reference ...
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Normal Strength Pull-down and Pull-up Characteristics The nominal pull-down - curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the V inner bounding lines of the 2. The full variation in driver ...
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Table 16 Normal Strength Pull-down and Pull-up Currents Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 ...
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Weak Strength Pull-down and Pull-up Characteristics The weak pull-down - curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner V I bounding lines of the - curve ...
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Table 18 Weak Strength Driver Pull-down and Pull-up Characteristics Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating I Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.) DD Note All voltages referenced Tests ...
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AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100 Parameter Clock Half Period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM ...
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AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100 Parameter Address and control input setup time Address and control input hold time Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto- refresh ...
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These parameters are not referred specific voltage level, but specify when the device is no longer driving (HZ), or begins ...
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I Table 20 Specification DD –7 DDR266A Symbol Typ. Max DD0 DD1 90 110 I 1.5 4 DD2P DD2F DD2Q DD3P I 29 ...
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I 5.2.1 Current Measurement Conditions Operating Current: One Bank Operation DD1 1. Only one bank is accessed with I once per clock cycle mA. OUT 2. Timing patterns a) DDR266A (133 MHz 2): ...
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Timing Diagrams DQS Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n. Figure 39 Data Input (Write), Timing Burst Length = 4 DQS DQ ...
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Figure 41 Initialize and Mode Register Sets Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 74 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 42 Power Down Mode Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 75 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 43 Auto Refresh Mode Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 76 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 44 Self Refresh Mode Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 77 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 45 Read without Auto Precharge (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 78 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 46 Read with Auto Pre charge (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 79 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 47 Bank Read Access (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 80 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 48 Write without Auto Precharge (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 81 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 49 Write with Auto Pre charge (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 82 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 50 Bank Write Access (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 83 Timing Diagrams Rev. 1.2, 2004-06 ...
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Figure 51 Write DM Operation (Burst Length = 4) Data Sheet HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM 84 Timing Diagrams Rev. 1.2, 2004-06 ...
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System Characteristics for DDR SDRAMs The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to ensure proper system performance. These characteristics are for system simulation purposes and are guaranteed by design. Table 21 Input ...
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Output Slew Rate Characteristrics (×4, ×8 Devices only) Table 25 Slew Rate Characteristic Typical Range (V/ns) Minumum (V/ns) Pullup Slew Rate 1.2 – 2.5 Pulldown Slew Rate 1.2 – 2.5 1) Pullup slew rate is characterized under the test conditions ...
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The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Table 28 TFBGA Common Package Properties (non-green/green) Description Ball Size Recommended Landing ...
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Basic +0.1 0.35 -0.05 Lead 1 Figure 55 Package Outline of P-TSOPII-66-1 (green/non-green) Data Sheet Gage Plane 0.805 REF 0.1 Seating Plane 22.22 ±0.13 89 HYB25D512[40/16/80]0B[E/F/C/T] 512Mbit Double Data Rate SDRAM Package Outlines 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 ...
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... Published by Infineon Technologies AG ...