CY7C1359A-133AC Cypress Semiconductor Corporation., CY7C1359A-133AC Datasheet
CY7C1359A-133AC
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CY7C1359A-133AC Summary of contents
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... Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Cypress Semiconductor Corporation Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelin- ing Chip Enable (CE), depth-expansion Chip Enables (CE ...
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... DEN# Latch CLK 16 A ADSC# ADV# A1-A0 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 [1] HIGHER BYTE WRITE D Q LOWER BYTE WRITE D Q ENABLE ...
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... CCQ N DQ17 CCQ Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 100-Pin TQFP Top View CY7C1359A/GVT71256T18 119-Lead BGA Top View ADSP CE A ADSC ...
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... Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 Name Type A0 Input- Addresses: These inputs are registered and must meet the A1 Synchronous set-up and hold times around the rising edge of CLK. The A burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. ...
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... A...A01 A...A11 A...A00 [ DEN =HIGH defined as CE=HIGH CY7C1359A/GVT71256T18 Description Second Third Address Address (internal) (internal) A...A01 A...A10 A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 MOE OE MATCH ...
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... Next [12 CY7C1359A/GVT71256T18 ADSC ADV WRITE OE CLK ...
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... TCK. This is the output side of the serial registers placed be- tween TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.) Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 Performing a TAP Reset The TAP circuitry does not have a Reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be ...
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... The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state ...
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... TEST-LOGIC 1 RESET 0 1 REUN-TEST/ 0 IDLE Note: 13. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram 1 SELECT ...
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... A OLC [15, 17 100 A OHC [15 8.0 mA OLT [15 8.0 mA OHT /2, Undershoot: V (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as GW, ADSC, etc.) may not have pulse widths less than t CC CY7C1359A/GVT71256T18 0 Selection Circuitry [14] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –5.0 5.0 0.2 V – ...
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... Notes: 18. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register 19. Test conditions are specified using the load in TAP AC Test Conditions. Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 [18, 19] Over the Operating Range Description Min. Max Unit 20 ...
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... Figure 5 TAP AC OUTPUT LOAD EQUIVALENT TEST CLOCK (TCK) TEST MODE SELECT (TMS) TEST DATA IN (TDI) TEST DATA OUT (TDO) Document #: 38-05120 Rev THTL t THTH t t MVTH THMX t DVTH t THDX t TLQV t TLQX CY7C1359A/GVT71256T18 ALL INPUT PULSES 3.0V 1.5V 1 TLTH Page ...
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... Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1359A/GVT71256T18 Description Description Page ...
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... Storage Temperature (plastic) ................... –55°C to +150° Junction Temperature ............................................... +150°C Power Dissipation.......................................................... 1. Short Circuit Output Current........................................ Operating Range Range 94 3G Com’ CY7C1359A/GVT71256T18 (continued) Signal Name TQFP 100 DQ10 8 DQ11 9 DQ12 12 DQ13 DQ14 18 DQ15 ...
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... Max.; CLK frequency = 0 CC Device deselected; all inputs < > Max CLK cycle time > t min. KC Description Test Conditions MHz 3.3V CC Test Conditions 4-layer PCB CY7C1359A/GVT71256T18 Min. Max. 1.7 V +0.3 CC 1.7 4.6 –0.3 0.8 –2 2 < V –2 2 OUT CC = 3.135V 2.4 = 2.375V 1.7 0.4 3.135 3 ...
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... MHz Min. Max. Min. 6.0 6.7 2.4 2.6 2.4 2.6 3.5 1.5 1.5 [17, 28, 29 [17, 28, 29] 1.5 6.0 1.5 3.5 [30] [17, 28, 29 [17, 28, 29] [17, 28, 29] 3.5 [17, 28, 29] [31] 1.5 1.5 [31] 0.5 0.5 is less than less than t KQHZ KQLZ OEHZ CY7C1359A/GVT71256T18 ALL INPUT PULSES 2.5V 90% 10% 0V 1.8 ns (c) -6.7 -7.5 -10 133 MHz 100 MHz Max. Min. Max. Min. 7.5 8.5 2.8 3.4 2.8 3.4 3.8 4.0 1.5 1 6.7 1.5 7.5 1.5 3.5 3 3.5 3.8 1.5 2.0 ...
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... Typical Output Buffer Characteristics Output High Voltage Pull-Up Current V (V) I (mA) Min –0.5 –38 0 –38 0.8 –38 1.25 –26 1.5 –20 2.3 0 2.7 0 2.9 0 3.4 0 Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 Output Low Voltage I (mA) Max –105 –0.5 –105 0 –105 0.4 –83 0.8 –70 1.25 –30 1.6 –10 2.8 0 3.2 0 3.4 Pull-Down Current I (mA) Min ...
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... CE active in this timing diagram means that all Chip Enables CE, CE 33. In this timing diagram assumed that DEN is tied to LOW (V Document #: 38-05120 Rev OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ , and CE are active CY7C1359A/GVT71256T18 Q(A2+2) Q(A2+3) Q(A2) BURST READ Q(A2+1) Page ...
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... Switching Waveforms (continued) [32, 33] Write Timing with Burst Feature CLK t S ADSP# ADSC ADDRESS A1 WEL#, WEH#, BWE# GW# CE# ADV# OE# t KQX DQ Q SINGLE WRITE Document #: 38-05120 Rev OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE CY7C1359A/GVT71256T18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE D(A3+2) Page ...
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... Switching Waveforms (continued) Read/Write Timing with Burst Feature CLK t S ADSP# ADSC ADDRESS A2 WEL#, WEH#, BWE#, GW# CE# ADV# OE# DQ Document #: 38-05120 Rev. ** [32, 33 Q(A1) Q(A2) D(A3) Single Reads Single Write CY7C1359A/GVT71256T18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) Burst Read Burst Write D(A5+1) Page ...
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... In this timing diagram assumed that burst feature is not used and therefore ADSP is tied to HIGH (V of ADV is a “Don’t Care”. 35. In this timing diagram assumed that WE = [BWE + WEL*WEH]*GW. Document #: 38-05120 Rev. ** [32, 34, 35 KQX t KQ Q(A1) Q(A2) Q(A3) Q(A4) Reads CY7C1359A/GVT71256T18 OEHZ t KQHZ D(A5) D(A6) D(A7) Writes ) and ADSC is tied to LOW ( D(A8) ) ...
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... Switching Waveforms (continued) [32, 34, 35] Compare/Fill Write Timing CLK ADDRESS WE# CE# DEN# OE# DQ MOE# t MOELZ MATCH Document #: 38-05120 Rev D(A1) t MOEHZ t KM MATCH HIGH CHIP DESELECTED t KMX FILL MISS WRITE CY7C1359A/GVT71256T18 D(A2) t MOEM HIT Page ...
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... CY7C1359A-166AC/ GVT71256T18T-6 150 CY7C1359A-150AC/ GVT71256T18T-6.7 133 CY7C1359A-133AC/ GVT71256T18T-7.5 100 CY7C1359A-100AC/ GVT71256T18T-10 Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
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... Document Title: CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM Document Number: 38-05120 Issue REV. ECN NO. Date ** 108311 09/25/01 Document #: 38-05120 Rev. ** CY7C1359A/GVT71256T18 Orig. of Change BRI New Cypress spec—converted from Galvantech format Description of Change Page ...