MAX3861ETG+ Maxim Integrated Products, MAX3861ETG+ Datasheet - Page 6

• Manufacturer Part Number: MAX3861ETG+
• Description: IC AMP POST W/AGC 24-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Postamplifierr

Specifications of MAX3861ETG+

• Applications: Optical Networks
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Operating Supply Voltage: 3.3 V
• Supply Current: 94 mA
• Operating Temperature Range: + 150 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Power Dissipation: 1350 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7Gbps Post Amp with Automatic Gain Control
6
2, 5, 14, 17
9, 12, 22
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PIN
EP
10
11
13
15
16
18
19
20
21
23
24
1
3
4
6
7
8
Exposed Pad Maxim recommends connecting the exposed pad to board ground.
NAME
OUT+
OUT-
V
GND
CG+
OSM
RSSI
CD+
CZ+
V
CG-
CD-
IN+
CZ-
IN-
EN
SC
SD
TH
REF
CC
Input Signal Detect Threshold Programming Pin. Attach a resistor between this pin and ground to
program the input signal detect assert threshold. Leaving this pin open sets the signal detect
threshold to its absolute minimum value (<2mV
Supply Voltage Connection. Connect all V
Positive CML Signal Input with On-Chip Termination Resistor
Negative CML Signal Input with On-Chip Termination Resistor
Signal Detect Enable. Set high (≥2.0V) or leave open to enable the input signal detection (RSSI and
SD) circuitry. Set low (≤0.4V) to power down the input signal detection circuitry.
Reference Voltage Output (2.0V). Connect this pin to the SC pin for maximum output signal swing.
Output Amplitude External Control. Ground SC for minimum output amplitude. Apply 2.0V to SC or
connect SC directly to V
Ground. Connect all GND pins to the board ground plane.
Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.
Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.
Output Signal Monitor. This DC signal is linearly proportional to the output signal amplitude.
Negative CML Data Output with On-Chip Back-Termination Resistor
Positive CML Data Output with On-Chip Back-Termination Resistor
Input Signal Detect. Asserts logic low when the input signal level drops below the programmed
threshold.
Received Signal Strength Indicator. Outputs a DC signal linearly proportional to the input signal
amplitude.
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.
REF
for maximum output amplitude.
CC
FUNCTION
pins to the board V
P-P
). See the Design Procedure section.
CC
plane.
Pin Description