PEF3460EV1.2 Infineon Technologies AG, PEF3460EV1.2 Datasheet

Page 1

...

Page 2

... Edition 2001-11-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...

Page 3

...

Page 4

PEF 3460 E Revision History: Previous Version: Page Page Subjects (major changes since last revision) (previous (current Version) Version Changed recommended connection for pin RSVD_F1 from "unconnected" to "pull-down resistor required". This is to ensure the correct T3/E3 ...

Page 5

Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

Table of Contents 3.3.5.1 Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.6 ...

Page 7

Table of Contents 5.6.2.3 Master Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

Table of Contents 7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

List of Tables Table 1 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

List of Tables Table 38 Parameter Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

List of Figures Figure 43 Block Diagram ot Test Access Port and Boundary Scan Unit . . . . . . 170 Figure 44 TE3-FALC Configuration Assistant Main Window . . . . . . . . . . . ...

Page 13

List of Messages Notification ID: Command ID: Command ID: Command ID: Command ID: Command ID: Command ID: Acknowledgement ID: Notification ID: Command ID: Notification ID: Notification ID: Command ID: Command ID: Command ID: Command ID: Acknowledgement ID: Command ID: Acknowledgement ...

Page 14

List of Messages Notification ID: Command ID: Command ID: Command ID: Command ID: Command ID: Command ID: Command ID: Acknowledgement ID: Command ID: Command ID: Notification ID: Command ID: Notification ID: Command ID: Notification ID: Command ID: Command ID: Notification ...

Page 15

List of Messages Acknowledgement ID: Command ID: Acknowledgement ID: Preliminary Data Sheet ACK_GET_STATUS ...

Page 16

Preface This Preliminary Data Sheet provides a complete reference for hardware and software design with "T3/E3 Framer & Line Interface for ATM, Frame Relay & PPP/IP" TE3-FALC (PEF 3460 E). Note: Some features mentioned in this document are options for ...

Page 17

Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ANSI T1.107-1995 section 9 (DS3 framing) ANSI T1.231-1997 section 7 (DS3 performance monitoring) ANSI T1.404-1994 (DS3) ANSI T1.646-1995 (DS3, esp. PLCP mapping) ATMF af-phy-0034.000, Aug. 1995 (E3 ...

Page 18

Overview The TE3-FALC is a complete solution for a T3/E3 broadband interface. It includes DS3/ E3 framing, analogue line interface, two jitter attenuators and the mapping of ATM or HDLC-framed PPP. The TE3-FALC also integrates a µController which is ...

Page 19

T3/E3 Framer & Line Interface for ATM, Frame Relay & PPP/IP TE3-FALC Version 1.1 1.1 Features General Features • Integrated T3/E3 LIU for recovery of analog signals from the line and the transmission of signals onto the line via a ...

Page 20

I/Os are 3.3 V tolerant and have 3.3 V driving capability • Package PBGA-272-4 (27mm x 27mm; pitch 1.27mm) • Full scan path and BIST of on-chip RAMs for production test • Estimated power consumption: < 1500 mW Analog ...

Page 21

ATM/PPP Protocol Processor • Transmit Cell Processing: – Extraction of ATM cells on pre-set VPI/VCI – Optional on-the-fly checking of CRC-10 or AAL5 CRC-32 and length fields for 1) extracted cells . – Supports ATM cell payload scrambling, header check ...

Page 22

System Interface • UTOPIA Interface – 8/16-bit interface running MHz. – Compliant to ATMF Utopia Level 2. – 16 Cell FIFO in both transmit and receive directions, • POS-PHY Interface – Dual mode 8/16-bit interface running up ...

Page 23

Logic Symbol Line rl1 In te rfac e rl2 x clk igital Line rclki In te rfac e rdi T ...

Page 24

Minimum System 1 1 100 nf 37.5 T3/E3 +/- 1% +/- 1% Figure 2 TE3-FALC Minimum System (UTOPIA or Serial Interface) The above diagram shows the minimum system connectivity for ...

Page 25

Typical Applications T3/E3 uplink card Infineon TE3-FALC PEF3460 Figure 3 3G Mobile Base Station (AAL1/AAL2/AAL5) The above diagram shows an application where the TE3-FALC provides the T3/E3 high speed WAN connection Base stations, via point-point micro-wave ...

Page 26

Infineon VDSL-A PEB22811 Infineon VDSL-A PEB22811 Infineon VDSL-A PEB22811 Infineon VDSL-A PEB22811 Figure 4 Customer based MDU with T3/E3 uplink The above diagram shows an example of a four port Multi Dwelling Unit (MDU). The TE3-FALC provides the high speed ...

Page 27

Pin Descriptions Table 1 gives an overview about the pin utilization per interface. Beyond the signal count of these interfaces there is a variety of test signals, which is made available either directly (using dedicated pins) or multiplexed with ...

Page 28

Pin Diagram (top view VSS VDD clkout VDDPLL mpim1 B RSVD ref8k rsync clkin mpint_n mpim0 C core_ N.C. RSVD N.C. rclkout ratio D N.C. RSVD RSVD VSS tclkin Clock E N.C. N.C. ...

Page 29

Pin Definitions and Functions The following tables contain the pin information. The 1 nd number, the 2 the pin name. rd The 3 column describes input (I), output (O) or bidirectional (I/O) pin. If it’s ...

Page 30

T3/E3 Analog Line Interface Table 2 T3/E3 Analog Line Interface Ball Name In/Out No. J1 XL1 O (analog) K2 XL2 O (analog) K1 RL1 I (analog) L1 RL2 I (analog) F3 RSVD_F3 I G4 RSVD_G4 I J4 RSVD_J4 O ...

Page 31

DS3/E3 Digital Line Interface Table 3 DS3/E3 Digital Line Interface Ball Name In/Out No. G3 RCLKI I G2 RDI I H2 XCLK O H3 XDO O B1 RSVD_B1 O D2 RSVD_D2 O D3 RSVD_D3 O E4 RSVD_E4 O 2.2.3 ...

Page 32

Table 4 DS3/E3 Bitstream and Overhead Access Interface (cont’d) Ball Name In/Out No. R1 DOHTCK O P3 DOHTD I R2 DOHTINS I T1 DRGCKIN I P4 DRXDOUT O R3 DRXDIN I T2 DRFSOUT O U1 DRMIN I T3 DRGCKOUT O ...

Page 33

Clock Multiplier Interface Table 5 Clock Multiplier Interface Ball Name In/Out No. C5 CORE_ I RATIO B4 CLKIN I A3 CLKOUT O D5 TCLKIN I Preliminary Data Sheet Driver Pullup / Function -down PU Core Clock Ratio ’0’ : ...

Page 34

Table 5 Clock Multiplier Interface (cont’d) Ball Name In/Out No. C4 RCLKOUT O B3 RSYNC I B2 REF8K I 2.2.5 System Interface (UTOPIA / POS-PHY / UTOPIA-L2X) These pins carry different signals depending on the interface mode. Please refer to ...

Page 35

Table 6 System Interface Receive (UTOPIA/POS-PHY/UTOPIA-L2X) (cont’d) Ball Name In/Out No. Y19 SRD0 O V18 SRD1 O W19 SRD2 O Y20 SRD3 O W20 SRD4 O V19 SRD5 O U18 SRD6 O T17 SRD7 O V20 SRD8 O U20 SRD9 ...

Page 36

Table 7 System Interface Transmit (UTOPIA/POS-PHY/UTOPIA-L2X) Ball Name In/Out No. P18 STCLK I G19 STADDR0 I G20 STADDR1 I H18 STADDR2 I H19 STADDR3 I J17 STADDR4 I J18 RSVD_J18 I J20 STD0 I K17 STD1 I K18 STD2 I ...

Page 37

Table 7 System Interface Transmit (UTOPIA/POS-PHY/UTOPIA-L2X) (cont’d) Ball Name In/Out No. G17 STSX/STSOC I F18 STSOP I D20 STEOP I E18 STMOD I C20 STERR I E19 STRDY O F20 STPA O F19 RSVD_F19 O G18 RSVD_G18 O 2.2.6 Microprocessor ...

Page 38

Table 8 Microprocessor Interface (cont’d) Ball Name In/Out No. D7 MPIM2 I C6 MPIM3 I A6 MPIM4 I/O E17 MPCLK I C7 MPCS I C15 MPA0 I/O D14 MPA1 I/O B15 MPA2 I/O C14 MPA3 I/O B14 MPA4 I/O A14 ...

Page 39

Table 8 Microprocessor Interface (cont’d) Ball Name In/Out No. A10 MPA16 I/O B10 MPA17 I/O C10 MPA18 I/O D10 MPA19 I/O B7 MPBHE I/O MPBLE MPTSIZ0 A8 MPWR I/O MPR/W C8 MPRD I/O MPDS MPTS A7 MPREADY O (t/s) MPDTACK ...

Page 40

Table 8 Microprocessor Interface (cont’d) Ball Name In/Out No. B17 MPD8 I/O C17 MPD9 I/O D16 MPD10 I/O A18 MPD11 I/O A17 MPD12 I/O C16 MPD13 I/O B16 MPD14 I/O A16 MPD15 I/O B5 MPINT O, o/d A9 MPMCS O ...

Page 41

Table 8 Microprocessor Interface (cont’d) Ball Name In/Out No. C9 MPBG I MPHLDA D9 MPBB O (o/d) D 2.2.7 JTAG Interface Table 9 JTAG Interface Ball Name In/Out No. V2 TDO O W1 TDI I V3 TCK I W2 TMS ...

Page 42

Debug Interface (Reserved) This debug interface is for manufacturer use only. Pins can be left unconnected. Table 10 Debug Interface Ball Name In/Out No. V8 RSVD_V8 I W8 RSVD_W8 I Y8 RSVD_Y8 O U9 RSVD_U9 O V9 RSVD_V9 O ...

Page 43

Control Interface Table 11 Control Interface Ball Name In/Out No. Y2 POR I W4 RSVD_W4 I/O (o/d) Y6 CFG0 I V7 CFG1 I W7 CFG2 I Y7 RSVD_Y7 I Preliminary Data Sheet Driver Pullup / Function -down Power-On Reset ...

Page 44

General Purpose I/O Port Table 12 General Purpose I/O Port Ball Name In/Out I/O Preliminary ...

Page 45

UART Interface Table 13 UART Interface Ball Name In/Out No. V4 ATXD O U5 ARXD I 2.2.12 Test Interface Table 14 Test Interface Ball Name In/Out No. T4 SCANMODE I U3 SCANEN I Preliminary Data Sheet Driver Pullup / ...

Page 46

Power Supply Table 15 Power Supply Ball No. Name A1, D4, D8, D13, D17, V H4, H17, N4, N17, U4, U8, U13, U17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 ...

Page 47

Functional Description 3.1 Functional Overview 3.2 Block Diagram Overhead Interface Tx Line Interface Analog or Digital DS3 / E3 Framer Transmit DJAT DS3 C-bit parity/M23 LIU E3 G.832 FDL Insert DS3 FEAC DS3 MDL E3 TTI ...

Page 48

Transmit Line Interface The main internal functional blocks are • Analog line receiver with noise & crosstalk filter, equalizer network and clock/data recovery • Analog line driver with programmable pulse shaper • Central clock generation module • Maintenance functions ...

Page 49

The jitter attenuated clock is output on pin XCLK. 1) disabled . In that case data is read from the transmit elastic buffer with the clock sourced on pin TCLKIN (34 MHz for MHz for DS3). 0.1 ...

Page 50

RX and TX Jitter Attenuator Buffer The TE3-FALC has two jitter attenuator buffers, one for transmit direction and one for receive. The buffer length is 64 bit. The buffers can be used if the line clock and the framer ...

Page 51

In both modes, full payload rate format is supported, i.e. the data blocks [84] carry one continuous data stream. 3.3.4.1 M23 Multiplex Format The framing structure of the M23 multiplex signal is shown in multiframe consists of 7 subframes and ...

Page 52

X The X-bits are used for transmission of asynchronous in-service messages (Remote Defect Indications, RDI). Both X-bits carry the identical value and do not change more than once every second. [84] - DS3 Information Data These bits represent an information ...

Page 53

FEAC - Far End Alarm and Control Channel The alarm or status information of a far end terminal is sent back over the Far End Alarm and Control channel. Messages are sent in bit oriented mode ( BOM). Access to ...

Page 54

Performance Measurement The following conditions are counted: • Line code violations • Excessive zeros • P-bit errors, CP-bit errors • Framing bit errors • Far end block errors • OOF defects • LOS defects • Remote Defect Indications (RDI) ...

Page 55

TR - Trail Trace This byte is used to repetitively transmit a trail access point identifier (16-byte frame format) so that a trail receiving terminal can verify its continued connection to the intended transmitter. TE3-FALC provides insert and extract access ...

Page 56

Performance Measurement The following conditions are counted: • Line code violations • BIP-8 errors • Framing bit errors • Remote error indications (REI) • OOF defects • LOS defects • Remote Defect Indications (RDI) • Errored Seconds (far-end and ...

Page 57

ATM Cell Processor and PLCP The cell processor performs the mapping and de-mapping of ATM cells from the G.832 E3 Frame, DS3 Frame and DS3-PLCP Frame. The mapping and de-mapping follows the requirements described in G.804. The self-synchronizing payload ...

Page 58

As indicated in the state diagram it requires the number of DELTA consecutive cells with correct HEC to transition from the PRESYNC state to the SYNCH state. Also, only a sequence of ALPHA consecutive cells with incorrect HEC can bring ...

Page 59

B1 - Bit Interleaved Parity The B1 octet contains the bit interleaved parity information (BIP-8) calculated over a 12 times 54 octet structure consisting of the POH field and the associated ATM cells of the previous PLCP frame. G1 The ...

Page 60

P0..P11 - Path Overhead Identifier (POI) Octets The Path Overhead Identifier (POI) octets mark the individual path overhead (POH) octets. Table 23 Path Overhead Identifier (POI) Codes POI POI Code P11 00101100 P10 00101001 P9 00100101 P8 00100000 P7 00011100 ...

Page 61

HDLC Packet Processor The HDLC packet processor implements HDLC framing and supports the Point-to-Point Protocol (PPP) with its bit-synchronous and octet-synchronous mapping options. Opening PPP PPP Flag Address Control Figure 10 PPP in HDLC-like Framing ...

Page 62

Control fields. If not assumed that the fields were compressed and were not transmitted. Towards the system side, the bytes FF-03 are added to front if they were not present on the line. When other Address or ...

Page 63

Operational Description 4.1 Operational Overview 4.2 Operating States This chapter shall guide the designer through the initial steps of activating and configuring the TE3-FALC. 4.2.1 Reset Global Hardware Reset A Global Reset of the device can be issued on ...

Page 64

Receive NFC_DCI_ACCESSIBLE Optional: Setup Interrupt Output Characteristic by sending message CMD_INTERRUPT_MODE_SET Optional: Setup CLKIN Clock Supply Frequency by sending message CMD_CLOCKING_FREQUENCY_SET Optional: Initiate internal Memory Check by sending message CMD_MEMORY_REGION_CHECK Load Firmware Data Block by sending message CMD_BLOCK_UPLOAD_WITH_CRC Upload Complete: ...

Page 65

Table 24 Upload Image Data 31 TCID(15: Data Byte ... CRC32 unused. Byte 3 A block of image data as shown in The usable address range is 8000 The length indicator (LENIC) includes the whole block size, including ...

Page 66

Note: The following messages are only applicable for the boot process, i.e. until message NFC_FW_ACCESSIBLE Notification ID: This message reports the successful initialization of the Device Control Interface (DCI) after reset. When receiving this message the interface is ready to ...

Page 67

Optional Boot Messages The following messages are optional and can be used as needed to improve the standard (minimum) boot process described above. Note that after the boot process messages CMD_SPECIFY_CLOCKS (page 96) are available for analog functionality as the ...

Page 68

Command ID: The external interrupt pin characteristic is configurable with this meassage. By default the interrupt output is disabled. For interrupt driven download, the interrupt mask register be programmed. Note: Interrupts INTREG:HPQINSA and INTREG:LPQINSA are not available during download! Input ...

Page 69

Receive NFC_FW_ACCESSIBLE Figure 12 EPROM Boot Process 4.2.3 Initialization After the boot process is completed, as indicated with the notification message NFC_FW_ACCESSIBLE TE3-FALC’s ingress queue LPQIN. The first steps of the initialization procedure shown in TE3-FALC interrupt output pin characteristic ...

Page 70

Device Controller Figure 13 Minimum Initialization Message Flow As an option, the RX PLL and TX PLL transitioning to their LOCK state can be monitored through notifications NFC_PLL_LOCKED (page 95). These notifications must first be enabled by using the message ...

Page 71

Now configuration of the data flow is complete and the line and system side interfaces shall be enabled with the 4.2.4 Test Loops The TE3-FALC supports a number of test loops as shown in and a Local Loop shall be ...

Page 72

Local Framer Loop The local framer loopback mode disconnects the receive data to the framer. Instead of the signals coming from the LIU, data provided by the transmit framer is routed back to the receive framer. The transmit clock is ...

Page 73

Hardware Interface Description 5.1 T3/E3 Analog Line Interface 5.1.1 Receiver Application 75 Figure 15 Standard Receiver Configuration Table 25 External Component Values for Receiver Parameter [nF ...

Page 74

Line Monitoring Application DSX cross connect point Figure 16 DS3 Line Monitoring Table 26 External Component Values for DS Line Monitoring Parameter ...

Page 75

Receive Line Interface The receive line interface consists of a pre-amplifier, a noise and crosstalk filter, a variable gain amplifier (VGA) and an equalizer followed by the clock and data recovery. The noise and crosstalk filter reduces distortions within ...

Page 76

Receive Clock and Data Recovery The receive clock and data recovery extracts the route clock from the digital data stream and converts the data stream into a dual rail bit stream. The clock and data recovery needs a reference ...

Page 77

Receive Jitter Tolerance The TE3-FALC receiver’s tolerance to input jitter complies to and exceeds the relevant international standards. Especially the requirements of Telcordia GR-499-CORE (DS3), ITU-T G.824 (DS3) and ITU-T G.823 (E3) are fulfilled and exceeded. Table 28 show ...

Page 78

GR-499-CORE Cat. 1 Figure 20 Jitter Tolerance GR-499-CORE Jitter Tolerance Requirements (DS3) The input jitter tolerance is defined as the minimum amplitude of sinusodial jitter at a given frequency that when ...

Page 79

Transmitter Application Figure 21 Transmitter Configuration Table 29 External Component Values for Transmitter Parameter [pF This value refers to an ideal transformer without any ...

Page 80

Table 30 E3 Transmit Return Loss Frequency Range from [kHz] 860 1720 1) measured with an unframed PRBS 2 5.1.7 Transmit Pulse Shaper The internal pulse shaper generates the required pulse shapes for E3 and DS3 signals according to ANSI ...

Page 81

rfa Framer rity ransmit ...

Page 82

Bitstream (Break-out) Interface: Receive Framer Payload Extraction DRGCKOUT 1) DRFSOUT DRXDOUT last bit of DS3 Multiframe (N = 4704) last bit of E3 Frame (N = 4240) Bitstream Break-out Interface: Receive ATM/HDLC Data Insertion DRGCKIN DRMIN DRXDIN Overhead Interface: Receive ...

Page 83

Bitstream (Break-out) Interface: Transmit Framer Payload Insertion DTGCKOUT 1) DTFSOUT DTXDIN last bit of DS3 Multiframe (N = 4704) last bit of E3 Frame (N = 4240) Bitstream Break-out Interface: Transmit ATM/HDLC Data Extraction DTGCKIN DTMIN DTXDOUT Overhead Interface: Transmit ...

Page 84

RSYNC is the optional receive reference clock, the TE3-FALC can use this clock during LOS conditions for a reference to the RX DJAT PLL. The reference clock for the RX DJAT PLL can vary between 8 kHz and 52 MHz. ...

Page 85

The size of the chunks is programmable. The signals listed in Table 31 UTOPIA-L2X / POS-PHY interface signals. These tables shall be used as a reference. Table 31 Receive ...

Page 86

Table 32 Transmit UTOPIA / POS-PHY / UTOPIA-L2X Interface Signals (cont’d) TE3-FALC I/O Function Signal STSX I Transmit Start of Transfer/ Cell STSOP I Transmit Start Of Packet STEOP I Transmit End Of Packet STMOD I Transmit Modulo Count STERR ...

Page 87

Parity check enabled. Parity-errored cells are discarded within transmit buffer. – Parity check disabled UTOPIA Cell Format For 16-bit UTOPIA interface the 54-octet cell format is used, with big endian byte arrangement. For 8-bit UTOPIA interface the 53-octet cell ...

Page 88

Odd or Even parity generation/check Short parity-errored packets are discarded within transmit buffer. Long parity-errored packets are aborted on the line. – Parity check disabled 5.5.3 UTOPIA-L2X Interface Option UTOPIA-L2X Transmit Following diagram shows an example of packet oriented ...

Page 89

The higher-layer device has the possibility to invalidate a packet sent to the TE3-FALC by asserting the STERR line along with STEOP. In case of HDLC/PPP protocol this leads to the well defined abort sequence. In section (C), PHY M ...

Page 90

Optional UTOPIA-L2X Settings • Bus Width – 8-bit – 16-bit • Chunk Size – Programmable bytes (multiple of 4 bytes) • Status Indication – MPHY polling mode – Direct status indication • Bus Configuration – Multiple ...

Page 91

Slave Accesses (Device Configuration/Control) Communication with the TE3-FALC is done via MPI slave accesses according to the message based Device Control Interface (DCI, refer to data structures are 32-bit wide, and in general 32-bit words ( DWORD) have to ...

Page 92

Table 5-3 16-bit Intel Mode (cont’d) BHE • Table 5-4 16-bit Asynchronous Motorola Mode BLE ...

Page 93

Prior to a read access the TE3-FALC arbitrates for bus mastership. Both Intel and Motorola arbitration mechanisms are implemented, pin correspondence in both modes: Table 34 Intel/Motorola Master Pin Correspondence Intel MPIM[1: MPIM[1: MPRD MPHOLD ...

Page 94

Arbitration Motorola Mode Figure 26 shows the arbitration in Motorola mode. The MPI master starts arbitration by asserting the MPBR signal (low). After receiving an bus grant MPBG the MPI master has to wait until MPBB becomes or is ...

Page 95

After the TE3-FALC is granted to access the bus, the address and the MPCS signal are driven synchronously to the internal system clock (SYSCLK). After three system clock cycles the MPRD signal is activated. The MPRD signal can be used ...

Page 96

Table 35 PLL Frequency Programming P2, P1, P0 CLKIN Clock Supply Frequency 000 Reserved. 2 001 Reserved. 2 010 4 MHz CLKIN 2 011 8 MHz CLKIN 2 100 16 MHz 2 101 32 MHz 2 110 Reserved. 2 111 ...

Page 97

Software Interface Description 6.1 Device Control Interface (DCI) The Device Control Interface (DCI) is built to make the configuration and controlling of the device easier and more comfortable. The DCI is a dual-ported Memory- and Register-Area which is accessible ...

Page 98

This interface decouples the internal functional blocks from the external microprocessor bus. The RAM data width is 32 bits, the depth is 8192 words, resulting in an overall size of 32 kBytes. Table 36 shows how memory and register areas ...

Page 99

Read-Modify-Write sequence to preserve control information within the bits marked as "reserved". MCR MPI Control Register Byte Byte 1 MCR Register Bits: ENDIAN Host Processor Endianess ...

Page 100

In case bit INTREG:DCIERR was read as ’1’, the order to clear its status bits. INTREG Interrupt Status Register Byte reserved Byte 1 INTREG Register Bits: DCIERR DCI Error ...

Page 101

INTMSK Interrupt Mask Register Byte reserved Byte 1 INTMSK Register Bits: Each bit in this register masks the MPINT interrupt generation for the corresponding interrupt status bit of register ...

Page 102

DCIERR Register Bits: LPQOUT Egress Low/High Priority Queue Overflow Error This bit indicates that the corresponding egress queue experienced an OV HPQOUT overflow error and at least one message got lost. The host processor OV should read the corresponding egress ...

Page 103

D evice C ontro ller Ingress E gress Figure 28 Dependency between different message types Command Messages Command Messages are used for configuring or controlling the TE3-FALC. The direction of command ...

Page 104

Notification Message Notification messages are sent from the TE3-FALC to the external controller if a special internal event occurs. Every Notification message has to be enabled by the user software before. Within a notification message the transaction correlation identifier TCID ...

Page 105

To distinguish between the different messages, the actuator contains a 10-bit message identifier field MSGID. 31 1-1 0 MSGPT(15:0) 1-2 0 MSGPT(15:0) 2-1 TCID(15:0) 2-2 TCID(15:0) Byte 3 Message Actuator Fields Message Identifier MSGID This unique value is to distinguish ...

Page 106

Message Actuator Fields (cont’d) Progress-Indication Flag P-Flag This flag is only valid within command messages. It decides whether a progress-indication message shall be generated when the command including its optional parameter array has been read. This indication can be used ...

Page 107

Optional Parameter Array The parameter array (see array has its own header (shaded fields). Table 38 Parameter Array Structure 31 TCID(15:0) 16-bit Value (packed) Number of Bytes following, e.g. 5 8-bit Value4 unused Number of Bytes following, e.g. 6 ...

Page 108

Parameter Array Fields Length Indicator LENIC The length indicator (LENIC) represents the size (in number of bytes) of the (15:0) complete parameter array, including its 8-byte header progress-indication message is desired for this command message. 1 Send progress-indication ...

Page 109

Parameter Array Fields (cont’d) Parameter ID Param. Parameters consist of a 16-bit Parameter ID and one or more associated ID Values. The list of optional parameters is processed as long as the defined (15:0) length (LENIC) of the parameter array ...

Page 110

Message Catalog The below example of a command and corresponding acknowledge message show the structure of message descriptions used in the following chapters. Command ID: A brief description of the message is posted here. Input Parameters (optional) Parameter ID ...

Page 111

Device Maintenance Messages Notification ID: This notification is sent to the host after receipt firmware boot and initialization was completed successfully. The attached output parameters identify the hardware and firmware version ID of the device (see encoding). This notification ...

Page 112

Command ID: CLK_FRQ_TCLKIN 32 CLK_FRQ_RSYNC 32 CLK_FRQ_CLKOUT 32 CLK_SRC_RCLKOUT P CLK_FRQ_RCLKOUT 32 Notification ID: After power up the internal PLLs are in the unlocked state. If all clocking setting are applied, the internal PLLs shall reach the locked state. This ...

Page 113

Notification ID: Output Parameters Parameter ID INTERNAL_PLL P Command ID: With this command the output characteristics of the interrupt output pin MPINT can be programmed. Interrupt sources are determined by reading register Interrupt events can be masked via register Input ...

Page 114

Command ID: This message causes the firmware to activate or deactivate a specific data path loop. For details on provided loop options refer to Input Parameters (optional) Parameter ID LOOP_LOCAL P LOOP_REMOTE P 1) This is an option which is ...

Page 115

Command ID: Input Parameters Acknowledgement ID: This acknowledgement is sent to the host after receipt of the message to identify the hardware and firmware version of the device. Output Parameters Parameter ID HW_VERSION_ID 32 FW_VERSION_ID 32 Command ID: This commands ...

Page 116

Command ID: This message causes the firmware to perform a reset of the TE3-FALC. All hardware modules are reset. All interrupts except for DCI interrupts are disabled. For details on the boot process refer to Input Parameters (optional) Parameter ID ...

Page 117

Data Flow Configuration Message The configuration process should be hierarchical. A Data Flow Configuration Function selects a specific data flow between the system side and the line side of the TE3-FALC device. According to the selected data flow all ...

Page 118

Table 39 Supported Operational Modes (cont’d) Type of Data Flow (Command Message) ATM - G.832 (CMD_SET_ATM_E3G832) ATM - DS3 (CMD_SET_ATM_DS3) ATM - PLCP - DS3 (CMD_SET_ATM_PLCP_DS3) PPP - G.832 (CMD_SET_PPP_E3G832) PPP - DS3 (CMD_SET_PPP_DS3) ATM Transparent (CMD_SET_ATM_TRANS) PPP Transparent (CMD_SET_PPP_TRANS) ...

Page 119

Command ID: Command ID: Message CMD_SET_ATM_E3G832_E3 System Interface <=> G.804 <=> E3:G.832 <=> E3 LIU. Message CMD_SET_ATM_E3G832 System Interface <=> G.804 <=> E3:G.832. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings ...

Page 120

Command ID: Command ID: Message CMD_SET_ATM_DS3_T3 System Interface <=> G.804 <=> DS3 <=> T3 LIU. Message CMD_SET_ATM_DS3 System Interface <=> G.804 <=> DS3. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings ...

Page 121

Command ID: Command ID: Message CMD_SET_ATM_PLCP_DS3_T3 System Interface <=> G.804 <=> PLCP <=> DS3 <=> T3 LIU. Message CMD_SET_ATM_PLCP_DS3 System Interface <=> G.804 <=> PLCP <=> DS3. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P ...

Page 122

Command ID: Command ID: Message CMD_SET_PPP_E3G832_E3 System Interface <=> PPP <=> E3:G.832 <=> E3 LIU. Message CMD_SET_PPP_E3G832 System Interface <=> PPP <=> E3:G.832. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings ...

Page 123

Command ID: Command ID: Message CMD_SET_PPP_DS3_T3 System Interface <=> PPP <=> DS3 <=> T3 LIU. Message CMD_SET_PPP_DS3 System Interface <=> PPP <=> DS3. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings ...

Page 124

Command ID: This message sets up the path System Interface <=> G.804 <=> E3 LIU , with the E3 G.832 framer being bypassed. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings ...

Page 125

Command ID: This message sets up the path System Interface <=> G.804 <=> T3 LIU , with the T3 framer being bypassed. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings (These ...

Page 126

Command ID: This message sets up the data path System Interface <=> PPP <=> E3 LIU , with the E3 G.832 framer being bypassed. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default ...

Page 127

Command ID: This message sets up the data path System Interface <=> PPP <=> T3 LIU , with the DS3 framer being bypassed. Input Parameters (optional) Parameter ID LINE_TIMING P SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P Default Settings ...

Page 128

Command ID: Command ID: Message CMD_SET_BIT_E3G832_E3 Bitstream Interface <=> E3:G.832 <=> E3 LIU. Message CMD_SET_BIT_E3G832 Input Parameters (optional) Parameter ID LINE_TIMING P Default Settings (These settings can be modified by E3 Framer Command ID: Command ID: Message CMD_SET_BIT_DS3_T3 Bitstream Interface ...

Page 129

Interfaces Control Messages Command ID: This message controls enabling and disabling of both line interface (digital or analog) and system side interface (UTOPIA, POS-PHY or Bitstream). Also the bitstream break-out and DS3/E3 framer overhead access interfaces (see Chapter 5.3) ...

Page 130

Module Configuration Messages Command ID: This message causes the firmware to configure the Line Interface Unit (LIU). Input Parameters (optional) Parameter ID LIU_AMPLIFIER P LIU_TRANSMIT P Command ID: This message causes the firmware to configure the Digital Jitter Attenuators. ...

Page 131

Command ID: DJAT_TRANSMIT P DJAT_TX_LOSMODE digital line interface mode, the clock on pin RCLKI is used as reference instead. Command ID: This message causes the firmware to configure the DS3 framer. The DS3 framer is configured in ...

Page 132

Command ID: DS3F_AIS_PATTERN P DS3F_F_REFRAME P DS3F_M_REFRAME P Notification ID: This message notificates to the host, that the C-Bit Parity mode (AIC signal is set the M23 mode has been detected (AIC signal is random 1s and ...

Page 133

Command ID: This message causes the firmware to configure the E3 framer. Input Parameters (optional) Parameter ID E3F_MODE P Preliminary Data Sheet CMD_CFG_E3_FRAMER Value _G832 Select E3 framing according to ITU-T G.832. _BYPASS Bypass E3 framer. Setting the E3F_MODE parameter ...

Page 134

Command ID: This message causes the firmware to configure the HDLC Module. Input Parameters (optional) Parameter ID HDLC_MODE P HDLC_CRC_MODE P HDLC_SHARED_FLG P HDLC_IFTF P HDLC_MAX_FRMLEN P HDLC_MIN_FRMLEN P PPP_COMPRESS case of inter-frame time fill set to ...

Page 135

Command ID: This message causes the firmware to configure the G.804 Module. Input Parameters (optional) Parameter ID ATM_MAPPING P ATM_SCRAMBLING P ATM_HEAD_CORR P ATM_ALPHA P ATM_DELTA P Preliminary Data Sheet CMD_CFG_ATM_PROCESSOR Value _DIRECT Direct mapped ATM. _PLCP PLCP mapped ATM. ...

Page 136

Command ID: This message causes the firmware to configure the System Interface. Input Parameters (optional) Parameter ID SYSIF_MODE P SYSIF_WIDTH P SYSIF_ADDR P SYSIF_STATUS P SYSIF_CHUNK_SIZE P SYSIF_PARITY_CHK P Preliminary Data Sheet CMD_CFG_SYSIF Value _UTOPIA_L1 UTOPIA Level 1 mode _UTOPIA_L2 ...

Page 137

Command ID: SYSIF_PARITY P SYSIF_OUTPUTS P SYSIF_HANDSHAKE P Command ID: This message causes the firmware to configure the Data Buffers. The forward threshold parameter has no relevance for ATM operation. Input Parameters (optional) Parameter ID BUF_SIZE P BUF_FW_THRESH P 1) ...

Page 138

Command ID: This message causes the firmware to configure the General Purpose I/O port pins. Input Parameters (optional) Parameter ID GPIO_0_CTRL P GPIO_1_CTRL P ... GPIO_7_CTRL P GPIO_ALL_CTRL P GPIO_0_LED_STAT 32 GPIO_1_LED_STAT 32 GPIO_2_LED_STAT 32 GPIO_3_LED_STAT 32 GPIO_4_LED_STAT 32 GPIO_5_LED_STAT ...

Page 139

Command ID: This message causes the firmware to perform a read access to the General Purpose I/O port pins. Input Parameters Acknowledgement ID: Returned input level of the GPIO port after requested by the host via message CMD_READ_GPIO. Output Parameters ...

Page 140

Link Maintenance Messages 6.3.5.1 TTI Support (E3/G.832) The firmware synchronizes to the Trail Trace Identifier (TTI) as specified in G.832 Annex A and checks and generates the CRC-7 checksums. TTI data are not generated or evaluated by the firmware ...

Page 141

Notification ID: This message indicates to the host that TTI data different from the data set by message CMD_CFG_TTI_CHANNEL To enable this notification use message Output Parameters Parameter ID TTI_RX_STATUS P TTI_RX_DATA 8 Preliminary Data Sheet NFC_TTI_RX_DATA_CHANGE was received. CMD_SET_NFC_ALM_MODE ...

Page 142

Payload Type (PTY) Support (E3/G.832) Command ID: This message causes the firmware to start or stop evaluating the received PTY field and sets the transmit and receive Payload Type field. The PTY transmitter is always active. Note that the ...

Page 143

Notification ID: This message indicates to the host that a PTY field different from the field set by message CMD_CFG_PTY_CHANNEL Output Parameters Parameter ID PTY_RX_STATUS P PTY_RX_FIELD P Preliminary Data Sheet NFC_PTY_RX_DATA_CHANGE was received. Value _MATCH New received PTY data ...

Page 144

SSM Nibble Support (E3/G.832) Command ID: This message causes the firmware to start or stop receiving SSM nibble data. The SSM transmitter is always active. Input Parameters (optional) Parameter ID SSM_RX_CHNG_CNT P SSM_TX_DATA P SSM_RX_CMP_DATA P Notification ID: This ...

Page 145

MDL Support (DS3) Three bits C-Bits per multiframe (DL Maintenance Data Link). An HDLC controller processes these bits, checks and generates CRC16 checksums, adds and detects HDLC frame delimiting flags etc. The HDLC idle pattern when no data are ...

Page 146

Notification ID: This message notifies the host about new receive MDL data. Along with the MDL data, the parameter MDL_RX_STATUS indicates whether the received HDLC frame is valid or not. To enable this notification use message Output Parameters Parameter ID ...

Page 147

FEAC Support (DS3) The firmware synchronizes to the 8-ones bit pattern in the FEAC codes delivered by the hardware. Table 41 and firmware, according to ANSI T1.107-1995 (Figures 23 and 24). The unassigned codes listed in ANSI T1.107-1995 Table ...

Page 148

Command ID: This message causes the firmware to transmit the FEAC code word followed by the DS3 line code word acc. to ANSI T1.107-1995. Input Parameters (optional) Parameter ID FEAC_CODEWORD P FEAC_CODE_CNT P Notification ID: This message indicates to the ...

Page 149

Alarm Messages 6.3.6.1 Framer LOS Detection (Loss of Signal) Alarm ID: An LOS defect occurs when the TE3-FALC does not detect the expected signal type on the line. In DS3 mode, LOS defects are integrated to generate an LOS ...

Page 150

Framer OOF/LOF Detection (Out of Frame, Loss of Frame) Alarm ID: This alarm notifies about both declaring and clearing a Out-of-Frame (OOF) defect. An OOF defect is indicated by the framer if several F- and M-bit errors are detected. ...

Page 151

Framer AIS/IDLE Detection (Alarm Indication, DS3 Idle Signal) Alarm ID: An AIS defect is declared when the AIS pattern is received from the far end. In DS3 mode, AIS defects are monitored to generate an AIS failure after 2.5 ...

Page 152

Alarm ID: This alarm is generated if the DS3 Idle Signal is detected on the receive line. The Idle Signal is defined as a 1100 DS3 mode only. To enable this alarm use message Output Parameters Parameter ID FRM_IDLE_RCVD P ...

Page 153

Alarm ID: In DS3 mode, an RDI defect (also known as “far-end SEF/AIS defect") is declared when both X-bits in an M-frame are received to zero cleared when both X-bits are received to one mode a ...

Page 154

Framer RDI Generation (Remote Defect Indication) Command ID: This message configures the criteria to declare "Remote Defect Indication" (RDI) towards the far end. By default, RDI is only declared on LOS, OOF and AIS defects configration, ...

Page 155

Framer FEAC Detection (Far End Alarm Control) Alarm ID: This message indicates to the host, that a FEAC alarm has occured. To enable this alarm use message Output Parameters Parameter ID FEAC_ALARM P 6.3.6.8 Framer FEAC Generation (Far End ...

Page 156

PLCP OOF Detection (Out-of-Frame) Alarm ID: This alarm notifies about both declaring and clearing a PLCP Out-of-Frame (OOF) defect. To enable this alarm use message Output Parameters Parameter ID PLCP_OOF_DEFECT P Firmware Actions Actions when declared Actions when cleared ...

Page 157

G.804 LCD Detection (Loss of Cell Delineation) Alarm ID: This message indicates to the host, that the G.804 receiver has lost or gained cell delineation synchronization. To enable this alarm use message Output Parameters Parameter ID G804_LCD P Firmware ...

Page 158

Performance Measurement 6.3.7.1 Bit Error Ratio Testing (BERT) Command ID: This message configures the bit error ratio test unit with a programmable bit pattern. Note that the framer gets reset with each start of a BER measurement. Input Parameters ...

Page 159

Command ID: Note: The parameters listed below are only relevant if a generic pattern shall be built. BERT_GEN_LENGTH P BERT_GEN_FBTAP P BERT_GEN_FIXPAT 32 BERT_GEN_INVERT P Notification ID: To enable this notification use message Output Parameters Parameter ID RPT_BERT_TOTAL 32 Preliminary ...

Page 160

Status Messages Command ID: This message initiates the firmware to send the device status in form of a 32-bit status word. Input Parameters Acknowledgement ID: The device status is coded as a 32-bit word with the bit assignment shown ...

Page 161

Command ID: Preliminary Data Sheet CMD_GET_STATUS (cont’d) 0001 0000 Receiving DS3/E3 AIS Defect H 0002 0000 Receiving DS3/E3 OOF Defect H 0004 0000 Receiving DS3/E3 RDI Defect H 0008 0000 Receiving DS3/E3 LOS Defect H 0010 0000 Receiving IDLE Pattern ...

Page 162

Statistics Messages To support performance measurement statistics, several performance counters are realized in TE3-FALC. These counters can be requested anytime with a single message CMD_GET_STATISTICS last clearing of counters ("TOTAL") and/or the count of the last completed 1-second ("1SEC") ...

Page 163

The implemented performance counters are listed in Table 46 and Table 47. Reporting of the counter values is performed in the order they are listed. Table 43 DS3/E3 Framer Performance Counters Near-/ Word Name Far-end PES - NE 0 PSES ...

Page 164

Table 44 PLCP Performance Counters Near-/ Word Name Far-end PLCP_SEFS - NE 0 PLCP_UAS - NE 1 PLCP_FAE - NE 2 PLCP_BIPE - NE 3 PLCP_OOF - NE 4 PLCP_FEBE - FE 5 PLCP_RAI - FE 6 Table 45 ATM ...

Page 165

Table 46 HDLC Performance Counters (cont’d) Word Too long packets 3 Too short packets 4 Bad PPP address fields 5 Bad PPP control fields 6 Overflown packets (rx packets aborted due to buffer overflow) 7 Received valid packets 8 Received ...

Page 166

Command ID: This message causes the firmware to control the reporting of the provided Performance Counters. Input Parameters (optional) Parameter ID STAT_FRAMR_TOTAL P STAT_FRAMR_1SEC P STAT_FRAMR_T1231 P STAT_PLCP_TOTAL P STAT_PLCP_1SEC P STAT_ATM_TOTAL P STAT_ATM_1SEC P STAT_HDLC_TOTAL P STAT_HDLC_1SEC P STAT_BERT_TOTAL ...

Page 167

Command ID: Acknowledgement ID: If activated, this acknowledgement is sent out when the command has been processed. This message provides Performance Counters, when requested so by the host via CMD_GET_STATISTICS Output Parameters STAT_TIMESTAMP P RPT_FRAMR_TOTAL 32 RPT_FRAMR_1SEC 32 RPT_FRAMR_T1231 32 ...

Page 168

Electrical Characteristics 7.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Core supply voltage I/O supply voltage Analog PLL supply voltage Analog LIU supply voltage Voltage on any pin with respect to ground 1) ESD robustness HBM: ...

Page 169

Thermal Package Characteristics Parameter Thermal package resistance junction to ambient without airflow 7.4 DC Characteristics Parameter Input low voltage Input high voltage Maximum analog input voltage Output low voltage Output high voltage Avg. (nom. 1 power ...

Page 170

Parameter Analog transmitter leakage current Analog transmitter output impedance Transmit differential peak voltage of mark (XL1/XL2) Receive differential peak voltage of mark (RL1/RL2) Receiver input impedance (RL1/RL2) Receiver sensitivity (RL1/ RL2) Analog loss of signal threshold E3 1) applies to ...

Page 171

AC Characteristics - DDP All outputs are measured at All inputs are driven The AC testing input/output waveforms are shown below. Test Levels Timing Test Drive Levels ...

Page 172

Intel Demux Mode ...

Page 173

Only applicable when destination address is located at RAM interface. In case of accessing other internal registers or memories additional clock periods can occur according to the availability of internal ressources. 2) not tested in production 3) Only when ...

Page 174

Table 49 Timings for Asynchronous Motorola Mode (cont’d) Timing Description t29 MPDS to MPDTACK delay in case of read t30 delay between MPDTACK and read MPD driven and stable t31 MPR/W setup to MPDS t32 MPR/W hold from MPDS 1) ...

Page 175

Table 50 Timings for Synchronous Motorola Mode Timing Description t33 MPCLK period t34 MPCLK high period t35 MPCLK low period t36 MPTS, MPCS, MPA/MPTSIZ, MPR/W setup to MPCLK rising t37 MPTS, MPCS, MPA/MPTSIZ, MPR/W hold from MPCLK rising t38 MPTA, ...

Page 176

Figure 35 UTOPIA / POS-PHY / UTOPIA-L2X Output Signal Timing Table 51 Transmit UTOPIA ...

Page 177

Table 52 Receive UTOPIA / POS-PHY / UTOPIA-L2X Timing (cont’d) No. Signal Name t52 SRENB, SRADDR(4:0) t53 t54 SRPA, SRD(15:0), SRVAL, SRPRTY, t56 SRSX, SRSOP, SREOP, SRERR, t57 SRMOD 7.5.3 Serial Data Interfaces Timing 7.5.3.1 Digital Line Interface Timing RCLKI ...

Page 178

XCLK XDO Figure 37 Digital Transmit Line Output Timing Table 54 XCLK/XDO Timing Parameter Values No. Parameter t71 XCLK period E3 XCLK period DS3 t72 XCLK high t73 XCLK low t74 XDO delay time Preliminary Data Sheet Electrical Characteristics t71 ...

Page 179

Bitstream Access Interface Timing DTGCKOUT t84 DTFSOUT t82 t83 DTXDIN DRGCKOUT t84 DRFSOUT t84 DRXDOUT Figure 38 Bitstream Access Interface Timing Table 55 Bitstream Access Timing Parameter Values No. Parameter t81 DTCGKOUT, DTGCKIN, DRGCKOUT, DRGCKIN clock period (E3) DTCGKOUT, ...

Page 180

DS3/E3 Overhead Access Interface Timing DOHTCK DTFSOUT DOHTINS DOHTD DOHRCK DRFSOUT DOHRD Figure 39 Overhead Access Interface Timing Table 56 Overhead Access Timing Parameter Values No. Parameter t86 DOHTCK, DOHRCK clock period (DS3, E3) t87 DOHTINS, DOHTD setup time ...

Page 181

Table 57 Reset Timing Number Parameter t91 POR pulse width Preliminary Data Sheet Electrical Characteristics Limit Values min. typ. 500 164 TE3-FALC PEF 3460 E Unit max. ns 2001-11-30 ...

Page 182

Main Clock (CLKIN) Timing Table 58 CLKIN Timing Parameter Values No. Parameter t101 CLKIN period CLKIN frequency CLKIN Clock accuracy 7.5.6 JTAG Interface TCK t112 TMS t112 TDI TDO TRST Figure 40 Boundary-Scan Test Interface Timing Diagram Table 59 ...

Page 183

Analog Line Interface 7.5.7.1 Pulse Template E3 V 1.0 0.5 0 Figure 41 E3 Pulse Shape at Transmitter Output Table 60 E3 Pulse Mask No. Parameter Nominal peak voltage of a mark (pulse) Peak voltage of a space (no ...

Page 184

Pulse Template DS3 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.5 Figure 42 DS3 Pulse Shape at the Cross Connect Point (450 ft.) ...

Page 185

Table 62 DS3 Pulse Mask (ANSI T1.404) Time T -0.36 -0.36 T +0.36 T +0.36 Time T -0.68 -0.68 T +0.36 T +0.36 Table 63 DS3 Pulse Mask (GR-499-CORE) Time -0.85 T -0.36 -0.36 T +0.36 +0.36 T Time -0.85 ...

Page 186

Capacitances Table 64 Pin Capacitances Parameter 1) Input capacitance 1) Output capacitance 1) Output capacitance 1) not tested in production Preliminary Data Sheet Symbol Limit Values min. max OUT OUTX 169 ...

Page 187

Test Configurations 8.1 JTAG Boundary Scan Mode A test access port (TAP) is implemented in the TE3-FALC. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. ...

Page 188

TE3-FALC are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of the TE3-FALC contains a total 368 scan cells. The desired test mode is ...

Page 189

Package Outlines 9.1 PBGA-272-4 Package PBGA-272-4 (Plastic Ball Grid Array) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Preliminary Data Sheet 172 TE3-FALC PEF 3460 E Package Outlines Dimensions in ...

Page 190

Appendix TE3-FALC comes along with a comprehensive support package available on the Infineon Technologies web site at http://www.infineon.com/t3. 10.1 Documentation Several application notes and technical documentation provide additional information. Online access to supporting information is available on the Internet ...

Page 191

Screenshots of the program are shown in Figure 44 TE3-FALC Configuration Assistant Main Window Figure 45 Configuration Assistant Framer Status and Performance Counters Preliminary Data Sheet Figure 44 and Figure 45 174 TE3-FALC PEF 3460 E Appendix below: 2001-11-30 ...

Page 192

Glossary API Application Programmer’s Interface ATM Asynchronous Transfer Mode BERT Bit Error Rate Test BGA Ball Grid Array (package type) BOM Bit Oriented Message CRC Cyclic Redundency Check DS3 Digital Signal Level 3 DWORD Double Word (32-bit word) FDL ...