CY7C63742-SC Cypress Semiconductor Corporation., CY7C63742-SC Datasheet
CY7C63742-SC
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CY7C63742-SC Summary of contents
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... CY7C63722/23 CY7C63742/43 enCoRe™ USB Combination Low-Speed USB & PS/2 Peripheral Controller Cypress Semiconductor Corporation enCoRe USB™ CY7C63722/23 PRELIMINARY • 3901 North First Street • San Jose CY7C63742/43 • CA 95134 • 408-943-2600 May 25, 2000 ...
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... Auxiliary Input Port ....................................................................................................................20 13.0 USB SERIAL INTERFACE ENGINE (SIE) .................................................................................20 13.1 USB Enumeration ......................................................................................................................21 13.2 USB Port Status and Control ....................................................................................................21 14.0 USB DEVICE ...............................................................................................................................22 14.1 USB Address Register ..............................................................................................................22 14.2 USB Control Endpoint ...............................................................................................................22 14.3 USB Non-Control Endpoints (2) ...............................................................................................23 14.4 USB Endpoint Counter Registers ............................................................................................23 15.0 USB REGULATOR OUTPUT ......................................................................................................24 FOR enCoRe™ USB CY7C63722/23 PRELIMINARY TABLE OF CONTENTS 2 CY7C63742/43 ...
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... Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) ............................................................ 20 Figure 12-8. Port 2 Data Register (Address 0x02) .......................................................................... 20 Figure 13-1. USB Status and Control Register (Address 0x1F) .................................................... 21 Figure 14-1. USB Device Address Register (Address 0x10) .......................................................... 22 Figure 14-2. USB EP0 Mode Register (Address 0x12) .................................................................... 22 FOR enCoRe™ USB CY7C63722/23 PRELIMINARY TABLE OF CONTENTS (continued) LIST OF FIGURES 3 CY7C63742/43 ...
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... Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) ............32 Table 21-1. Interrupt Vector Assignments .......................................................................................34 Table 22-1. USB Register Mode Encoding ......................................................................................37 Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” ...38 Table 22-3. Details of Modes for Differing Traffic Conditions .......................................................39 FOR enCoRe™ USB CY7C63722/23 PRELIMINARY LIST OF FIGURES (continued) LIST OF TABLES 4 CY7C63742/43 ...
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... CPU clock — Internal memory — 256 bytes of RAM — 6 Kbytes of EPROM (CY7C63722, CY7C63742) — 8 Kbytes of EPROM (CY7C63723, CY7C63743) — Interface can auto-configure to operate as PS/2 or USB — No external components for switching between PS/2 and USB modes — ...
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... USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds lower system cost. The CY7C63722/23 and CY7C63742/43 are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embed- ded applications ...
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... Watch Dog Timer Low Voltage Reset 4.0 Pin Configurations CY7C63722/23 18-pin PDIP P0.0 1 P0.1 2 P0.2 3 P0 VSS 7 VPP 8 VREG 9 XTALIN/P2.1 5.0 Pin Assignments CY7C63722/23 CY7C63742/43 Name I/O 18-Pin D–/SDATA, I/O 12 D+/SCLK 13 P0[7:0] I 15, 16, 17, 18 P1[7:0] I XTALIN/P2 XTALOUT OUT VREG/P2.0 8 ...
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... During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY 8 CY7C63742/43 ...
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... EQU 10h • MOV X,3 • MOV A,[x+array] This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY 9 CY7C63742/43 ...
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... ASL 1C 4 ASR 1D 5 RLC 1E RRC 1F 4 RET RETI 80- 90-9F 10 JNC A0-AF 5 JACC B0-BF 5 INDEX 10 CY7C63742/43 operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address 2A 5 ...
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... Capture timer A interrupt Vector 0x0012 Capture timer B interrupt vector 0x0014 GPIO interrupt vector 0x0016 Wake-up interrupt vector Program Memory begins here 0x0018 4 KB 0x0FFF 6 KB PROM ends here (CY7C63722, CY7C63742) 0x17FF ( bytes) 0x1FDF 8 KB PROM ends here (CY7C63723, CY7C63743) 11 CY7C63742/43 ...
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... Top of RAM Memory FOR enCoRe™ USB CY7C63722/23 PRELIMINARY Address 0x00 user selected User Variables 0xE8 USB FIFO for Address A endpoint 2 0xF0 USB FIFO for Address A endpoint 1 0xF8 USB FIFO for Address A endpoint 0 0xFF 12 CY7C63742/43 Program Stack Growth Data Stack Growth ...
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... Rising edge Capture Timer B data register R Falling edge Capture Timer B data register R/W Capture Timer configuration register R Capture Timer status register R/W SPI read and write data register R/W SPI status and control register R/W Internal / External Clock configuration register R/W Processor status and control 13 CY7C63742/43 Function Fig. 12-2 12-3 12-8 21-4 21-5 21-6 21-7 12-4 12-5 12-6 12-7 14-1 14-4 ...
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... FOR enCoRe™ USB CY7C63722/23 PRELIMINARY Clock Doubler Figure 9-1. Clock Oscillator On-chip Circuit R/W R/W R/W Wake-up Low Voltage Timer Adjust Reset Bit 1 Bit 0 Disable 14 CY7C63742/43 XTALOUT XTALIN R/W R/W Precision Internal Clock External USB Clocking Output Oscillator Enable Disable Enable 0 ...
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... For a BOR or LVR, the external oscillator is disabled and Internal Clock mode is activated, followed by a time-out period t for V to stabilize. A WDR does not change the clock mode, and there is no delay for V CC FOR enCoRe™ USB CY7C63722/23 PRELIMINARY 15 CY7C63742/43 START stabilization on a WDR. Note that CC ...
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... CC drops below approximately 2.5V. Since the device MHz) 2–4 ms WDR goes HIGH for 2–4 ms Figure 10-1. Watch Dog Reset (WDR) 16 CY7C63742/ that point, the LVR is deasserted LVR pin voltage drops below V . The LVR can be CC LVR voltage to the device that point, the t ...
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... The wake-up timer runs whenever the wake-up interrupt is enabled, and is turned off whenever that interrupt is disabled. Operation is independent of whether the device is in suspend mode or if the global interrupt bit is enabled. Only the wake-up interrupt enable controls the wake-up timer. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY 17 CY7C63742/43 or ground. Note that this also CC ...
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... Figure 12-1 shows a diagram of a GPIO port pin. Each I/O pin can be configured independently of any other pin. Port 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0 in the CY7C63722/23, or all 8-bits, P1.7 - P1.0 in the CY7C63742/43 parts. Each bit can also be selected as an interrupt source for the microcontroller, as explained in Section 21.3.6. ...
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... R/W P0.7 P0.6 P0 R/W R/W P1.7 P1.6 P1.5 Pins 7:2 only in CY7C63742/43 Note: 1. When performing a read of the Port 0 or Port 1 Data registers, above, only the status of the GPIO pins will be read. The registers content will NOT be read P0.7 Mode0 P0.6 Mode0 P0.5 Mode0 Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) FOR enCoRe™ ...
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... P0.3 Mode1 P1.4 Mode0 P1.3 Mode0 P1.4 Mode1 P1.3 Mode1 D– (SDATA) Reserved State Figure 12-8. Port 2 Data Register (Address 0x02) 20 CY7C63742/ P0.2 Mode1 P0.1 Mode1 P0.0 Mode1 P1.2 Mode0 P1.1 Mode0 P1.0 Mode0 P1.2 Mode1 P1.1 Mode1 P1.0 Mode1 ...
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... Volt above VREG if the VREG CC Enable bit is set the Device Address is enabled (bit 7 of the USB Device Address Register, Figure 14-1 ). FOR enCoRe™ USB CY7C63722/23 PRELIMINARY R/W - R/W Reserved USB Bus Activity 21 CY7C63742/ R/W R/W R/W Control Control Control Bit 2 Bit 1 Bit 0 ...
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... Force D– HiZ, D+ LOW Force D– HiZ, D+ HiZ R/W R/W R/W Device Device Address Address Bit 5 Bit 4 Bit R/W R/W R/W ACK Mode OUT Bit 3 22 CY7C63742/43 Application Any Mode USB Mode [2] PS/2 Mode R/W R/W R/W Device Device Device Address Address Address Bit 2 Bit 1 Bit R/W R/W ...
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... For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY R/W R/W ACK Mode Bit R/W Reserved Byte Count Bit 3 23 CY7C63742/ R/W R/W R/W Mode Mode Mode Bit 2 Bit 1 Bit R/W R/W R/W Byte Count ...
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... The VREG pin can be placed into a high-impedance state, so that a USB pull-up resistor on the D–/SDATA pin will not interfere with PS/2 operation (bit 6, USB Status and Control Register). The PS/2 on-chip support circuitry is illustrated in Figure 16-1 . FOR enCoRe™ USB CY7C63722/23 PRELIMINARY . (Disable USB by clearing the Address Enable bit of the USB Device CC 24 CY7C63742/43 (see Section 24.0 addition, REG ...
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... SPI modes are activated by setting the appropriate bits in the SPI Control Register, as described below. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY Port 2.0 3.3V Regulator V CC PS/2 Pull-up Enable USB - PS/2 Driver Port 2.4 25 CY7C63742/43 200 VREG 1.3 k D+/SCLK D–/SDATA On-chip Off-chip ...
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... USB CY7C63722/23 PRELIMINARY Data Bus Write TX Buffer 8 bit shift register RX Buffer Data Bus Read Figure 17-1. SPI Block Diagram R/W R/W R/W Data I/O [4] Data I/O [3] Figure 17-2. SPI Data Register (Address 0x60) 26 CY7C63742/43 MOSI Master / Slave MISO Control SCK SS 4 Internal SCK 2 1 R/W R/W Data I/O [2] Data I/O [1] Data I/O [0] 0 R/W ...
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... The SPI interrupt is asserted at the same time TCMP is set to 1. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY R/W R/W R/W Mode[0] CPOL Figure 17-3. SPI Control Register (Address 0x61) Function 2 Mbit/s 1 Mbit/s 0.5 Mbit/s 0.0625 Mbit/sec All Communications functions disabled (default) SPI Master Mode SPI Slave Mode reserved 27 CY7C63742/ R/W R/W R/W CPHA SCK Select [1] SCK Select [0] ...
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... For Master Mode, Firmware sets SS, may use any GPIO pin. For Slave Mode active LOW input. P0.5 Data output for master, data input for slave. P0.6 Data input for master, data output for slave. P0.7 SPI Clock: Output for master, input for slave. 28 CY7C63742/43 LSB x LSB Comment ...
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... R Reserved Timer Bit 11 Figure 18-2. Timer MSB Register (Address 0x25 Figure 18-3. Timer Block Diagram 29 CY7C63742/ Timer Timer Bit 2 Bit Timer Timer Bit 10 Bit 9 1.024-ms interrupt 128- s interrupt MHz clock ...
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... Prescaler Mux 8-bit Capture Registers Timer A Rising Edge Time Timer A Falling Edge Time Timer B Rising Edge Time Timer B Falling Edge Time Figure 19-1. Capture Timers Block Diagram 30 CY7C63742/43 1 MHz Clock Capture Timer A Interrupt Request Capture Timer B Interrupt Request ...
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... Falling Falling Bit 5 Bit 4 Bit R/W R/W R/W Prescale Capture B Bit 0 Falling Int Enable Reserved Capture B Falling Event 31 CY7C63742/ Capture A Capture A Capture A Rising Rising Rising Bit 2 Bit 1 Bit Capture A Capture A Capture A Falling Falling Falling ...
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... FOR enCoRe™ USB CY7C63722/23 PRELIMINARY Capture From R/W R/W R/W Low Voltage or Suspend Brown-Out Reset 32 CY7C63742/ MHz) CLK LSB Step Size Range 1 s 256 512 1.024 2.048 4.096 ms 2 ...
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... IRQ Sense bit (Bit 7 in the Processor Status and Control Register). FOR enCoRe™ USB CY7C63722/23 PRELIMINARY R/W R/W R/W Capture SPI Timer A Interrupt Intr. Enable Enable Reserved Reserved 33 CY7C63742/ R/W R/W R/W 1.024 ms 128 s USB Reset / Interrupt Interrupt PS/2 Activity Enable Enable Intr. Enable R/W R/W R/W ...
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... Priority Encoder ROM Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 34 CY7C63742/43 To CPU IRQ Pending CPU (Bit 7, Reg 0xFF) IRQ Global Int Enable Interrupt Sense Enable (Bit 2, Reg 0xFF) Bit Controlled by DI, EI, and CLR RETI Instructions ...
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... The CY7C637xx does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not affected by the interrupt acknowledge process. FOR enCoRe™ USB CY7C63722/23 PRELIMINARY 35 CY7C63742/43 ...
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... P1.3 Intr Polarity Intr Polarity GPIO Interrupt OR Gate Flip Flop (1 input per GPIO pin) 1 Global 1 = Enable GPIO Interrupt 0 = Disable Enable (Bit 6, Register 0x20) Figure 21-8. GPIO Interrupt Diagram 36 CY7C63742/ P0.2 P0.1 Intr Enable Intr Enable Intr Enable P1.2 P1.1 Intr Enable Intr Enable ...
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... This mode is changed by SIE on issuance of ACK --> 0001 NAK ignore An ACK from mode 1101 --> 1100 TX cnt ignore This mode is changed by SIE on issuance of ACK --> 1100 stall ignore NAK check An ACK from mode 1111 --> 111 Ack In - Status Out TX cnt check This mode is changed by SIE on issuance of ACK -->1110 37 CY7C63742/43 . WAKE ...
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... Status bits PID Status bits dval DTOG DVAL COUNT Setup The validity of the received data TX: transmit TX0: transmit 0-length packet RX: receive 38 CY7C63742/43 What the SIE does to Mode bits Interrupt? End Point Mode In Out ACK Response Acknowledge phase completed Int ...
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... UC UC dval DTOG DVAL COUNT Setup valid 1 1 updates UC valid 0 1 updates UC valid updates 1 updates CY7C63742/43 Set End Point Mode In Out ACK response ACK NoChange ignore NoChange ignore NoChange ignore UC ...
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... .................................................................................................................. –0.5V to +7.0V 40 CY7C63742/ NoChange ignore NoChange NAK NoChange ACK Stall Stall NoChange ignore NoChange ...
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... V – CY7C63742/43 Conditions V Note 4 V Note 5.5V, no GPIO loading CC A Oscillator off, D– > 2.8V A Oscillator off, D– > 2. 5.0V, ceramic resonator CC A Any I/O pin [5] mA Cumulative across all ports [5] mA Cumulative across all ports ...
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... MHz 2.2 MHz 125 ns 125 ns – CY7C63742/43 Conditions Internal Clock Mode enabled Internal Clock Mode enabled, Bit 2 of regis- ter 0xF8h is set (Precision USB Clocking) USB Operation, with External ±1.5% Ceramic Resonator or Crystal [12] Enabled Wake-up Interrupt MHz OSC [4] CLoad = 200 pF (10% to 90% ...
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... T CL Figure 25-1. Clock Timing 90% 90% 10% Figure 25-2. USB Data Signal Timing 43 CY7C63742/43 Conditions Time before leading SCK edge SCK to data valid Time after SS LOW to data valid Before first SCK edge After last SCK edge range. CC2 drops below approximately 2.5V. CC 10% ...
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... Figure 25-5. Differential Data Jitter enCoRe™ USB CY7C63722/23 T JR1 Consecutive Transitions + T PERIOD JR1 Paired Transitions PERIOD JR2 Crossover Point Extended Source EOP Width: DEOP Receiver EOP Width: T Points Transitions + T PERIOD xJR1 Paired Transitions PERIOD xJR2 44 CY7C63742/43 T JR2 T EOPT , T EOPR1 EOPR2 ...
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... SCK (CPOL=1) MOSI MSB T T SSU SDO MISO enCoRe™ USB CY7C63722/23 PRELIMINARY (SS is under firmware control in SPI Master mode) T SCKL MSB T MHD Figure 25-6. SPI Master Timing, CPHA=0 T SCKL T SHD MSB Figure 25-7. SPI Slave Timing, CPHA=0 45 CY7C63742/43 LSB LSB T SSH LSB LSB ...
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... SCK (CPOL=1) MSB MOSI T T SSU SHD T SDO1 MISO MSB enCoRe™ USB CY7C63722/23 PRELIMINARY (SS is under firmware control in SPI Master mode) T SCKL T MDO Figure 25-8. SPI Master Timing, CPHA=1 T SCKL T SDO Figure 25-9. SPI Slave Timing, CPHA=1 46 CY7C63742/43 LSB LSB T SSH LSB LSB ...
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... Ordering Information EPROM Ordering Code Size CY7C63722- CY7C63723- CY7C63742- CY7C63743- CY7C63742- CY7C63743- Document #: 38-00944 27.0 Package Diagrams FOR enCoRe™ USB CY7C63722/23 PRELIMINARY Package Name Package Type P3 18-Pin (300-Mil) PDIP P3 18-Pin (300-Mil) PDIP P13 24-Pin (300-Mil) PDIP ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. enCoRe™ USB CY7C63722/23 PRELIMINARY 24-Lead (300-Mil) Molded DIP P13/P13A CY7C63742/43 51-85013-A ...