W219BH Cypress Semiconductor Corporation., W219BH Datasheet
W219BH
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W219BH Summary of contents
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Frequency Generator for Integrated Core Logic Features • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Low jitter and tightly controlled clock skew • Highly integrated device providing clocks required for CPU, core logic, and SDRAM • Two copies ...
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I Pin Definitions Pin Name Pin No. Type REF2x/FS3 PCI0/FS0 11 PCI1/FS1 12 PCI2/FS2 13 PCI3:6 15, 16, 18, 19 3V66_0 48MHz_0 21 48MHz_1/ 22 FS4 SIO/ 23 24_48#MHz PWR_DWN# 29 CPU0:1 ...
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W219B Power-on Output Three-state Reset Timer Figure 1. Input Logic Selection Through Resistor Load Option Overview The W219B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architec- ture platform using graphics integrated ...
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CPU 100 Period CPU 100-MHz SDRAM 100 Period SDRAM 100-MHz Hub-PC 3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock) Power-Down Control W219B provides one PWRDWN# signal ...
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Spread Spectrum Frequency Timing Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic ...
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Start bit Slave Address Ack Data Byte 1 1 bit 8 bits Serial Data Interface The W219B features a two-pin, serial data interface that can be used to configure internal register settings that control par- ticular ...
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Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits Byte 1 - Bits ...
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Byte 3: Reserved Register (1 = Enable Disable) Bit Pin# Bit 7 31 Bit 6 - Bit 5 - Bit 4 - Bit 3 47 Bit 2 - Bit 1 - Bit 0 - Byte 4: Reserved Register ...
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Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 4, Bit Bit 2 Bit 7 Bit 6 SEL_4 SEL_3 SEL_2 SEL_1 ...
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DC Electrical Characteristics DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter V 3.3V Core Supply Voltage DDQ3 V 2.5V I/O Supply Voltage DDQ2 T Storage Temperature S Absolute Maximum DC I/O Parameter ...
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AC Electrical Characteristics T = 0°C to +70° 3.3V±5 DDQ3 f = 14.31818 MHz XTL Parameter Description T Host/CPUCLK Period Period T Host/CPUCLK High Time HIGH T Host/CPUCLK Low Time LOW T Host/CPUCLK Rise Time RISE ...
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Group Skew and Jitter Limits Output Group Pin-Pin Skew Max. CPU 175 ps SDRAM 250 ps APIC 250 ps 48MHz 250 ps 3V66 175 ps PCI 500 ps REF N/A Clock Output Wave 2.0 1.25 2.5V Clocking 0.4 Interface T ...
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Layout Example 3. Document #: 38-07220 Rev. *A PRELIMINARY +3.3V Supply FB VDDQ3 10 F 0.005 ...
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Package Diagram 48-Pin Shrink Small Outline Package (SSOP, 300 mils) Document #: 38-07220 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of ...
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Document Title: W219B Frequency Generator for Integrated Core Logic with 133-MHz FSB Document Number: 38-07220 Issue REV. ECN NO. Date ** 110485 10/21/01 *A 122837 12/21/02 Document #: 38-07220 Rev. *A PRELIMINARY Orig. of Change Description of Change SZV Change ...