MT4LC4M16R6TG-5S Micron Semiconductor Products, MT4LC4M16R6TG-5S Datasheet
MT4LC4M16R6TG-5S
Related parts for MT4LC4M16R6TG-5S
MT4LC4M16R6TG-5S Summary of contents
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... R6 † A12 for N3 version, NC for R6 version. N3 None S* Configuration Refresh None Row Address IT** Column Addressing 4 MEG x 16 EDO DRAM PART NUMBERS PART NUMBER MT4LC4M16R6TG-x MT4LC4M16R6TG MT4LC4M16N3TG-x AA CAC CAS MT4LC4M16N3TG-x S 25ns 13ns 8ns 30ns 15ns 10ns x = speed 1 4 MEG x 16 EDO DRAM www ...
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WE# CASL# CASH# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS 10 BUFFER(10) REFRESH CONTROLLER A0- A11 REFRESH COUNTER ROW- 12 ADDRESS BUFFERS (12) NO. 1 CLOCK RAS# GENERATOR WE# CASL# CASH# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS 9 BUFFER(9) REFRESH CONTROLLER ...
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GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The ...
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DRAM ACCESS (continued) the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE ...
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V IH RAS CAS ROW COLUMN (A) ADDR IOH OPEN V IOL RAS CAS ...
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EDO PAGE MODE (continued) two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have OE# HIGH when CAS# transitions HIGH and t keep OE# HIGH for OEHC thereafter. This ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on V Relative to V ................ -1V to +4. Voltage on NC, Inputs or I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (ambient) A Commercial ......................................... 0°C to +70°C ...
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Icc OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes +3.3V ±0.3V) CC PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (RAS# = CAS 0.2V; DQs may be ...
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CAPACITANCE (Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER Access time from column address Column-address setup ...
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AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row address hold time RAS# ...
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NOTES 1. All voltages referenced This parameter is sampled. V MHz 25° dependent on output loading and cycle CC rates. Specified values are obtained with mini- mum cycle time and ...
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NOTES (continued) 28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 29. Each CASx# must meet minimum pulse width. 30. The last CASx# edge to transition HIGH. 31. Last falling CASx# edge ...
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V IH RAS CRP V CAS ASR V IH ROW ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN ...
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V IH RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...
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WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR ROW WE IOH DQ V IOL ...
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V IH RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR ROW WE OPEN OE# ...
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EDO-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW IL t WCS ...
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WRITE and READ-MODIFY-WRITE cycles RAS CRP CASL#/CASH RAD t ASR t RAH V IH ADDR ROW IOH DQ V ...
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EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH DQ OPEN ...
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V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...
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V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR RAS RPC CASL#/CASH ...
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V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR ROW IOH DQx V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX MIN ...
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RAS RPC CSR V IH CASL CASH WRP TIMING PARAMETERS -5 SYMBOL MIN MAX MIN t CHD ...
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TYP PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal ...