MT48LC16M4A2P-7E Micron Semiconductor Products, MT48LC16M4A2P-7E Datasheet
MT48LC16M4A2P-7E
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MT48LC16M4A2P-7E Summary of contents
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Synchronous DRAM MT48LC16M4A2 – 4 Meg banks MT48LC8M8A2 – 2 Meg banks MT48LC4M16A2 – 1 Meg banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/sdram ...
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... Table 3: 64Mb SDRAM Part Numbers MT48LC16M4A2TG MT48LC16M4A2P MT48LC8M8A2TG MT48LC8M8A2P MT48LC4M16A2TG MT48LC4M16A2P MT48LC4M16A2B4 MT48LC4M16A2F4 Notes: 1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron containing 67,108,864 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 16 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functional Block Diagrams Figure 1: 16 Meg x 4 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 10 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. M 10/07 EN ...
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Figure 2: 8 Meg x 8 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 9 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. M 10/ BANK0 ROW- ...
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Figure 3: 4 Meg x 16 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 8 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. M 10/ BANK0 ROW- ...
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Pin/Ball Assignments and Descriptions Figure 4: Pin Assignment (Top View) 54-Pin TSOP DQ0 - NC DQ0 DQ1 - NC NC DQ2 - NC DQ1 DQ3 - ...
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Table 4: Pin/Ball Descriptions VFBGA TSOP Pin Ball Numbers Numbers Symbol 38 F2 CLK 37 F3 CKE 19 G9 CS# 16, 17, 18 F9, F7, F8 WE#, CAS#, RAS# 39 – x4, x8: DQM 15, 39 E8, F1 x16: DQML, ...
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Table 4: Pin/Ball Descriptions VFBGA TSOP Pin Ball Numbers Numbers Symbol 43, 49 A7, B3, C7 12, 46, A3, B7, C3 14, 27 A9, ...
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The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL- compatible. 3. Provide stable CLOCK signal. Stable clock is defined as ...
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The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length READ and WRITE accesses ...
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Figure 6: Mode Register Definition M11, M10 = “0, 0” to ensure compatibility with future devices. Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access M8 M7 M6– Defined – – – Burst Type Accesses ...
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Table 5: Burst Definition Burst Length Full page (y) Notes: 1. For full-page accesses 1,024 (x4 512 (x8 256 (x16). 2. For A1–A9 (x4), A1–A8 (x8), or A1–A7 (x16) select the ...
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Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 7: CAS Latency COMMAND COMMAND Table 6: CAS Latency Operating Mode The normal operating mode is selected by setting M7 and M8 to ...
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Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following “Operation” on page 20; these tables provide current state/next state information. Table 7: ...
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LOAD MODE REGISTER The mode register is loaded via inputs A0–A11. See mode register heading in “Register Definition” on page 12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command ...
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A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is ...
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Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625µs or less, as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Operation Bank/Row Activation Before any READ or WRITE commands can be issued ...
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Figure 9: Example: Meeting CLK COMMAND READs READ bursts are initiated with a READ command, as shown in Figure 10 on page 22. The starting column and bank addresses are provided with the READ command, and auto precharge is either ...
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Figure 10: READ Command A0–A9: x4 A0–A8: x8 A0–A7: x16 A9, A11: x8 A8, A9, A11: x16 BA0, BA1 Figure 11: CAS Latency COMMAND COMMAND PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. M 10/07 EN CLK CKE HIGH CS# RAS# CAS# ...
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Figure 12: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. M 10/ CLK READ NOP NOP BANK, COL n ...
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Figure 13: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 14 shows the case where the clock frequency allows for bus ...
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A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full- page burst may be truncated with a PRECHARGE command to the same ...
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Figure 17: Terminating a READ Burst CLK COMMAND ADDRESS CLK COMMAND ADDRESS Note: DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 28. The starting column and bank addresses are ...
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An example is shown in Figure 20 on page 29. Data either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore ...
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Figure 20: WRITE-to-WRITE CLK COMMAND ADDRESS TRANSITIONING DATA Note: DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst ...
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Figure 21: Random WRITE Cycles CLK COMMAND ADDRESS Note: Each WRITE command may be to any bank. DQM is LOW. Figure 22: WRITE-to-READ CLK COMMAND ADDRESS Note: The WRITE command may be to any bank, and the READ command may ...
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Figure 23: WRITE-to-PRECHARGE CLK CLK ≥ 15ns DQM COMMAND ADDRESS CLK < 15ns DQM COMMAND ADDRESS Note: DQM could remain LOW in this example if the WRITE burst is a fixed length ...
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Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs ...
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Figure 26: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is ...
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Figure 27: Clock Suspend During WRITE Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Figure 28: Clock Suspend During READ Burst CLK CKE INTERNAL CLOCK COMMAND ADDRESS Note: For this example greater, and DQM ...
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READ with Auto Precharge • Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to ...
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Figure 30: READ With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is HIGH prevent D Figure 31: WRITE With Auto Precharge Interrupted by a READ Internal States Notes: 1. DQM is LOW. PDF: ...
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Figure 32: WRITE With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is LOW. Table 8: Truth Table 2 – CKE Notes 1–4 apply to entire table CKE CKE Current State n Power-Down Self ...
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Table 9: Truth Table 3 – Current State Bank n, Command to Bank n (Notes 1–6 apply to entire table; notes appear below and on next page) Current State CS# RAS# Any Idle ...
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Accessing mode Precharging all: Starts with registration of a PRECHARGE ALL command and ends when 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not ...
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Table 10: Truth Table 4 – Current State Bank n, Command to Bank m (Notes 1–6 apply to entire table; notes appear below and on next page) Current State CS# RAS# Any Idle X X Row ...
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All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. ...
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Electrical Specifications Stresses greater than those listed in Table 11 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 12: Temperature Limits Parameter Operating case temperature: Commercial Industrial Junction temperature: Commercial Industrial Ambient temperature: Commercial Industrial Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figure 33 and Figure 34 ...
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Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. M 10/07 EN 22.22mm 11.11mm 8.00mm 4.00mm 8.00mm ...
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Table 14: DC Electrical Characteristics and Operating Conditions Notes apply to entire table; notes appear on pages 48 and 49; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All ...
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Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 34 apply to entire table; notes appear on pages 48 and 49 Characteristics Parameter Access time from CLK (positive edge) ...
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Table 19: AC Functional Characteristics Notes 11, 34 apply to entire table; notes appear on pages 48 and 49; V Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to ...
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Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used ...
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V IH cannot be greater than one-third of the cycle rate pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock ...
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Timing Diagrams Figure 35: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ...
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Figure 36: Power-Down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active ...
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Figure 37: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM / DQML, DQMH ...
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Figure 38: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ ...
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Figure 39: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge ...
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Figure 40: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW ...
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Figure 41: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE ...
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Figure 42: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ...
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Figure 43: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0–A9, A11 ROW ...
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Figure 44: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE AUTO ...
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Figure 45: READ – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 ...
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Figure 46: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ENABLE AUTO ...
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Figure 47: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0-A9, A11 ROW ROW ...
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Figure 48: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, ...
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Figure 49: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ...
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Figure 50: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW t ...
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Figure 51: Alternating Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, A11 ROW ...
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Figure 52: WRITE – Full-Page Burst CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 ...
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Figure 53: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 t AS ...
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Package Dimensions Figure 54: 54-Pin Plastic TSOP II (400 mil) PIN # 0. 1.00 10.16 ±0.08 11.76 ±0.20 +0.03 0.15 -0.02 Notes: 1. All dimensions are in millimeters. 2. Package width and length do not ...
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Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42. BALL A9 6.40 3.20 3.20 Notes: 1. ...
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