MT46V16M16P-75Z Micron Semiconductor Products, MT46V16M16P-75Z Datasheet
MT46V16M16P-75Z
Related parts for MT46V16M16P-75Z
MT46V16M16P-75Z Summary of contents
Page 1
Double Data Rate (DDR) SDRAM MT46V64M4 – 16 Meg banks MT46V32M8 – 8 Meg banks MT46V16M16 – 4 Meg banks Features • +2.5V ±0.2V ...
Page 2
Table 1: Key Timing Parameters CL = CAS (READ) latency; MIN clock rate with 50% duty cycle (-75E, -75Z 2.5 (-6, -6T, -75), and (-5B) Clock Rate (MHz) Speed Grade CL ...
Page 3
Figure 1: 256Mb DDR SDRAM Part Numbers MT46V Configuration FBGA Part Marking System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see ...
Page 4
Table of Contents State Diagram ...
Page 5
State Diagram Figure 2: Simplified State Diagram Power applied Note: This diagram represents operations within a single bank only and does not capture concur- rent operations in other banks. PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 256Mb DDR: Rev. O, Core DDR: ...
Page 6
Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an inter- face designed to transfer two data words per clock cycle at the ...
Page 7
Automotive Tempature The automotive temperature (AT) option adheres to the following specifications: • 16ms refresh rate • Self refresh not supported • Ambient and case temperatures cannot be less than –40°C or greater than +105°C PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - ...
Page 8
Functional Block Diagrams The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a 4-bank DRAM. Figure 3: 64 Meg x 4 Functional Block Diagram CKE CK# CK Control CS# logic ...
Page 9
Figure 4: 32 Meg x 8 Functional Block Diagram CKE CK# CK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTERS 15 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER 2 10 Figure 5: 16 Meg x 16 Functional Block ...
Page 10
Pin and Ball Assignments and Descriptions Figure 6: 66-Pin TSOP Pin Assignments (Top View DQ0 DQ1 ...
Page 11
Figure 7: 60-Ball FBGA Ball Assignments (Top View REF REF DQ14 DQ12 DQ10 DQ8 V REF PDF: 09005aef80768abb/Source: ...
Page 12
Table 4: Pin and Ball Descriptions FBGA TSOP Numbers Numbers Symbol K7, L8, L7, 29, 30, 31, A0, A1, A2, M8, M2, L3, 32, 35, 36, A3, A4, A5, L2, K3, K2, 37, 38, 39, A6, A7, A8, J3, K8, ...
Page 13
Table 4: Pin and Ball Descriptions (continued) FBGA TSOP Numbers Numbers Symbol B7, D7, D3, 5, 11, 56, DQ0–DQ2 B3 62 DQ3 E3 51 DQS E7 16 LDQS E3 51 UDQS F8 B2, D2, ...
Page 14
Package Dimensions Figure 8: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ±0.075 TYP PIN #1 ID Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is ...
Page 15
Figure 9: 60-Ball FBGA (8mm x 14mm) Seating plane A 0.12 A 60X Ø0.45 Solder ball material: SAC305. Dimensions apply solder balls post- reflow on Ø0.33 NSMD ball pads. 11 CTR 1 TYP Notes: 1. Package ...
Page 16
Figure 10: 60-Ball FBGA (8mm x 12.5mm) Seating plane A 0.12 A 60X Ø0.45 Solder ball material: eutectic or SAC305. Dimensions apply to solder balls post- reflow on Ø0. NSMD ball pads. 11 CTR 1 TYP Notes: ...
Page 17
Electrical Specifications – I Table 6: I Specifications and Conditions (x4, x8: -5B, -6, -6T, -75E, -7Z, -75) - Die Revision F Only +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, ...
Page 18
Table 7: I Specifications and Conditions (x16: -5B, -6, -6T, -75E, -75Z, -75) - Die Revision G Only +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on ...
Page 19
Table 8: I Specifications and Conditions (x4, x8, x16: -5B, -6, -6T) - Die Revision K Only +2.6V ±0.1V 0°C ≤ T ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages ...
Page 20
Electrical Specifications – DC and AC Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above ...
Page 21
Table 11: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) Notes: 1–5, 17 apply to the entire table; Notes appear on page 35; V Parameter/Condition Supply voltage I/O supply voltage I/O reference voltage I/O termination voltage (system) ...
Page 22
Figure 10: Input Voltage Waveform Transmitter Notes Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: ...
Page 23
Table 13: Clock Input Operating Conditions Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Parameter/Condition Clock input mid-point voltage: CK and CK# Clock input voltage ...
Page 24
Table 14: Capacitance (x4, x8 TSOP) Note: 14 applies to the entire table; Notes appear on page 35 Parameter Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) Delta input capacitance: Command and address Delta input capacitance: CK, CK# Input/output capacitance: DQ, ...
Page 25
Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
Page 26
Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) (continued) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Write recovery time Internal ...
Page 27
Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
Page 28
Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...
Page 29
Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-6T) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
Page 30
Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-6T) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...
Page 31
Table 21: Electrical Characteristics and Recommended AC Operating Conditions (-75E) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
Page 32
Table 21: Electrical Characteristics and Recommended AC Operating Conditions (-75E) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write preamble setup ...
Page 33
Table 22: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
Page 34
Table 22: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...
Page 35
Table 23: Electrical Characteristics and Recommended AC Operating Conditions (-75) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
Page 36
Table 23: Electrical Characteristics and Recommended AC Operating Conditions (-75) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...
Page 37
Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I Output ...
Page 38
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK REF 17. Inputs are not recognized as valid until ...
Page 39
The input capacitance per pin group will not differ by more than this maximum amount for any given device. 31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). Figure 12: Derating Data ...
Page 40
The full driver pull-up current variation from MIN to MAX process; temperature 38d. The driver pull-up current variation within nominal limits of voltage and temper- 38e. The full ratio variation of MAX to MIN pull-up and pull-down current should ...
Page 41
The driver pull-up current variation, within nominal voltage and temperature 39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should 39f. The full ratio variation of the nominal pull-up to pull-down current should be Figure 15: ...
Page 42
RPST end point and but specify when the device output is no longer driving ( t ( RPRE). 45. During initialization, V Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the ...
Page 43
Table 26: Normal Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 ...
Page 44
Table 27: Reduced Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 ...
Page 45
Commands Tables 28 and 29 provide a quick reference of available commands. Two additional Truth Tables—Table 30 on page 44 and Table 31 on page 45—provide current state/next state information. Table 28: Truth Table 1 – Commands CKE is HIGH ...
Page 46
Table 30: Truth Table 3 – Current State Bank n – Command to Bank n Notes: 1–6 apply to the entire table; Notes appear below Current State CS# RAS# CAS# Any Idle L L Row active L ...
Page 47
Refreshing: Starts with registration of an AUTO REFRESH command and ends when • Accessing mode register: Starts with registration of an LMR command and ends when • Precharging all: Starts with registration of a PRECHARGE ALL command and ends ...
Page 48
This table describes alternate bank operation, except where noted (that is, the current state is for bank n, and the commands shown are those allowed to be issued to bank m, assuming that bank such a ...
Page 49
Table 33: Truth Table 5 – CKE Notes 1–6 apply to the entire table; Notes appear below CKE CKE Current State n Power-down Self refresh L H Power-down Self refresh H L All banks idle Bank(s) active ...
Page 50
ACTIVE (ACT) The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access, like a read or a write, as shown in Figure 17. The value on the BA0, BA1 inputs selects ...
Page 51
READ The READ command is used to initiate a burst read access to an active row, as shown in Figure 18 on page 49. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs ...
Page 52
WRITE The WRITE command is used to initiate a burst write access to an active row as shown in Figure 19. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai and configuration, ...
Page 53
PRECHARGE (PRE) The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks as shown in Figure 20. The value on the BA0, BA1 inputs selects the bank, and the ...
Page 54
Operations INITIALIZATION Prior to normal operation, DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures, other than those specified, may result in undefined operation. To ensure device operation, the DRAM must be initialized as described ...
Page 55
Figure 21: INITIALIZATION Flow Diagram Step PDF: 09005aef80768abb/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B ...
Page 56
Figure 22: INITIALIZATION Timing Diagram ( ( ) ) VTD REF ) ) ( ( CK ...
Page 57
REGISTER DEFINITION Mode Register The mode register is used to define the specific DDR SDRAM mode of operation. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in ...
Page 58
Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 23 on page 55. The burst length determines the maximum ...
Page 59
CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set (-5B only) ...
Page 60
Table 35: CAS Latency Speed -5B -6/-6T -75E -75Z -75 Operating Mode The normal operating mode is selected by issuing an LMR command with bits A7–An each set to zero and bits A0–A6 set to the desired values. A DLL ...
Page 61
Figure 25: Extended Mode Register Definition Notes the most significant row address bit from Table 2 on page 2. 2. The reduced drive strength option is available only on Design ...
Page 62
Figure 26: Example: Meeting T0 T1 CK# CK Command ACT NOP Row Address Bank x BA0, BA1 READ During the READ command, the value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, ...
Page 63
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 31 on page 66. The BURST TERMINATE latency is equal to the CL, that is, the BURST TERMINATE command should be issued x ...
Page 64
Figure 27: READ Burst T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ ...
Page 65
Figure 28: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
Page 66
Figure 29: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
Page 67
Figure 30: Random READ Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
Page 68
Figure 31: Terminating a READ Burst T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK READ Command Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n ...
Page 69
Figure 32: READ-to-WRITE T0 CK# CK Command READ Bank, Address Col n DQS CK# CK Command READ Bank, Address Col n DQS CK# CK READ Command Bank a, Address Col n DQS DQ DM ...
Page 70
Figure 33: READ-to-PRECHARGE T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ Notes: ...
Page 71
Figure 34: Bank READ – Without Auto Precharge CKE Command NOP ACT Row Address A10 Row BA0, ...
Page 72
Figure 35: x4, x8 Data Output Timing – DQ (first data no longer valid) DQ (first data no longer valid) All DQ and DQS collectively t Notes the lesser DQSQ is derived at each ...
Page 73
Figure 36: x16 Data Output Timing – CK# CK LDQS (last data valid (first data no longer valid (last data valid) ...
Page 74
Figure 37: Data Output Timing – CK (MIN) DQS or LDQS/UDQS 3 DQ (last data valid) DQ (first data valid) All DQ values collectively 4 Notes: 1. READ command with issued at T0. t ...
Page 75
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of ...
Page 76
Figure 38: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following ...
Page 77
Figure 39: Consecutive WRITE-to-WRITE T0 CK# CK WRITE Command Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are ...
Page 78
Figure 40: Nonconsecutive WRITE-to-WRITE Command Address t DQSS (NOM) Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following Three ...
Page 79
Figure 42: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ ...
Page 80
Figure 43: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ ...
Page 81
Figure 44: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...
Page 82
Figure 45: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ ...
Page 83
Figure 46: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ ...
Page 84
Figure 47: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...
Page 85
Figure 48: Bank WRITE – Without Auto Precharge CKE NOP 1 ACT Command Row Address A10 Row BA0, ...
Page 86
Figure 49: WRITE – DM Operation CKE ACT NOP Command Row Address A10 Row BA0, BA1 Bank ...
Page 87
Figure 50: Data Input Timing CK# CK DQS DQ DM Notes: 1. WRITE command issued at T0 DSH (MIN) generally occurs during t 3. DSS (MIN) generally occurs during 4. For x16, LDQS controls the lower byte and ...
Page 88
Figure 51: Bank READ – with Auto Precharge CKE ACT NOP Command Address Row A10 Row IS IH BA0, BA1 Bank ...
Page 89
Figure 52: Bank WRITE – with Auto Precharge CKE Command NOP ACT Address Row A10 Row BA0, ...
Page 90
Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends Figure 53: Auto Refresh Mode ...
Page 91
NOPs for 200 additional clock cycles before applying a READ. Any command other than a READ can be performed reset. NOP or DESELECT commands must be issued during the Self refresh is not supported on ...
Page 92
Power-down (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend ...
Page 93
Figure 55: Power-Down Mode CK# CK CKE Command Address DQS DQ DM Notes: 1. Once initialized this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is ...