SST39SF020A-70-4C-PH Silicon Storage Technology, Inc, SST39SF020A-70-4C-PH Datasheet
SST39SF020A-70-4C-PH
Available stocks
Related parts for SST39SF020A-70-4C-PH
SST39SF020A-70-4C-PH Summary of contents
Page 1
... Fast Erase and Byte-Program: – Sector-Erase Time (typical) – Chip-Erase Time (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A 8 seconds (typical) for SST39SF040 • Automatic Write Timing – Internal V Generation PP • ...
Page 2
... Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector- Erase operation will be ignored. ...
Page 3
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification tor- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit ( During the internal Program or Erase operation, any con- ...
Page 4
... DQ0 DQ0 FIGURE SSIGNMENTS FOR ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 X-Decoder Control Logic SST39SF010A 32-pin PLCC ...
Page 5
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification SST39SF040 SST39SF020A SST39SF010A A11 A11 A11 A13 A13 A13 A14 A14 A14 A17 A17 NC WE# WE# WE A18 NC NC A16 A16 A16 A15 A15 A15 A12 ...
Page 6
... Erase Standby Write Inhibit Product Identification Software Mode 1. X can but no other value ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 -A address lines will select the sector for SST39SF040 18 CE# OE# WE ...
Page 7
... SST Manufacturer’s ID= BFH, is read with SST39SF010A Device ID = B5H, is read with A SST39SF020A Device ID = B6H, is read with A SST39SF040 Device ID = B7H, is read with A 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” ...
Page 8
... Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 V = 5.0V±10% DD Limits Min Max Units Test Conditions ...
Page 9
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification AC CHARACTERISTICS TABLE EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output ...
Page 10
... ADDRESS A MS-0 CE# OE WE# HIGH-Z DQ 7-0 Note Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE EAD YCLE IMING 5555 ADDRESS OE# CE# DQ 7-0 AA SW0 Note Most significant address ...
Page 11
... for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE 6: CE# C ONTROLLED ADDRESS A MS-0 CE# OE# WE Note Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE ATA OLLING IMING ©2001 Silicon Storage Technology, Inc. INTERNAL PROGRAM OPERATION STARTS ...
Page 12
... ADDRESS A MS-0 CE# OE# WE Note: Toggle bit output is always high first Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE OGGLE IT IMING 5555 ADDRESS A MS-0 CE# OE WE# DQ 7-0 AA SW0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met ...
Page 13
... Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10 Sector Address Most significant address for SST39SF010A for SST39SF020A, and A 18 for SST39SF040 FIGURE 10: WE# C ONTROLLED Three-byte sequence for ...
Page 14
... ADDRESS A 14-0 DQ 7-0 AA CE# OE WE# SW0 FIGURE 12 OFTWARE XIT AND ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 5555 IDA T WHP SW1 SW2 R ESET 14 Preliminary Specification 398 ILL F10.0 S71147-02-000 5/01 398 ...
Page 15
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification V IHT INPUT V ILT AC test inputs are driven at V (3.0V) for a logic “1” and V IHT and outputs are V (1.5V) and FIGURE 13 NPUT UTPUT TO DUT FIGURE 14 EST OAD XAMPLE © ...
Page 16
... FIGURE 15 YTE ROGRAM LGORITHM ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of ...
Page 17
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification Internal Timer Byte Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 16 AIT PTIONS ©2001 Silicon Storage Technology, Inc. Toggle Bit Byte Program/Erase Initiated Read byte Read same No byte No Does DQ 6 ...
Page 18
... Wait T IDA Read Software ID FIGURE 17 OFTWARE RODUCT ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: F0H ...
Page 19
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification Chip-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 10H ...
Page 20
... U = Unencapsulated die Temperature Range C = Commercial = 0°C to +70° Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed Version Device Density 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit Voltage S = 5.0±10%V SST39SF040-70-4C-PH SST39SF010A-70-4C-PH SST39SF020A-70-4C-PH 20 Preliminary Specification S71147-02-000 5/01 398 ...
Page 21
... Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Preliminary Specification PACKAGING DIAGRAMS TOP VIEW .485 .495 .447 Optional .453 Pin #1 Identifier .042 .048 .042 .048 .585 .547 .595 .553 .050 BSC. Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...
Page 22
... SST ACKAGE ODE Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2001 Silicon Storage Technology, Inc. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 1.645 1.655 .170 .200 .120 .150 .016 ...