IC41LV16256-50T INTEGRATED CIRCUIT SOLUTION, IC41LV16256-50T Datasheet

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IC41LV16256-50T

Manufacturer Part Number
IC41LV16256-50T
Description
Manufacturer
INTEGRATED CIRCUIT SOLUTION
Datasheet
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Document Title
256Kx16 bit Dynamic RAM with EDO Page Mode
Revision History
0C
0A
0B
Revision No
History
Initial Draft
Revise for typo on page 20
Add Pb-free package
Draft Date
August 9,2001
December 18,2001
April 23,2004
Remark
1

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IC41LV16256-50T Summary of contents

Page 1

... IC41C16256 IC41LV16256 Document Title 256Kx16 bit Dynamic RAM with EDO Page Mode Revision History Revision No History 0A Initial Draft 0B Revise for typo on page 20 0C Add Pb-free package The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products ...

Page 2

... GND DESCRIPTION ICSI The IC41C16256 and IC41LV16256 is a 262,144 x 16- bit high-performance CMOS Dynamic Random Access Memo- ries. The IC41C16256 offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short per 16-bit word ...

Page 3

... IC41C16256 IC41LV16256 FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0-A8 Integrated Circuit Solution Inc. DR018-0C 04/23/2004 WE CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY 262,144 CONTROL LOGIC I/O0-I/O15 ...

Page 4

... IC41C16256 IC41LV16256 TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write (1,2) EDO Page-Mode Read 1st Cycle: (2) 2nd Cycle: Any Cycle: EDO Page-Mode Write ...

Page 5

... The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS) . The IC41C16256 and IC41LV16256 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical man- ner to the single CAS input on the other 256K x 16 DRAMs ...

Page 6

... IC41C16256 IC41LV16256 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage CC I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A Industrial Operationg Temperature T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 7

... IC41C16256 IC41LV16256 ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Standby Current: TTL Standby Current: CMOS Operating Current ...

Page 8

... IC41C16256 IC41LV16256 AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC t Access Time from RAS RAC t Access Time from CAS CAC t Access Time from Column-Address AA t RAS Pulse Width RAS t RAS Precharge Time RP t CAS Pulse Width ...

Page 9

... IC41C16256 IC41LV16256 AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Column-Address Setup Time to CAS ACH Precharge during WRITE Cycle t OE Hold Time from WE during OEH READ-MODIFY-WRITE cycle t Data-In Setup Time (15, 22 Data-In Hold Time (15, 22 READ-MODIFY-WRITE Cycle Time ...

Page 10

... IC41C16256 IC41LV16256 Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V ...

Page 11

... IC41C16256 IC41LV16256 READ CYCLE RAS t CRP UCAS-LCAS t ASR ADDRESS Row WE I/O OE Note referenced from rising edge of RAS or CAS, whichever occurs last. OFF Integrated Circuit Solution Inc. DR018-0C 04/23/2004 RAS t CSH t RSH CAS CLCH RCD RAD RAL ...

Page 12

... IC41C16256 IC41LV16256 EARLY WRITE CYCLE (OE = DON'T CARE) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC CAH t ACH Column t CWL t RWL t WCR t t WCS WCH DHR ...

Page 13

... IC41C16256 IC41LV16256 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP UCAS-LCAS t ASR ADDRESS Row WE I/O OE Integrated Circuit Solution Inc. DR018-0C 04/23/2004 t RWC t RAS t CSH t t CAS RCD RAD RAH ASC CAH Column t RWD t t CWD RCS t AWD ...

Page 14

... IC41C16256 IC41LV16256 EDO-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t t ASR ADDRESS Row t RAH WE Open I/O OE Note can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both PC measurements must meet the t specifications RASP t t CSH ...

Page 15

... IC41C16256 IC41LV16256 EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP UCAS/LCAS t RAD t ASR ADDRESS Row t RAH WE I/O OE Integrated Circuit Solution Inc. DR018-0C 04/23/2004 t RASP t CSH CAS, CAS, RCD CLCH CLCH ACH ACH ASC CAH ASC Column Column ...

Page 16

... IC41C16256 IC41LV16256 EDO-PAGE-MODE READ-WRITE CYCLE RAS t t CRP RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RWD t RCS WE t RAC Open I/O OE Note for LATE write cycles only CAS to rising edge of CAS. Both measurements must meet the t ...

Page 17

... IC41C16256 IC41LV16256 EDO-PAGE-MODE READ-EARLY-WRITE CYCLE RAS t t CRP RCD UCAS/LCAS ASR RAD t t ASC RAH ADDRESS Row t RCS WE t RAC Open I/O OE Integrated Circuit Solution Inc. DR018-0C 04/23/2004 (Psuedo READ-MODIFY WRITE) t RASP t CSH CAS CAS CAH ASC ...

Page 18

... IC41C16256 IC41LV16256 AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE RAS RAS RAS-ONLY REFRESH CYCLE RAS RAS RAS t CRP UCAS/LCAS t ASR ADDRESS I CSH t t RCD CAS RAD t t RAH ASC Column t RCS RAC ...

Page 19

... IC41C16256 IC41LV16256 CBR REFRESH CYCLE (Addresses; WE DON'T CARE) RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE (1) RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH referenced from rising edge of RAS or CAS, whichever occurs last. ...

Page 20

... IC41C16256 IC41LV16256 ORDERING INFORMATION (Pb-free) IC41C16256 Commercial Range: 0°C to 70°C Speed (ns) Order Part No. 25 IC41C16256-25K(G) IC41C16256-25T(G) 35 IC41C16256-35K(G) IC41C16256-35T(G) 50 IC41C16256-50K(G) IC41C16256-50T(G) 60 IC41C16256-60K(G) IC41C16256-60T(G) ORDERING INFORMATION (Pb-free) IC41C16256 Industrial Range: -40°C to 85°C Speed (ns) Order Part No. 25 IC41C16256-25KI(G) IC41C16256-25TI(G) 35 IC41C16256-35KI(G) IC41C16256-35TI(G) 50 IC41C16256-50KI(G) ...

Page 21

... IC41LV16256-60T(G) ORDERING INFORMATION (Pb-free) IC41LV16256 Industrial Range: -40°C to 85°C Speed (ns) Order Part No. 35 IC41LV16256-35KI(G) IC41LV16256-35TI(G) 50 IC41LV16256-50KI(G) IC41LV16256-50TI(G) 60 IC41LV16256-60KI(G) IC41LV16256-60TI(G) NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, Integrated Circuit Solution Inc. DR018-0C 04/23/2004 Package 400mil SOJ(Pb-free) 400mil TSOP-2(Pb-free) 400mil SOJ(Pb-free) ...

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