SII1161CT100 Silicon Image, SII1161CT100 Datasheet
SII1161CT100
Related parts for SII1161CT100
SII1161CT100 Summary of contents
Page 1
Technology SiI 1161 PanelLink Receiver Data Sheet Document # SiI-DS-0096-D ® ...
Page 2
... Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. ...
Page 3
SiI 1161 PanelLink Receiver Data Sheet SiI 1161 Pin Diagram ....................................................................................................................1 Functional Description .................................................................................................................2 Electrical Specifications...............................................................................................................3 Absolute Maximum Conditions ................................................................................................................... 3 Normal Operating Conditions ..................................................................................................................... 3 Digital I/O Specifications ............................................................................................................................. 3 General DC Specifications .......................................................................................................................... 4 General AC Specifications .......................................................................................................................... ...
Page 4
Table 1. DC Parametric Specifications ........................................................................................................... 4 Table 2. General AC Specifications ................................................................................................................ 5 Table 3. SiI 161B Mode DC Specifications ..................................................................................................... 7 Table 4. SiI 161B Mode AC Specifications ..................................................................................................... 8 Table 5. SiI 1161 Mode DC Specifications.................................................................................................... 10 ...
Page 5
SiI 1161 PanelLink Receiver Data Sheet General Description SiI 1161 The receiver uses technology to support high-resolution displays up to UXGA (25-165MHz). This receiver supports up to true color panels (24 bits per pixel, 16M colors) with both one and ...
Page 6
Functional Description The SiI 1161 is a DVI 1.0 compliant PanelLink receiver in a compact package. It provides bits for data output, and allows for panel support up to UXGA. Figure 1 shows the functional blocks of ...
Page 7
SiI 1161 PanelLink Receiver Data Sheet Electrical Specifications Absolute Maximum Conditions Symbol V Supply Voltage 3. Input Voltage I V Output Voltage O T Junction Temperature J T Storage Temperature STG Notes 1. Permanent device damage may occur ...
Page 8
General DC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter V Differential Input Voltage ID Single Ended Amplitude I Power-down Current PD I Receiver Supply Current PDO with Outputs Powered Down I Receiver Supply Current CCR for Active ...
Page 9
SiI 1161 PanelLink Receiver Data Sheet General AC Specifications Symbol Parameter T Intra-Pair (+ to -) Differential Input Skew DPS T Channel to Channel Differential Input Skew CCS T Worst Case Differential Input Clock Jitter IJIT tolerance R ODCK Cycle ...
Page 10
Compatibility Mode Selection Specifications The 1161 design provides new features that were not available on previous TMDS receiver series. To utilize the new features and ensure backwards compatibility, two mode selections have been defined. SiI 161B (Compatible) Mode: This mode ...
Page 11
SiI 1161 PanelLink Receiver Data Sheet The output drive specifications in the Compatible mode are equivalent to the drive on the SiI 161B part. Strap option: ST=0 (Low Drive Strength) Parameter Data and Controls I Output High Drive OHD I ...
Page 12
SiI 161B (Compatible) Mode AC Specifications AC timings are provided here in setup/hold format at 165MHz for ease of direct comparison to the SiI 161B part. Timing specifications in Table 4 apply to worst-case one pixel per clock mode. For ...
Page 13
SiI 1161 PanelLink Receiver Data Sheet Q[23:0] DE ODCK Figure 3. Output Loading in SiI 161B Mode SiI 1161 (Programmable) Mode DC Specifications The SiI 1161 provides an internal register, accessible via I control and ODCK pins. This arrangement allows ...
Page 14
Program Option: ST=0 (Low Drive Strength) Parameter Data and Controls I Output High Drive OHD I Output Low Drive OLD ODCK and DE I Output High Drive OHC I Output Low Drive OLC 1 Program Option: ST=1 (High Drive ...
Page 15
SiI 1161 PanelLink Receiver Data Sheet SiI 1161 (Programmable) Mode AC Specifications SiI 1161 Mode AC timings are based on “Clock to Output” (CK2OUT) timing measurements. This methodology provides a precise means of calculating setup and hold at any frequency ...
Page 16
Calculating Setup and Hold Times Output setup and hold times between video output clock (ODCK) and video data (including HSYNC, VSYNC and DE) are functions of the worst case duty cycle specification for ODCK and the worst case clock to ...
Page 17
SiI 1161 PanelLink Receiver Data Sheet Table 7 shows the calculations required for determining setup and hold timings using the clock period T specific to the clock frequency, also bringing in the clock duty cycle as required when OCK_INV=0. The ...
Page 18
Actual setup and hold times can be derived from the clock period at the operating frequency of interest. Clock duty cycle must also be taken into account when calculating setup and hold times. Setup Time to ODCK: Hold Time from ...
Page 19
SiI 1161 PanelLink Receiver Data Sheet Timing Diagrams SiI 1161 2.0 V Figure 8. Receiver Clock Cycle/High/Low Times RX0 RX1 RX2 Figure 9. Channel-to-Channel Skew Timing 2.0 V 10pF / 5pF 0 LHT Figure 7. Digital Output Transition ...
Page 20
CK2OUT VSYNC HSYNC ODCK (OCK_INV=0) Figure 10. Receiver Clock-to-Output Delay and Duty Cycle Limits RXC+ QE[23:0], QO[23:0], DE, CTL[3:1] VSYNC, HSYNC Figure 11. Output Signals Disabled Timing from Clock Inactive RXC+ SCDT SiI-DS-0096-D = max 50% T ...
Page 21
SiI 1161 PanelLink Receiver Data Sheet PD# QE[23:0], QO[23:0], DE, CTL[3:1], VSYNC, HSYNC Figure 13. Output Signals Disabled Timing from PD# Active DE SCDT DE SCDT Figure 14. SCDT Timing from DE Inactive or Active Internal ODCK * 2 ODCK ...
Page 22
SDA T SCL Figure 16. I VCC max VCC min VCC T RESET PD# 2 Figure 17 Reset Timing at Power-Up or Prior to first I SiI-DS-0096-D I2CDVD 2 C Data Valid Delay (driving Read Cycle data) PD# ...
Page 23
SiI 1161 PanelLink Receiver Data Sheet Pin Descriptions Output Pins Pin Name Pin # Type QE23- See Out Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode and to the first 24-bit pixel data ...
Page 24
Configuration Pins Pin Name Pin # Type MODE 99 In Mode Select Pin. Used to select between drop-in strap-selected operation, or register- programmable operation. To activate register-programmable operation, tie both pin 99 and pin 7 LOW. Refer to Selecting SiI ...
Page 25
SiI 1161 PanelLink Receiver Data Sheet Power and Ground Pins Pin Name Pin # VCC 6,38,67 GND 5,39,68 OVCC 18,29,43,57,78 OGND 19,28,45,58,76 AVCC 82,84,88,95 AGND 79,83,87,89,92 PVCC 97 PGND 98 Type Description Power Digital Core VCC, must be set to ...
Page 26
Feature Information HSYNC De-jitter Function HSYNC de-jitter enables the SiI 1161 to operate properly even when the HSYNC signal contains jitter. Pin 1 is used to enable or disable this circuit. Tying this pin high enables the HSYNC de-jitter circuitry ...
Page 27
SiI 1161 PanelLink Receiver Data Sheet Slave Interface The SiI 1161 slave state machine supports only byte read and write. Page mode is not supported. The 7-bit binary 2 address of the I C machine is 0x76. ...
Page 28
TFT Panel Data Mapping Table 9 summarizes the output data mapping in one pixel per clock mode for the SiI 1161. This output data mapping is dependent upon the PanelLink transmitters having the exact same type of input data mappings. ...
Page 29
SiI 1161 PanelLink Receiver Data Sheet Note: SiI143B, SiI 151B, SiI 153B and SiI 1161 all have the same pinout. The pin assignments shown in the following tables should also be used for these other receivers. Table 11. One Pixel ...
Page 30
Table 12. Two Pixels per Clock Input/Output TFT Mode TFT VGA Output 24-bpp 18-bpp B0 – – – – – – – – – ...
Page 31
SiI 1161 PanelLink Receiver Data Sheet Table 13. 24-bit One Pixel per Clock Input with 24-bit Two Pixels per Clock Output TFT Mode TFT VGA Output 24-bpp ...
Page 32
Table 14. 18-bit One Pixel per Clock Input with 18-bit Two Pixels per Clock Output TFT Mode TFT VGA Output 18-bpp DIE0 DIE1 B0 DIE2 B1 DIE3 B2 DIE4 B3 DIE5 B4 DIE6 B5 DIE7 DIE8 DIE9 G0 DIE10 G1 ...
Page 33
SiI 1161 PanelLink Receiver Data Sheet Table 15. Two Pixels per Clock Input with One Pixel per Clock Output TFT Mode TFT VGA Output 24-bpp 18-bpp B0 – – – – – ...
Page 34
Table 16. Output Clock Configuration by Typical TFT Panel Application PIX OCK_INV SiI-DS-0096-D ODCK (frequency/data latch edge) 0 divide negative 1 divide positive 0 divide negative 1 ...
Page 35
SiI 1161 PanelLink Receiver Data Sheet Design Recommendations The following sections describe recommendations for robust board design with this PanelLink receiver. Designers should include provision for these circuits in their design, and adjust the specific passive component values according to ...
Page 36
... SiI 1161 by using the OCK_INV, ST, and CKST selections to meet system timing requirements. This is possible because the SiI 1161 part has better timing characteristics in most applications. Contact your Silicon Image representative for additional application-specific suggestions. SiI-DS-0096-D resistor on the PD# pin is sufficient to provide the Ω ...
Page 37
SiI 1161 PanelLink Receiver Data Sheet Adjusting Equalizer and Bandwidth The SiI 1161 provides access to several internal registers that can be set to optimize the connection to a variety of source devices and accommodate a range of cable lengths. ...
Page 38
Register Access Default Name VND_IDL RO 0x01 VND_IDH RO 0x00 DEV_IDL RO 0x00 DEV_IDH RO 0x00 DEV_REV RO 0x00 EQ_DATA RW 0xD CKST RW 0 OCK_INV RW 0 STAG_OUT LBW RW 00 ZONEO RO 0 ...
Page 39
SiI 1161 PanelLink Receiver Data Sheet Decoupling and bypass capacitors are also involved with power supply connections, as described in detail in Figure 26. Figure 24. Voltage Regulation using LM317 For the purposes of efficient power supply design, the relative ...
Page 40
VCCPIN Figure 26. Decoupling and Bypass Schematic The values shown in Table 20 are recommendations for noise suppression in the 1-2MHz range that should be adjusted according to the noise characteristics of the specific board-level design. Pins in one group ...
Page 41
SiI 1161 PanelLink Receiver Data Sheet Receiver Layout The receiver chip should be placed as close as possible to the input connector that carries the TMDS signals. For a system using the industry-standard DVI connector (see http://www.ddwg.org), the differential lines ...
Page 42
... Board designers driving into another clocked chip should take this into account in their timing analysis. Silicon Image recommends the use of STAG_OUT# and the two pixels per clock mode whenever possible. Adjusting Output Timings for Loading ...
Page 43
... T4 ∆T T1 All dimensions are in millimeters. ePad is centered on the package center lines. Silicon Image recommends that the ePad be electrically grounded on the PCB. The ePad must not be electrically connected to any other voltage level except ground (GND). A clearance of at least 0.25mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads to avoid any electrical shorts ...
Page 44
Application-Specific Thermal Calculations The junction temperature of the silicon is the limiting factor to the performance of this device. Junction temperature may be calculated as shown in Equation 1, where the input factors are: T Ambient temperature. A Θ Junction-to-Ambient ...
Page 45
... Footprint G1 Footprint L1 Lead Length b Lead Width c Lead Thickness e Lead Pitch Dimensions in millimeters. Overall thickness A=A1+A2. A Device Device Number 2 Standard SiI1161CT100 Pb-free SiI1161CTU Legend Description LLLLLL.LLLL Lot Number YY Year of Mfr WW Week of Mfr TTTTTT Trace Code mm Maturity Code 0: engineering samples =1: pre-production >1: production SiI-DS-0096-D ...
Page 46
... Silicon Image. Inc. Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA SiI-DS-0096-D SiI 1161 PanelLink Receiver Tel: (408) 616-4000 Fax: (408) 830-9530 E-mail: salessupport@siimage.com Web: www.siliconimage.com 42 Data Sheet ...