SII3114CT176 Silicon image, SII3114CT176 Datasheet
SII3114CT176
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SII3114CT176 Summary of contents
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SiI3114 PCI to Serial ATA Controller Data Sheet Document # SiI-DS-0103-D Data Sheet ...
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... Maximum Ratings; Corrected inconsistent sentences (minor fixes including mistyping) A2 10/30/03 Updated Section 8.2 Serial ATA Device Initialization Corrected part number on cover page to SiI3114CT176 from SiI3114CT144 A3 02/05/04 Updated the part number on cover page to SiI3114 from SiI3114CT176; Added Part Ordering A4 04/05/05 Number in section 4. Package Drawing; Updated Marking Specification in section 4. Package Drawing B 07/21/06 Corrected inconsistent sentences (minor fixes including mistyping) ...
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... PCI Status – PCI Command.................................................................................................................. 27 PCI Class Code – Revision ID .............................................................................................................. 28 BIST – Header Type – Latency Timer – Cache Line Size..................................................................... 28 Base Address Register 0....................................................................................................................... 29 Base Address Register 1....................................................................................................................... 29 © 2007 Silicon Image, Inc. Table of Contents iii SiI3114 PCI to Serial ATA Controller Data Sheet ...
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... FIFO Valid Byte Count and Control – Channel X .................................................................................. 57 System Configuration Status – Command ............................................................................................ 57 System Software Data Register ............................................................................................................ 58 Flash Memory Address – Command + Status....................................................................................... 58 Flash Memory Data ............................................................................................................................... 59 EEPROM Memory Address – Command + Status................................................................................ 59 EEPROM Memory Data ........................................................................................................................ 60 SiI-DS-0103-D iv Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Slumber Power Management Mode ...................................................................................................... 83 Hot Plug Support .................................................................................................................................... 84 FIS Support ................................................................................................................................................. 85 FIS Summary ........................................................................................................................................... 85 FIS Transmission .................................................................................................................................... 86 FIS Reception .......................................................................................................................................... 86 FIS Types Not Affiliated with Current ATA/ATAPI Operations ............................................................ 89 BIST Support ......................................................................................................................................... 89 BIST Signals.......................................................................................................................................... 89 DMA Setup ............................................................................................................................................ 89 © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller v Data Sheet SiI-DS-0103-D ...
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... Data Sheet ATA Command Decoding........................................................................................................................... 90 Data Modes .............................................................................................................................................. 90 ATA Commands....................................................................................................................................... 90 Obsolesced Commands ........................................................................................................................ 92 Read/Write Long.................................................................................................................................... 92 Vendor Specific Command Support ..................................................................................................... 93 Silicon Image's Vendor Specific Commands......................................................................................... 93 Vendor Specific, Reserved, Retired and Obsolesced Commands ....................................................... 94 Definitions.............................................................................................................................................. 94 Scheme ................................................................................................................................................. 94 Bridge Device Vendor Specific Commands ......................................................................................... 96 Feature Set/Command Summary ......................................................................................................... 96 VS Lock ................................................................................................................................................. 97 VS Unlock Vendor Specific ...
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... Figure 1. Address Lines During Configuration Cycle ..................................................................................... 3 Figure 2. Flash Memory Timing ...................................................................................................................... 7 Figure 3. SiI3114 Pin Diagram...................................................................................................................... 13 Figure 4. Package Drawing – 176 TQFP ..................................................................................................... 19 Figure 5. Marking Specification – SiI3114CT176 ......................................................................................... 20 Figure 6. Marking Specification – SiI3114CTU............................................................................................. 20 Figure 7. SiI3114 Block Diagram .................................................................................................................. 21 Figure 8. Auto-Initialization from Flash Timing ............................................................................................. 22 Figure 9. Auto-Initialization from EEPROM Timing....................................................................................... 23 Figure 10. Hot Plug Logic State Diagram ..................................................................................................... 84 © ...
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... Table 45. Protocol Code Encoding Scheme............................................................................................... 112 Table 46. Vendor Specific Protocol Code (in Alphabetical Order) .............................................................. 113 Table 47. Vendor Specific Protocol Code (by Protocol Code).................................................................... 114 Table 48. Vendor Specific Protocol Code (in Alphabetical Order) .............................................................. 115 SiI-DS-0103-D List of Tables ......................................................................... 53 H ......................................................................... 55 H viii Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Overview The Silicon Image SiI3114 is a single-chip solution for a PCI to Serial ATA controller. It accepts host commands through the PCI bus, processes them, and transfers data between the host and Serial ATA devices. It can be used to control four independent Serial ATA channels. Each channel has its own Serial ATA bus and will support one Serial ATA device ...
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... The SiI3114 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as required during device operation PCI slave, the SiI3114 responds to the following PCI bus operations: • I/O Read • I/O Write SiI-DS-0103-D 2 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... To ensure awareness of these deviations by anyone considering the use of the SiI3114, we have included an Errata section at the end of this specification. Please ensure that the Errata section is © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 11 10 ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet carefully reviewed also important that you have the most current version of this specification. If there are any questions, please contact Silicon Image, Inc. Electrical Characteristics Device Electrical Characteristics Specifications are for Commercial Temperature range, 0 ...
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... Tx differential skew TX_SKEW clock frequency TX_DC_FREQ skew clock frequency TX_AC_FREQ skew © 2007 Silicon Image, Inc. Table 3. SATA Interface DC Specifications Condition Terminated by 50 Ohms. Tx Swing Value = 00 Terminated by 50 Ohms. Tx Swing Value = 01 Terminated by 50 Ohms. Tx Swing Value = 10 Terminated by 50 Ohms. ...
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... Table 7. PCI 33 MHz Timing Specifications 6 Silicon Image, Inc. Limits Min Typ Max - 4 6 Limits Min Typ Max - 25 - 100 0.7xVDDX - - - - 0.3xVDDX -100 +100 - - Limits Unit Min Max 2.0 11.0 ns 2.0 11 28 © 2007 Silicon Image, Inc. Unit ps rms ps rms ps ps Unit MHz V V ppm ns % ...
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... Input Hold Time H Flash Memory Timing Specifications PCICLK FL_ADDR FL_CS_N FL_RD_N PCICLK FL_ADDR FL_CS_N FL_WR_N © 2007 Silicon Image, Inc. Table 8. PCI 66 MHz Timing Specifications CYC FLASH READ TIMING CYC CYC FLASH WRITE TIMING Figure 2. Flash Memory Timing ...
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... SerDes Power GND - Analog Ground I - Channel 2 Differential Receive - Channel 2 Differential Receive +ve PWR - 1.8V SerDes Power GND - Analog Ground O - Channel 3 Differential Transmit + Channel 3 Differential Transmit -ve GND - Analog Ground PWR - 1.8V SerDes Power GND - Analog Ground 8 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... FL_ADDR[15] 77 FL_ADDR[16] 78 LED2 79 FL_ADDR[17] 80 FL_ADDR[18] 81 FL_CS_N 82 VDDI 83 VSSI 84 LED3 85 FL_DATA[00] 86 FL_DATA[01] © 2007 Silicon Image, Inc. Table 9. SiI3114 Pin Listing (continued) Type Internal Description Resistor I - Channel 3 Differential Receive - Channel 3 Differential Receive +ve PWR - 1.8V SerDes Power N internal connection PWR - 3.3 Volt Power GND ...
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... Internal Core Power GND - Ground PWR - 3.3 Volt Power GND - Ground I/O - PCI Address/Data I/O - PCI Address/Data I/O - PCI Address/Data I/O - PCI Address/Data I/O - PCI Address/Data I/O - PCI Command/Byte Enable I/O - PCI Frame I/O - PCI Initiator Ready I/O - PCI Parity Error PWR - 3.3 Volt Power 10 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... VDDO 169 VSSO 170 GPIOEN 171 TEST_MODE 172 TMS 173 TCK 174 TDO 175 TDI 176 TRSTN © 2007 Silicon Image, Inc. Table 9. SiI3114 Pin Listing (continued) Type Internal Description Resistor GND - Ground I/O - PCI Stop I/O - PCI Device Select I/O - PCI Target Ready ...
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... I-Schmitt Note: PCI pins are 5V tolerant. SiI-DS-0103-D Table 10. Pin Types Description I Input Pin with LVTTL Thresholds Input Pin with Schmitt Trigger O Output Pin T Tri-state Output Pin I/O Bi-directional Pin OD Open Drain Output Pin 12 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... VSSO 169 GPIOEN 170 TEST_MODE 171 TMS 172 TCK 173 TDO 174 TDI 175 TRSTN 176 © 2007 Silicon Image, Inc. SiI3114 Top View Figure 3. SiI3114 Pin Diagram 13 SiI3114 PCI to Serial ATA Controller Data Sheet 88 VDDO 87 FL_DATA2 86 FL_DATA1 85 FL_DATA0 84 LED3 ...
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... Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access input, PCI_DEVSEL_N indicates to a master whether any device on the bus has been selected. SiI-DS-0103-D 14 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Clock Signal provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals (except PCI_RST_N, and PCI_INTA_N) are sampled on the rising edge of PCI_CLK. All other timing parameters are defined with respect to this edge. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 15 ...
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... Pin Number: 81 Flash chip select signal, active low Serial EEPROM Interface Signals Pin Name: EEPROM_SDAT Pin Number: 47 Serial Interface (I2C) data line Pin Name: EEPROM_SCLK Pin Number: 48 Serial Interface (I2C) clock SiI-DS-0103-D 16 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Pin Number: 25 PLL 1.8 V Power supply Pin Pin Name: VDDX Pin Number: 20 Oscillator 1.8 V Power supply Pin Pin Name: GNDA Pin Numbers 11, 14, 16, 23, 26, 29, 31, 35, 38, 40 SerDes Ground © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 17 Data Sheet SiI-DS-0103-D ...
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... Pin Number: 24 External reference resistor pin for termination calibration. This pin provides the additional function of selecting frequency of the clock source. For 25MHz, a 1K, 1% resistor is connected to ground. For 100MHz, a 4.99K, 1% resistor is connected to ground. SiI-DS-0103-D 18 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Silicon Image, Inc. Package Drawing 176 PIN # Part Ordering Number: SiI3114CT176 (176 pin TQFP standard package) SiI3114CTU (176 pin TQFP universal package) © 2007 Silicon Image, Inc. 22.0 SQ NOM 20.0 SQ NOM 0.18 NOM 0.40 NOM Dimensions in millimeters Figure 4. Package Drawing – 176 TQFP 19 SiI3114 PCI to Serial ATA Controller ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Package Markings Figure 5. Marking Specification – SiI3114CT176 Figure 6. Marking Specification – SiI3114CTU SiI-DS-0103-D 20 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Silicon Image, Inc. Block Diagram The SiI3114 contains the major logic modules shown in Figure 7. PCI Interface © 2007 Silicon Image, Inc. Bus Data Interface FIFO PCI DMA Engine PCI DMA Engine Bus Data Interface FIFO Bus Data Interface FIFO PCI DMA ...
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... Data Signature = 55 H PCI Device ID [23:16] PCI Device ID [31:24] PCI Class Code [15:08] PCI Class Code [23:16] PCI Sub-System Vendor ID [07:00] 22 Silicon Image, Inc. and 7FFFE ), checking for the correct data 7FFFB 7FFFA 7FFF1 7FFF0 D04 D05 D14 D15 © 2007 Silicon Image, Inc. ...
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... Table 14. Auto-Initialization from EEPROM Timing Symbols Parameter © 2007 Silicon Image, Inc. Description PCI Sub-System Vendor ID [15:08] PCI Sub-System ID [23:16] PCI Sub-System ID [31:24] SATA PHY Config [07:00] (default: 0xB0) SATA PHY Config [15:08] (default: 0x80) SATA PHY Config [23:16] (default: 0x00) SATA PHY Config [31:24] (default: 0x20) ...
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... PCI Class Code [23:16] PCI Sub-System Vendor ID [07:00] PCI Sub-System Vendor ID [15:08] PCI Sub-System ID [23:16] PCI Sub-System ID [31:24] SATA PHY Config [07:00] (default: 0xB0) SATA PHY Config [15:08] (default: 0x80) SATA PHY Config [23:16] (default: 0x00) SATA PHY Config [31:24] (default: 0x20) 24 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Reserved Reserved © 2007 Silicon Image, Inc. Table 16. SiI3114 PCI Configuration Space Register Name 16 15 PCI Class Code Header Type Latency Timer Base Address Register 0 Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 ...
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... Bit [31:16] : Device ID (R/W) – Device ID. This value in this bit field is determined by any one of three options: 1) This field defaults to 0x3114 to identify the device as a Silicon Image SiI3114. 2) Loaded from an external memory device external memory device — flash or EEPROM — is present with the correct signature, the Device ID is loaded from that device after reset. See “Auto- Initialization” ...
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... SiI3114 does not support VGA Palette Snooping. • Bit [04] : Mem Wr & Inv (R) – Memory Write and Invalidate Enable. This bit is hardwired indicate that the SiI3114 does not support Memory Write and Invalidate. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller Reserved for Medium decode timing ...
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... FIFO is larger than the value programmed in this register. SiI-DS-0103-D PCI Class Code Header Type Latency Timer . resulting in a time granularity of 16 clocks Silicon Image, Inc. Revision set the three bytes are system H for the production chip. H Cache Line Size © 2007 Silicon Image, Inc. ...
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... Bit [31:03] : Base Address Register 2 (R/W). This register defines the I/O Space base address for Channel 1 task file registers. • Bit [02:00] : Base Address Register 2 (R). This bit field is not used and is hardwired to 001 © 2007 Silicon Image, Inc. Base Address Register 0 Base Address Register 1 ...
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... The register bits are defined below. • Bit [31:10] : Base Address Register 5 (R/W). This register defines the Memory Space base address for all Silicon Image driver specific functions. • Bit [09:00] : Base Address Register 5 (R). This bit field is not used and is hardwired to 000 ...
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... Bit [18:01] : Not Used (R). This bit field is hardwired to 00000 range is 512K bytes. • Bit [00] : Exp ROM Enable (R/W) – Expansion ROM Enable. This bit is set to enable the Expansion ROM access. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller Subsystem Vendor set the two bytes are system ...
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... This register defines the various control functions associated with the PCI bus. The register bits are defined below. • Bit [31:02] : Reserved (R). This bit field is hardwired to 00000000 SiI-DS-0103-D Reserved Min Grant Interrupt Pin Reserved . H 32 Silicon Image, Inc. Capabilities Pointer to define the H Interrupt Line . indicate that the H © 2007 Silicon Image, Inc. ...
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... Capabilities List. H • Bit [07:00] : Capability ID (R) – PCI Additional Capability ID. This bit field is hardwired to 01 this Capabilities List is a PCI Power Management definition. © 2007 Silicon Image, Inc. and and Subsystem ID (2F-2E ). ...
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... See “PCI Bus Master – Channel X ” section on page 53 for bit definitions. SiI-DS-0103-D Reserved PPM Data Sel Reserved , Base Address 5, Offset 00 , and Base Address 5, Offset Silicon Image, Inc. Reserved to B Reserved (Note that H © 2007 Silicon Image, Inc. ...
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... This register defines the PRD Table Address register for Channel 1/3 in the SiI3114. The register bits are also mapped to Base Address 4, Offset 0C section on page 54 for bit definitions. © 2007 Silicon Image, Inc. PRD Table Address – Channel 0/2 and Base Address 5, Offset 04 H ...
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... This register defines the system configuration status and command register for the SiI3114. The register bits are also mapped to Base Address 5, Offset 48 for bit definitions. SiI-DS-0103-D Reserved Reserved Reserved Reserved . See “System Configuration Status – Command” section on page Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... This register defines the data register for flash memory interface in the SiI3114. The register bits are also mapped to Base Address 5, Offset 54 . See “Flash Memory Data” section on page 59 for bit definitions. H © 2007 Silicon Image, Inc. System Software Data Reserved . See “Flash Memory Address – Command + Status” ...
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... SiI-DS-0103-D Reserved . See “EEPROM Memory Address – Command + H Reserved . See “EEPROM Memory Data” section on page 60 for bit definitions See “Channel X Task File Configuration + Status” section Silicon Image, Inc. Mem Address Memory Data Reserved © 2007 Silicon Image, Inc. ...
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... This register provides the indirect access addressed by the BA5 Indirect Address register. The use of indirect access must be enabled by setting bit 1 of the Configuration register (40 © 2007 Silicon Image, Inc. .See “Channel X Task File Configuration + Status” section on H Reserved , 2C0– ...
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... Register Name 16 15 Sector Count Features (W) Error (R) Device+Head Cylinder High Sector Count Features (W) Error (R) Data (dword access) Device+Head Cylinder High 40 Silicon Image, Inc. Access Type 00 Data R/W Cylinder Low R/W Data (byte access) Data (word access) Cylinder Low © 2007 Silicon Image, Inc ...
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... See “Channel X Task File Register 2” section on page 63 for bit definitions. The H value in the “shadow” Channel 0/2 Device Select bit is used to select the Task File registers for either Channel 0 (Master; bit Channel 2 (Slave; bit is 1). © 2007 Silicon Image, Inc. Register Name 16 15 ...
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... Register Name 16 15 Features (W) Sector Count Error (R) Device+Head Cylinder High Sector Count Features (W) Error (R) Data (dword access) Device+Head Cylinder High 42 Silicon Image, Inc. Access Type 00 Data R/W Cylinder Low R/W Data (byte access) Data (word access) Cylinder Low © 2007 Silicon Image, Inc. ...
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... See “Channel X Task File Register 2” section on page 63 for bit definitions. The H value in the “shadow” Channel 1/3 Device Select bit is used to select the Task File registers for either Channel 1 (Master; bit Channel 3 (Slave; bit is 1). © 2007 Silicon Image, Inc. Register Name 16 15 ...
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... PRD Table Address – Channel 1/3 Software PRD Table Address – Channel 0/2 and Base Address 5, Offset Silicon Image, Inc. Access Type 00 PCI Bus Master Command – R/W Channel 0/2 R/W PCI Bus Master Command – R/W Channel 1/3 R/W Reserved . See “PRD Table Address – H © 2007 Silicon Image, Inc. ...
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... Channel X ” section on page 54 for bit definitions. Writing to this register address results in both the Channel 1 and Channel 3 PRD Table Address registers being written. The read value is selected based upon the “shadow” Channel 1/3 Device Select bit. © 2007 Silicon Image, Inc. Reserved PRD Table Address – Channel 1/3 ...
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... PCI Bus Master R/W Command2 – Channel 0 - PCI Bus Master R/W Command2 – Channel FIFO Rd Request R/W Control – Channel 0 FIFO Rd Request R/W Control – Channel 1 System Command R/W R/W R/W Flash Memory R/W Data R/W EEPROM Memory R/W Data R/W - FIFO Byte0 Read R Pointer – Channel 0 © 2007 Silicon Image, Inc. ...
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... Reserved Channel Starting Sector H Number2 Channel Cmd © 2007 Silicon Image, Inc. Register Name 16 15 FIFO Byte3 Read FIFO Byte2 Write Pointer – Channel Pointer – Channel 0 0 FIFO Port – Channel 1 Reserved FIFO Byte1 Read FIFO Byte0 Write Pointer – ...
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... RxFIS3 (channel 0) RxFIS4 (channel 0) RxFIS5 (channel 0) RxFIS6 (channel 0) Reserved SControl (channel 1) SStatus (channel 1) SError (channel 1) 48 Silicon Image, Inc. Access Type 00 Channel 1 TF R/W Sector Count 2 Ext R/W Channel 1 R/W Cmd + Status R/W R/W R/W R/W Channel 1 Data R/W Transfer Mode - - R/W R R/C R R/W R/W R/W R R/W R/W R/C © 2007 Silicon Image, Inc. ...
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... Status – Channel H 1 214 H 218 Reserved H 21C H 220 H 224 H 228 H 22C H 230 H © 2007 Silicon Image, Inc. Register Name 16 15 SActive (channel 1) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMisc (channel 1) PHY Configuration (same as 144 ) ...
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... Pointer – Channel 2 R/W - FIFO Byte0 Read R Pointer – Channel 3 FIFO Byte2 Read R Pointer – Channel 3 R/W Channel 2 TF Data Channel 2 TF R/W Cylinder Low R/W Reserved R/W R/W Reserved Channel 2 TF R/W Cylinder Low2 Channel 2 TF R/W Sector Count 2 Ext R/W Channel 2 R/W Cmd + Status R/W R/W R/W R/W © 2007 Silicon Image, Inc. ...
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... H 32C H 330 H 334 H 338 H 33C H 340 H 344 H 348 H © 2007 Silicon Image, Inc. Register Name 16 15 Reserved Reserved Reserved Channel 3 TF Channel 3 TF Sector Features Channel 3 Count TF Error Channel 3 TF Channel 3 TF Device+Head Cylinder High Channel 3 TF Device Control Auxiliary Status ...
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... Reserved SIEN (channel 3) SFISCfg (channel 3) Reserved Reserved Reserved Reserved RxFIS0 (channel 3) RxFIS1 (channel 3) RxFIS2 (channel 3) RxFIS3 (channel 3) RxFIS4 (channel 3) RxFIS5 (channel 3) RxFIS6 (channel 3) Reserved 52 Silicon Image, Inc. Access Type 00 R R/W R/W R/C R R/W R/W R/W R © 2007 Silicon Image, Inc. ...
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... Table 23. Software Data Byte, Base Address 5, Offset 00 Bit Location [13:12] [11:10] [09:08] • Bit [07:04] : Reserved (R). This bit field is reserved and returns zeros on a read. © 2007 Silicon Image, Inc the SiI3114. The register bits are defined below registers; this bit is reserved in the Channel 1 (offset registers ...
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... SiI-DS-0103-D ) register; this bit is reserved in the Channel 0 (offset H ), and Channel 3 (offset 208 ) registers PRD Table Address H Reserved for Chnl 1/3 ) and Channel 2 (offset 210 H ) registers Silicon Image, Inc. Software ) registers; this bit field is reserved in H © 2007 Silicon Image, Inc. ...
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... If this bit is cleared while the PCI bus master is active, the operation will be aborted and the data discarded. While this bit is set, accessing Channel X Task File or PIO data registers will be terminated with Target-Abort. © 2007 Silicon Image, Inc. Default Description ...
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... Transfer Mode. Under generic mode, this bit field is reserved and returns zeros on a read. • Bit [15:00] Byte Count Low (R). This bit field reflects the current DMA byte count value. SiI-DS-0103-D H PRD Address H 56 Silicon Image, Inc. Byte Count Low © 2007 Silicon Image, Inc. ...
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... Bit [31:26] : Reserved (R). This bit field is reserved and returns zeros on a read. • Bit [25] : Chnl3 Int Block (R/W) – Channel3 Interrupt Block. This bit is set to block interrupts from Channel 3. © 2007 Silicon Image, Inc. H FIFO Valid Byte Count Reserved indicates empty, while a value of 100 ...
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... Reserved This register defines the address and command/status register for flash memory interface in the SiI3114. The register bits are defined below. SiI-DS-0103-D System Software Data Reserved 58 Silicon Image, Inc. Memory Address © 2007 Silicon Image, Inc. ...
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... This register defines the address and command/status register for EEPROM memory interface in the SiI3114. The register bits are defined below. • Bit [31:29] : Reserved (R). This bit field is reserved and returns zeros on a read. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller GPIO Control ...
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... The system can read from or write to this register for direct access to the data FIFO between the PCI bus and Channel X . While DMA is active, reading this register will be terminated with Target-Abort. SiI-DS-0103-D Reserved H FIFO Port 60 Silicon Image, Inc. Memory Data © 2007 Silicon Image, Inc. ...
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... Bit [23:16] : FIFO Byte 3 Rd Pointer (R). This bit field provides the read pointer for Byte 3. • Bit [15:08] : FIFO Byte 2 Wr Pointer (R). This bit field provides the write pointer for Byte 2. • Bit [07:00] : FIFO Byte 2 Rd Pointer (R). This bit field provides the read pointer for Byte 2. © 2007 Silicon Image, Inc. H FIFO Byte 1 Rd Pointer ...
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... Bit [23:16] : Task File Device+Head (R/W). This bit field defines the Channel X Task File Device and Head register. SiI-DS-0103-D H Sector Count Features (W) Error (R) Data (dword access) H Device+Head Cylinder High 62 Silicon Image, Inc. Data (byte access) Data (word access) Cylinder Low © 2007 Silicon Image, Inc. ...
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... This register defines the read ahead data port for PIO transfers on Channel X in the SiI3114. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. © 2007 Silicon Image, Inc. H Device Control ...
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... Bit [15:08] : Task File Cylinder High (R/W). This bit field defines the Channel X Task File Cylinder High register. • Bit [07:00] : Task File Cylinder Low (R/W). This bit field defines the Channel X Task File Cylinder Low register. SiI-DS-0103-D H Sector Count Features H Device+Head Cylinder High 64 Silicon Image, Inc. Reserved Cylinder Low © 2007 Silicon Image, Inc. ...
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... This register defines the task file configuration and status register for Channel X in the SiI3114. The register bits are defined below. • Bit [31:16] : Reserved (R). This bit field is reserved and defaults to 0x6515. © 2007 Silicon Image, Inc. H Cylinder Low Ext Start Sector Ext ...
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... Bit [01:00] : Device 0 Transfer Mode (R/W) – Channel X Device 0 Data Transfer Mode. This bit field is used to set the data transfer mode during PCI DMA transfer: 00 transfer. SiI-DS-0103-D H Reserved Silicon Image, Inc. = PIO transfer DMA PIO transfer DMA B B © 2007 Silicon Image, Inc. ...
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... Bit [03:00] : DET – This field controls host adapter device detection and interface initialization. Value Action 0000 No action 0001 ATA Reset is generated until another value is written to the field 0100 No action others Reserved, no action © 2007 Silicon Image, Inc. / 380 H PMP Reserved 67 SiI3114 PCI to Serial ATA Controller Data Sheet IPM SPD DET ...
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... PHY in offline mode as a result of the interface being disabled or running in a BIST loopback mode others Reserved, no action Until a device is detected (IPM and DET fields become nonzero), the SiI3114 issues a COMRESET every 100 milliseconds. SiI-DS-0103-D / 384 H Reserved 68 Silicon Image, Inc. IPM SPD DET © 2007 Silicon Image, Inc. ...
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... Recovered communications error P Protocol error R Reserved T Non-recovered Transient data integrity error © 2007 Silicon Image, Inc. / 388 Table 25. SError Register Bits (DIAG Field) Description Latched decode error or disparity error from the Serial ATA PHY Latched CRC error from the Serial ATA PHY N/A, always 0 ...
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... Bit [21] : Scr_dis (R/W)– This bit disables the scrambling of data on the serial ATA bus. This is used only for debugging purposes and should not be changed by the user SiI-DS-0103-D / 38C H H SActive bits / 3C0 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Bit[20] : Reserved. The value of this bits should not be changed from their defaults otherwise erratic operation may result • Bit[19] : Tx_Swing_1: This bit, together with Tx_Swing_0, sets the nominal output amplitude for the Transmitter © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 8 7 ...
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... Bit [16 – This bit enables an interrupt upon the assertion of the N bit in the DIAG field of the SError register. • Bit [15:00] : Reserved (R). This bit field is reserved and returns zeros on a read. SiI-DS-0103-D Nominal Output Swing 500mV 600mV 700mV 800mV / 3C8 Silicon Image, Inc. Reserved © 2007 Silicon Image, Inc. ...
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... H H Access Type: Read Reset Value: 0x????_???? These registers contain 7 dwords from a Serial ATA FIS reception. © 2007 Silicon Image, Inc. / 3CC H H –1F8 / 360 – ...
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... PCI bus by the SiI3114 controller. If interrupt driven operation is not desired, set bits [23:22] of the System Configuration Status and Command register to block interrupts from reaching the PCI bus. SiI-DS-0103-D 74 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Ultra DMA Mode Ultra DMA Mode 6 H • Programming bits [31:24] in the Channel x Task File Register 1 register with the value = EF • Wait for the command to complete (see above). © 2007 Silicon Image, Inc SiI3114 PCI to Serial ATA Controller Data Sheet ...
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... Continue to write data via the Channel x Task File Register 0 register until the expected number of sectors of data per interrupt are written. Wait until a channel interrupt (bit 11 in the Channel x Task File Timing + Configuration + Status register is set). SiI-DS-0103-D 76 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Register 0 register, until the expected number of sectors of data per interrupt are read. Repeat the read operation steps until all data for the read command has been transferred or an error has been detected. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 77 ...
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... Clear bit 17 in the PCI Bus Master – Channel x register. This bit is set if an error occurred during the previous DMA access. Clear bit 18 in the PCI Bus Master – Channel x register. This bit is set if an interrupt occurred during the previous DMA access. SiI-DS-0103-D 78 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... ATA Device Initialization” section, virtual DMA read/write operations may be performed by following the programming sequence described below. Note: The watchdog timer feature is compatible with virtual DMA operation. See section 0 for details about using the watchdog timer. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 79 Data Sheet ...
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... Write Multiple command would expect to transfer the lesser of the number of sectors set by the Set Multiple Mode command or the total number of sectors specified by the Write Multiple command. The DMA is setup similarly to the way it is when performing a normal write DMA command, but SiI-DS-0103-D 80 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... PIO type transfer mode before DMA operation is enabled, and must be re- programmed with the DMA/UDMA transfer type used during normal DMA operation once the virtual DMA operation is complete. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 81 ...
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... If operating in Large Block Transfer mode, this field contains the most significant 15-bits of the size of the memory region. 63 When set, this bit indicates that this is the last entry in the PRD table. SiI-DS-0103-D 82 Silicon Image, Inc 210 , or 218 ). © 2007 Silicon Image, Inc. ...
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... PMACK is received the Slumber mode is entered. A PMNAK is ignored; the request remains asserted. The Serial ATA device may initiate slumber mode. This is indicated by the reception of PMREQ_S primitives. Software enables the acknowledgement of this request by setting the IPM value in the SControl register to ‘001x’. © 2007 Silicon Image, Inc. Table 28. Power Management Register Bits 83 ...
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... PHYRDY signal going true causing an interrupt to the host driver (PHYRDY change interrupt, bit 16 of SError register; enabled by bit 16 of SIEN register). SiI-DS-0103-D CR dp_phyrdy=0 go_to_CR Figure 10. Hot Plug Logic State Diagram 84 Silicon Image, Inc. PhyRdy Normal operation dp_phyrdy=1 © 2007 Silicon Image, Inc. ...
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... B8h Reserved BFh Reserved C7h Reserved D4h Reserved D9h Reserved Others Reserved © 2007 Silicon Image, Inc. Table 29. FIS Summary Host to Device Comment Device to Host √ - Support Expanded Registers HOB not sent to device (device dongle ignores HOB received) Can be individually controlled via PCI registers - default to reject √ ...
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... EOF is received. If any error is received, R_ERR will be sent after EOF 01b Reject FIS without interlock. R_ERR will be sent 10b Interlock. This allows the host to examine the first dwords of the FIS to determine whether to accept or reject the FIS 11b Reserved. SiI-DS-0103-D 86 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Upon reception of a supported FIS (FISxxcfg[1:0] = '00'), the Link/Transport Logic responds with R_OK at WTRM (if no error is detected) or R_ERR (if an error is detected) to the downstream device. The host will be notified only as required by the protocol. © 2007 Silicon Image, Inc. Table 31. Default FIS Configurations Configuration Bits ...
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... Accept_IFIS or Reject_IFIS (if not asserted already) before responding. IntrlckFIS will cause an interrupt to the host. knows that the entire FIS is not larger than the size of RxFIS0 to 6 register. an Accept_IFIS (Link/Transport Logic to send R_OK Reject_IFIS (Link/Transport Logic to send R_ERR). 88 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... The host sets the Accept_FIS bit to accept the FIS. The device sends one or more Data FISes. There is no need to report transfer status. The host clears the DMAInEn when the transfer count is exhausted © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 89 Data Sheet ...
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... DAh - ECh - A1h - A3h - E1h - 91h Obsolesced in ATA/ATAPI-6. EDh - DEh - DFh - 00h - A0h - E4h - C8h - C9h Obsolesced Command code supported, decoded as Command Code C8h 25h 48-bit LBA Command C7h - 90 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Smart Enable/Disable Attributes Autosave Smart Execute Off-Line Immediate Smart Read Attribute Thresholds Smart Read Data Smart Read Log Smart Return Status Smart Save Attribute Values Smart Write Log © 2007 Silicon Image, Inc. Command/ Comment Features Codes 26h 48-bit LBA Command 2Fh - 22h Obsolesced command supported (see “ ...
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... C5h - 39h 48-bit LBA Command 30h - 31h Obsolesced Command code supported, decoded as Command Code 30h 34h 48-bit LBA Command 3Ah - 3Bh - 3Ch - (i.e 512 divided by 2 with round up) (i.e., XC divided by 4 with round up) 92 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... The SiI3114 supports most vendor specific commands that utilize existing protocols. Silicon Image's Vendor Specific Commands Silicon Image defines several vendor specific commands (all of which use Expanded Features in 48-bit LBA addressing) to support vendor specific and reserved commands: • VS Unlock Vendor Specific: Unlock the host or device to support vendor specific commands. ...
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... Upon any hardware reset or the Serial ATA COMRESET, or COMINIT, the VS State Machine shall be initialized to the locked state (the "default" state), which shall abort all vendor specific and reserved commands. Soft Reset (via Device Control register bit 2) shall NOT affect the VS State Machine. SiI-DS-0103-D 94 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... ATA device. Note that the lock will take effect in the Serial ATA host and the Serial ATA device even if an ABORT status is reported. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller ...
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... VS Set Command Protocol commands will not follow the protocol set by this command. F1h 87h Set protocol for an individual vendor specific or reserved command. The information is logged in a Command Protocol Table entry. F1h Other than Reserved. above 96 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Previous (Expanded) LBA High Current Previous (Expanded) Device Status 1. The DEV bit usage in the Serial ATA specification must be followed. 2. Error bit shall be ignored. Completion is determined by by BSY = 0 and DRDY = 1 only. © 2007 Silicon Image, Inc F1h D5h ...
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... The Serial ATA device is a native device and responds with an abort. The Serial ATA host will ignore the abort status and shall consider the VS block locked. In other words, regardless of the status reported (aborted or complete), the Serial ATA host and device that support this scheme shall be locked. SiI-DS-0103-D 98 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Previous (Expanded) LBA High Current Previous (Expanded) Device Status 1. The DEV bit usage in the Serial ATA specification must be followed. 2. Error bit shall be ignored. Completion is determined by by BSY = 0 and DRDY = 1 only. © 2007 Silicon Image, Inc F1h 12h ...
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... In other words, regardless of the status reported (aborted or complete), the Serial ATA host and device that support this scheme shall be unlocked to support vendor specific commands. SiI-DS-0103-D 100 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Previous (Expanded) LBA High Current Previous (Expanded) Device Status 1. The DEV bit usage in the Serial ATA specification must be followed. 2. Error bit shall be ignored. Completion is determined by by BSY = 0 and DRDY = 1 only. © 2007 Silicon Image, Inc obs na obs DEV F0h ...
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... In other words, regardless of the status reported (aborted or complete), the Serial ATA host and device that support this scheme shall be unlocked to support reserved commands. SiI-DS-0103-D 102 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Previous (Expanded) LBA High Current Previous (Expanded) Device Status 1. The DEV bit usage in the Serial ATA specification must be followed. 2. Error bit shall be ignored. Completion is determined by by BSY = 0 and DRDY = 1 only. © 2007 Silicon Image, Inc F1h 32h ...
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... In other words, regardless of the status reported (aborted or complete), the Serial ATA host and device that support this scheme shall be unlocked to support individual vendor specific/reserved commands. SiI-DS-0103-D 104 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... LBA High Previous (Expanded) Device Status 1. The DEV bit usage in the Serial ATA specification must be followed. 2. Error bit shall be ignored. Completion is determined by by BSY = 0 and DRDY = 1 only. © 2007 Silicon Image, Inc F1h F0h na Protocol Code (See “Protocols Summary” section) ...
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... In other words, regardless of the status reported (aborted or complete), the Serial ATA host and device that support this scheme shall accept the protocol as valid. SiI-DS-0103-D 106 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Current Previous (Expanded) LBA High Current Previous (Expanded) Device Status 1. The DEV bit usage in the Serial ATA specification must be followed. 2. Error bit shall be ignored. Completion is determined by by BSY = 0 and DRDY = 1 only. © 2007 Silicon Image, Inc F1h 87h Protocol Code (See “ ...
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... Command Code but different Features Codes Features Mask bit is '0', the corresponding Features Code bit will be ignored for comparison. 7-0 00h Reserved for Expanded Features Code. 7-0 00h Reserved for Expanded Features Mask. 108 Silicon Image, Inc. Protocol Code - - - - - © 2007 Silicon Image, Inc. ...
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... Received VS Unlock Individual command 3 Received VS Lock command 4 Otherwise © 2007 Silicon Image, Inc. Table 37. Default State - VS_LOCKED Vendor specific/Reserved commands not supported. All vendor specific and reserved commands shall result in an ABORT status. General Protocol Code shall be 00h. Command Protocol Table initialized with all Command Codes = 00h and all Protocol Codes = 00h ...
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... All other commands shall result in an ABORT status. 110 Silicon Image, Inc. → VS_VS_RSV → VS_RSV_IND → VS_LOCKED → VS_RSV → VS_VS_RSV → VS_VS_IND → VS_LOCKED → VS_IND → VS_VS_RSV_IND → VS_LOCKED → VS_VS_RSV → VS_VS_RSV_IND → VS_LOCKED → VS_VS_IND © 2007 Silicon Image, Inc. ...
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... VS_VS_RSV_IND 1 Received VS Lock command 2 Otherwise © 2007 Silicon Image, Inc. Table 43. VS_RSV_IND On VS Set General Protocol command, set General Protocol Code Set Command Protocol command, update the corresponding Command Protocol Table entry. Commands other than vendor specific or reserved commands shall be executed according to the predefined protocol ...
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... D0h, D1h, Bits 2-1: D8h, D9h 00b - currently defined 01b-11b - reserved. Bit not queued queued. A0h - A1h - Bit 6: B0h, F0h 0 - legacy addressing 1 - 48-bit LBA addressing B1h - B2h - 112 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Read DMA Queued (Ext) Read Long Service Write DMA Write DMA (Ext) Write DMA queued Write DMA queued (Ext) Write Long © 2007 Silicon Image, Inc. Protocol Description Code 00h Abort command. Status =51h and Error = 04h. Command shall not be passed to downstream device(s). B2h Device Reset protocol ...
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... LBA commands, e.g., Write Multiple Ext Read DMA protocol for 48-bit LBA commands. Read DMA Queued for 48-bit LBA commands. Write DMA protocol for 48-bit LBA commands. Write DMA queued for 48-bit LBA commands. Non-Data (Ext) protocol. 114 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Read DMA Queued Read DMA Queued (Ext) Read Long Service Write DMA Write DMA (Ext) Write DMA queued Write DMA queued (Ext) Write Long © 2007 Silicon Image, Inc. Protocol Command Examples Code 00h Any unsupported commands B2h Device Reset B1h ...
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... LED driver outputs will be driven low. There is no activity LED support for ATAPI device. If the downstream device is an ATAPI device, the corresponding LED output will not be driven low. SiI-DS-0103-D 116 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Verify that bit 25 is cleared in the Flash Memory Address – Command + Status register. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete. Read the data from the Flash memory access. The data field is defined by bits [07:00] in the Flash Memory Data register at Offset 54 © 2007 Silicon Image, Inc. of Base Address 5. H 117 ...
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... Read the data from the EEPROM memory access. The data field is defined by bits [07:00] in the EEPROM Memory Data register at Offset 5C SiI-DS-0103-D of Base Address Base Address 5. H 118 Silicon Image, Inc © 2007 Silicon Image, Inc. ...
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... The products and services described in these materials, and any other information, services, designs, know-how and/or products provided by Silicon Image, Inc. and/or its affiliates are provided on as “AS IS” basis, except to the extent that Silicon Image, Inc. and/or its affiliates provides an applicable written limited warranty in its standard ...