SII3132CNU Silicon image, SII3132CNU Datasheet
SII3132CNU
Available stocks
Related parts for SII3132CNU
SII3132CNU Summary of contents
Page 1
SiI3132 PCI Express to Serial ATA Controller Data Sheet Document # SiI-DS-0138-D Data Sheet ...
Page 2
... Silicon Image or its affiliates, and/or only in connection with your purchase of products and/or services from Silicon Image or its affiliates, and only in accordance with the terms and conditions herein. You have no right to copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these materials, or otherwise make these materials available, in whole or in part, to any third party ...
Page 3
... Command Issuance .............................................................................................................................. 26 Reset and Initialization .......................................................................................................................... 26 Port Reset Operation............................................................................................................................. 27 Initialization Sequence .......................................................................................................................... 27 Interrupts and Command Completion ................................................................................................... 28 Interrupt Sources................................................................................................................................... 29 Command Completion — The Slot Status Register .............................................................................. 32 © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Table of Contents iii Data Sheet SiI-DS-0138-D ...
Page 4
... Internal Register Space – Base Address 0 ........................................................................................... 54 Port Slot Status Registers ..................................................................................................................... 54 Global Control ....................................................................................................................................... 55 Global Interrupt Status........................................................................................................................... 55 PHY Configuration................................................................................................................................. 56 BIST Control Register ........................................................................................................................... 56 BIST Pattern Register ........................................................................................................................... 57 BIST Status Register ............................................................................................................................. Control ............................................................................................................................................. Status............................................................................................................................................... Slave Address.................................................................................................................................. 59 SiI-DS-0138-D iv Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 5
... Port Register Offset ............................................................................................................................... 78 Port Register Data ................................................................................................................................. 78 Power Management.................................................................................................................................... 79 2 Flash, GPIO, EEPROM, and I C Programming......................................................................................... 80 Flash Memory Access ............................................................................................................................ 80 PCI Direct Access.................................................................................................................................. 80 Register Access..................................................................................................................................... Operation ........................................................................................................................................... 80 © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller v Data Sheet SiI-DS-0138-D ...
Page 6
... Figure 3. Package Drawing 88 QFN ............................................................................................................ 12 Figure 4. Marking Specification .................................................................................................................... 13 Figure 5. SiI3132 Block Diagram.................................................................................................................. 14 Figure 6. Port Logic Block Diagram.............................................................................................................. 15 Figure 7. SiI3132 Interrupt Map.................................................................................................................... 30 Figure 8. Auto-Initialization from Flash Timing ............................................................................................. 35 Figure 9. Auto-Initialization from EEPROM Timing....................................................................................... 36 SiI-DS-0138-D List of Figures vi Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 7
... Table 42. Command Error Codes................................................................................................................. 68 Table 43. Default FIS Configurations............................................................................................................ 70 Table 44. SError Register Bits (DIAG Field) ................................................................................................. 76 Table 45. SiI3132 Internal Register Space – Base Address 2...................................................................... 77 Table 46. Power Management Register Bits ................................................................................................ 79 © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller List of Tables vii Data Sheet ...
Page 8
...
Page 9
... Overview The Silicon Image SiI3132 is a two-port PCI Express to Serial ATA controller. The SiI3132 is designed to provide multiple-port serial ATA connectivity with minimal host overhead and host-to-device latency. The SiI3132 supports a 1-lane 2.5 Gbit/s PCI Express bus and the Serial ATA Generation 2 transfer rate of 3.0 Gbit/s (300 MByte/s). ...
Page 10
... VDD VSS - Silicon Image, Inc. Ratings Unit 4.0 V 2.15 V 2.15 V -0.3 ~ VDD+0 °C/W 22.2 o -65 ~ 150 C Limits Min Typ Max - - - - - - 1.71 1.8 1. 3.0 3.3 3 450 570 - - 380 500 2 0.8 - 1.8 2.3 0.5 0 0.4 - © 2007 Silicon Image, Inc. Unit μA μ μA ...
Page 11
... Z Tx Single-Ended PCI_SIN impedance Z Rx Single-Ended PCI_SOUT impedance Z Rx Powered Down PCI_RX-HIGH-IMP-DC Impedance Z Electrical Idle Detect PCI_RX-IDLE-DET-DIFFp-p Threshold © 2007 Silicon Image, Inc. Table 3. SATA Interface DC Specifications Condition Terminated by 50 Ω. BAR1 1050h [4:0] = 0x0C - - - - - - - Condition Terminated by 50 Ω. Ratio - DC impedance ...
Page 12
... Random data pattern Measured at Tx output pins - peak to peak phase variation Random data pattern 4 Silicon Image, Inc. Limits Unit Typ Max - 273 ps 136 - +350 ppm - +0 ppm - - 15 ps Limits Unit Typ Max 100 - © 2007 Silicon Image, Inc. ...
Page 13
... PERST# active time PERST PCI Express Interface Transmitter Output Jitter Characteristics Table 9. PCI Express Interface Transmitter Output Jitter Characteristics Symbol Parameter TJ Total Jitter PCIe © 2007 Silicon Image, Inc. Condition /10 Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load =f /10 Measured at SATA ...
Page 14
... Measured with differential probe trigger by noise source 6 Silicon Image, Inc. Limits Unit Min Typ Max - 25 - MHz 0.7xVD - - 0.3xVD V DX -50 - +50 ppm - - psrms - - Limits Unit Min Typ Max - - 100 200 mV © 2007 Silicon Image, Inc. ...
Page 15
... FL_ADDR03 53 FL_ADDR04 55 FL_ADDR05 56 FL_ADDR06 57 FL_ADDR07 58 FL_ADDR08 59 FL_ADDR09 61 FL_ADDR10 62 FL_ADDR11 © 2007 Silicon Image, Inc. Table 12. SiI3132 Pin Listing Type Drive Internal Description Resistor Diff Serial port 1 differential receiver + input Diff Serial port 1 differential receiver – input Diff Out - - Serial port 1 differential transmitter – output ...
Page 16
... Crystal or Clock Input Table 13. Pin Types Pin Description Input Pin with LVTTL Thresholds Input Pin with Schmitt Trigger Output Pin Bi-directional Pin Bi-directional Pin with Schmitt Trigger Open Drain Output Pin 8 Silicon Image, Inc. C Serial Data C Serial Clock © 2007 Silicon Image, Inc. ...
Page 17
... TMS 76 TCK 77 TDI 78 TDO 79 TRSTN 80 81 SCAN_MODE I2C_SDAT 82 I2C_SCLK 83 VSSD 84 VDDX 85 XTALO 86 XTALI/CLKI 87 VSSX 88 © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller SiI3132 Top View Figure 2. Pin Diagram 9 Data Sheet 44 VDDO 43 FL_DATA4 42 FL_DATA3 41 FL_DATA2 40 FL_DATA1 39 FL_DATA0 38 VDDD 37 LED0 ...
Page 18
... Crystal Out. Crystal oscillator pin for SerDes reference clock. A 25-MHz crystal must be used. SiI-DS-0138-D Table 14. PCI Express Pin Descriptions 2 Table 15. Flash / LED Pin Descriptions 2 C) data line (internally connected to PHY clock (internally connected to PHY I 10 Silicon Image, Inc data line clock) © 2007 Silicon Image, Inc. ...
Page 19
... Digital Power. These pins provide 1.8V for the digital logic. VSSD 35, 48, 60, Digital Ground. These pins provide the Ground reference for the digital portion of the chip. 66, 84 © 2007 Silicon Image, Inc. Table 17. Test Pin Descriptions Table 18. Power/Ground Pin Descriptions 11 SiI3132 PCI Express to Serial ATA Controller ...
Page 20
... SiI-DS-0138-D Figure 3. Package Drawing 88 QFN Table 19. Package Dimensions Symbol Dimensions (mm) Minimum Nominal e 0.40 L 0.30 0.40 b 0.15 0. 5.85 6. 5.85 6. 0.85 A1 0.00 0. 0.65 A3 0.20 REF D 10.00 BSC D1 9.75 BSC E 10.00 BSC E1 9.75 BSC θ P 0.24 0.42 12 Silicon Image, Inc. Maximum 0.50 0.25 6.65 6.65 0.90 0.05 0.70 12° 0.60 © 2007 Silicon Image, Inc. ...
Page 21
... Silicon Image, Inc. Part Ordering Number SiI3132CNU (88-pin QFN lead free package with an exposed pad) SiI3132CNU LLLLLL.LL-L YYWW XXXXXXX © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Pin Location Logo SiI P/N Lot# (=Job#) Datecode Tracecode Figure 4. Marking Specification ...
Page 22
... Registers 2 Flash I C Controller 2 EEPROM I C Figure 5. SiI3132 Block Diagram 2 C Controller and Flash Controller is described in “” section on page 34 14 Silicon Image, Inc. Port Logic 0 SATA PLL Interrupt Logic Port Logic 1 Test Control Test Pins © 2007 Silicon Image, Inc. ...
Page 23
... PRB (Port Request Block). The 64-byte PRB is transferred into an available command slot in the LRAM by one of two methods: the direct method or the indirect method. The host driver is responsible © 2007 Silicon Image, Inc. PCI Exp – LRAM DMA Controller ...
Page 24
... SATA device. 4. The SiI3132 asserts a PCI Express interrupt to indicate command completion. 5. The host reads the SiI3132 port slot status to determine which command(s) have completed. SiI-DS-0138-D SiI 3132 controlled command transfer 16 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 25
... The XCF bit (bit 28 at offset 0x0c) indicates whether the region defined by this SGE used for data transfer (XCF set to zero external command fetch (XCF set to one). See section 0 for additional information on external command processing. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Table 20. Scatter/Gather Entry (SGE ...
Page 26
... SGE2 XCF Reserved[27:0] SGE3 Data Address Low SGE3 Data Address High SGE3 Data Count SGE3 XCF Reserved[27:0] 18 Silicon Image, Inc. 0 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C © 2007 Silicon Image, Inc. ...
Page 27
... Silicon Image, Inc. Table 22. Control Field Bit Definitions Description The Protocol Override Field used instead of the default protocol for this command. Allows retransmission if an error occurs during an external command transmission. The command FIS shall be fetched from host memory. This feature is used to send arbitrary FISes that will not fit in the command FIS area of the PRB ...
Page 28
... SGE1 Data Count SGE1 XCF 20 Silicon Image, Inc. 0 Control 0x00 0x04 PMP FIS Type 0x08 Sector Number 0x0C Sector Num (Exp) 0x10 Sector Count 0x14 Reserved 0x18 0x1C 0x20 0x24 0x28 Reserved[27:0] 0x2C 0x30 0x34 0x38 Reserved[27:0] 0x3C © 2007 Silicon Image, Inc. ...
Page 29
... Device Control 0x18 31:0 Reserved © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Table 25. PRB FIS Area Definition Description The FIS type field must be populated with a valid SATA FIS type. In all but special custom cases this value will be 0x27, which defines a “ ...
Page 30
... Control 0x00 0x04 PMP FIS Type 0x08 Sector Number 0x0C Sector Num (Exp) 0x10 Sector Count 0x14 Reserved 0x18 0x1C ATAPI opcode 0x20 LBA 0x24 XFR Length (LSB) 0x28 Reserved 0x2C 0x30 0x34 0x38 Reserved[27:0] 0x3C © 2007 Silicon Image, Inc. ...
Page 31
... These fields do not need to be supplied as inputs and may be in any state upon command issuance. Table 27. Port Request Block for Soft Reset Command 31 N/A Features / Error Command / Status Dev/Head Features (Exp) Cyl High (Exp) Device Control © 2007 Silicon Image, Inc. Control (0x0080) N Cyl High Cyl Low Cyl Low (Exp) Reserved ...
Page 32
... SGE0 XCF Reserved[27:0] SGE1 Data Address Low SGE1 Data Address High SGE1 Data Count SGE1 XCF Reserved[27:0] 24 Silicon Image, Inc. 0 0x00 0x04 Reserved 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C © 2007 Silicon Image, Inc. ...
Page 33
... Protocol Override SGE0 TRM SGE0 LNK SGE0 DRD SGE1 TRM SGE1 LNK SGE1 DRD © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Control Received Transfer Count Reserved – Must Be Zero SGE0 Data Address Low SGE0 Data Address High ...
Page 34
... The Port Reset must be cleared to zero by writing a one to bit zero of the Port Control Clear Register to release the Port Reset condition. Software may assert the port reset condition at any time by writing a one to bit zero of the Port Control Set Register. SiI-DS-0138-D 26 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 35
... Interrupt Enable Set Register (Port offset (port*0x2000)+0x1010 determine if device is present, poll the SStatus Register (Port offset (port*0x2000)+0x1f04) for a PHYRDY condition indicated by the DET field (bits[3:0]) having a value of 0x3. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller 27 ...
Page 36
... By default, this field is set to a value of zero, indicating that the interrupt is directed to INTA. The register may be set to one of four values, shown in Table 30. SiI-DS-0138-D 28 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 37
... Writing any value to the port CRC Error Counter Register or writing a one to bit the Interrupt Status Clear Register will clear this interrupt condition. This interrupt is enabled by © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Table 30 ...
Page 38
... Port_0_IntB INTB Port_1_IntB Port_0_IntC INTC Port_1_IntC Port_0_IntD INTD Port_1_IntD I2C_Interrupt I2C_Int_Enable Figure 7. SiI3132 Interrupt Map 30 Silicon Image, Inc. Global_Int_En_0 Port_0_IntA Int_Select_0 Port_0_IntB Int_Select_1 Port_0_IntC Int_Select_2 Port_0_IntD Int_Select_3 Port_0_Global_Int_Status Attention (Slot_Status[31]) Port 0 ULA PCI_CFG_INT_DIS Port_0_IntA Port_1_IntA © 2007 Silicon Image, Inc. INTA ...
Page 39
... CRC Error 9 Threshold Handshake Error 10 Threshold Set Device Bits 11 Notification Received © 2007 Silicon Image, Inc. Table 31. Port Interrupt Causes and Control To Clear: Raw 16 If Interrupt W1C == 0 Write 1 to Interrupt Enable Set bit 0 Read Slot Status If Interrupt W1C == 1 Write 1 to Port ...
Page 40
... Attention bit is one, the host should read the port Interrupt Status Register (Port offset (port*0x2000)+0x1008) to ascertain the cause for the Attention condition. Once the Attention condition has been resolved and cleared, normal processing may continue. SiI-DS-0138-D 32 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 41
... Fatal Errors. All other error codes indicate that an error condition has occurred that requires both the device and the internal operational state of the SiI3132 to be reset. The most common method to perform this function is to issue a Device Reset. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller 33 ...
Page 42
... Device Reset is issued. This ensures that the Port Resume bit is always cleared when starting normal processing in the event that an abnormal exit is taken from the error recovery procedure. Auto-Initialization The SiI3132 supports an external flash and/or EEPROM device for BIOS extensions and user-defined PCI configuration header data. SiI-DS-0138-D 34 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 43
... H 7FFF9 D06 H 7FFF8 D07 H 7FFF7 D08 H 7FFF6 D09 H 7FFF5 D10 H 7FFF4 D11 H © 2007 Silicon Image, Inc. and 7FFFE H 7FFFF 7FFFE 7FFFD 7FFFC D00 D01 D02 D03 Value Description 660 ns PCI reset to flash Auto-Initialization cycle begin 4200 ns Flash Auto-Initialization cycle time Table 33 ...
Page 44
... End of Auto-Initialization from flash to start of Auto-Initialization from EEPROM Auto-Initialization from EEPROM cycle time EEPROM serial clock period Description START condition R Write Command Read Command Acknowledge Serial data No-Acknowledge STOP condition 36 Silicon Image, Inc © 2007 Silicon Image, Inc. P ...
Page 45
... H 08 D08 H 09 D09 H 0A D10 H 0B D11 H © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Table 36. EEPROM Data Description Description Memory Present Pattern = AA H Memory Present Pattern = 55 H Data Signature = AA H Data Signature = 55 H PCI Device ID [23:16] ...
Page 46
... Silicon Image, Inc. Vendor ID PCI Command Revision ID Cache Line Size Subsystem Vendor ID Capabilities Ptr Interrupt Pin Interrupt Line Hdr Wr Ena Pwr Mgt Cap ID Control and Status MSI Cap ID Message Data PCI Exp Cap ID Device Control Link Control © 2007 Silicon Image, Inc. ...
Page 47
... Bit [31:16]: Device ID (R/W) – Device ID. The value in this bit field is one of the following: • The default value of 0x3132 to identify the device as a Silicon Image SiI3132 . • The value loaded from an external memory device external memory device – flash or EEPROM – is present with the correct signature, the Device ID is loaded from that device after reset. See “ ...
Page 48
... Bit [07:00]: Cache Line Size (R/W). This bit field is Read/Write for legacy purposes. The field is not used by the SiI3132. SiI -DS-0138-D PCI Class Code is defined by this specification. H Header Type Latency Timer . Silicon Image, Inc. Revision set the PCI Class Code is H Cache Line Size . © 2007 Silicon Image, Inc. ...
Page 49
... Bit [63:15]: Base Address Register 1 (R/W). This register defines the base address for the 16kbyte Memory Space containing the Port Registers. • Bit [14:00]: (R). This bit field is hardwired to 0004 © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Base Address Register 0 Base Address Register 0 to indicate a 64-bit base address ...
Page 50
... See “Auto-Initialization from Flash” section on page 35 for more information. • System programmed value; if bit 0 of the Configuration register (48 Vendor ID is system programmable. SiI -DS-0138 Subsystem Vendor set the Subsystem set the Subsystem H 42 Silicon Image, Inc. 000 0001 © 2007 Silicon Image, Inc. ...
Page 51
... Bit [15:08]: Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01 SiI3132 uses the INTA interrupt. The INTB, INTC, and INTD interrupts may be used by enabling them in the Port Interrupt Enable registers; this use is outside the PCI specification. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller 000_0000_0000_0000_000 ...
Page 52
... Bit [07:00]: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 01 PCI Power Management Capability. SiI -DS-0138-D Reserved ), Subsystem Vendor ID (2D-2C H PPM Rev Next Capability Pointer 44 Silicon Image, Inc. ), and Subsystem ID H Capability ID ; the indicate indicate that this © 2007 Silicon Image, Inc. ...
Page 53
... Bit [15:08]: Next Capability Pointer (R) –Next Capability Pointer. This bit field is hardwired the 3 Capabilities register, the PCI Express Capability. • Bit [07:00]: Capability ID (R) – This bit field is hardwired to 05 © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Reserved PPM Data Sel Multiple ...
Page 54
... Bit [15:08]: Next Capability Pointer (R) – PCI Next Capability Pointer. This bit field is hardwired the last capability). SiI -DS-0138-D Message Address Upper Message Address Device Type Version Next Capability Pointer to indicate compliance with the PCI Express H 46 Silicon Image, Inc. 00 Message Data Capability ID to indicate a PCI Express Legacy B © 2007 Silicon Image, Inc. (this H ...
Page 55
... Bit [08]: Ext Tag Fld En (R) – Extended Tag Field Enable. This bit is hardwired to 0. • Bit [07:05]: Max Payload Size (R/W) – Allowable values are 000 000 (128 bytes). B © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller L1 L0s Reserved ...
Page 56
... Bit [04]: Link Disable (R) – This bit is hardwired to 0. • Bit [03]: RCB (R/W) – Read Completion Boundary. • Bit [01:00]: ASPM Control (R/W) SiI -DS-0138-D L1 Exit L0s Exit Reserved Latency Latency . Link Speed Reserved . B 48 Silicon Image, Inc. Maximum Link Maximum Link Width Speed . © 2007 Silicon Image, Inc. ...
Page 57
... Access Type: Read/Write This register provides the indirect access addressed by the Port Register Offset register. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Reserved ...
Page 58
... Bit [04]: DL Protocol Err (R/W1C) – Data Link Protocol Error Status. • Bit [00]: Training Error (R) – This bit is hardwired to 0 (as are its mask and error severity bits). SiI -DS-0138-D Version Extended Capability ID to indicate compliance with the PCI Express H Reserved 50 Silicon Image, Inc indicate H Reserved © 2007 Silicon Image, Inc. ...
Page 59
... Bit [07]: Bad DLLP (R/W1C) – Bad DLLP Status. • Bit [06]: Bad TLP (R/W1C) – Bad TLP Status. • Bit [00]: Rx Error (R/W1C) – Receiver Error Status. This bit is hardwired to 0 (as is the corresponding mask bit). © 2007 Silicon Image, Inc. Reserved 51 SiI3132 PCI Express to Serial ATA Controller ...
Page 60
... Bit [06]: ECRC Gen En (R/W) – ECRC Generation Enable. • Bit [05]: ECRC Gen Cap (R) – ECRC Generation Capable. This bit is hardwired to 1. • Bit [04:00]: First Error Pointer (R). SiI -DS-0138-D Reserved Reserved 52 Silicon Image, Inc. Reserved Reserved First Error Pointer © 2007 Silicon Image, Inc. ...
Page 61
... Header Byte 0 Header Byte 4 Header Byte 8 Header Byte 12 This 16-byte register contains the header of a TLP associated with an error. © 2007 Silicon Image, Inc. / 128 H H Header Log (1st dword) Header Byte 1 ...
Page 62
... Port 0 Slot Status Port 1 Slot Status Reserved Global Control Global Interrupt Status PHY Configuration Reserved Control Status Slave Address Data Buffer Flash Address GPIO Reserved Slot Status 54 Silicon Image, Inc. Flash Data © 2007 Silicon Image, Inc. ...
Page 63
... Bit [1:0]: Port Interrupt Status (R/W1C). These bits, when set to one, indicate that the corresponding port has an interrupt condition pending. Writing any of these bits clears the corresponding Command Completion Interrupt Status, but not other interrupt sources. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Reserved ...
Page 64
... Bit [17:16]: BISTcompsel (R/W). This bit field selects the port from which loopback data is selected for pattern comparison. • Bit [15:04]: Reserved (R/W). These bits are reserved and must write zeros. • Bit [03:00]: BISTrun (R/W). This bit field selects the port(s) that transmit loopback data. SiI -DS-0138-D PHY Confgig Reserved 56 Silicon Image, Inc. BISTrun © 2007 Silicon Image, Inc. ...
Page 65
... Bit [12]: Arb Loss Det Int En (R/W). Arbitration Loss Detected Interrupt Enable – This bit enables interrupt generation upon losing arbitration in Master Mode. If this bit is not set, and arbitration is lost during transmission of the control byte, the arbitration and transmission will be automatically repeated. © 2007 Silicon Image, Inc. BIST Pattern Reserved 2 C interface ...
Page 66
... C Data Buffer Receive Full – A data byte has been received and an ACK or 58 Silicon Image, Inc controller operations Clock output for Master Mode 2 C clock allowing for some minimal (one bit clock allowing for some minimal (one © 2007 Silicon Image, Inc. ...
Page 67
... Bit [30:27]: Reserved (R). This bit field is reserved and returns ‘0001’ read. • Bit [26]: Mem Present (R) – Memory Present. This bit set indicates that the auto-initialization signature was read correctly from the flash Memory. © 2007 Silicon Image, Inc bus is busy because of activity other than that generated controller is busy ...
Page 68
... For GPIO, this field is used to write the GPIO output register and to read the GPIO input signals. SiI -DS-0138-D GPIO Control Transition Detect 60 Silicon Image, Inc. Memory Data © 2007 Silicon Image, Inc. ...
Page 69
... Port 0 SStatus H 1F08 Port 0 SError H 1F0C Port 0 SActive (indirect location) H 1F10 Port 0 SNotification H 1F14 -1FFF Reserved H H 2000 -3FFF Port 1 Registers mapped as above H H © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller . H 61 Data Sheet SiI -DS-0138-D ...
Page 70
... Port Multiplier Device 1 Status Register H Port Multiplier Device 1 QActive Register H Port Multiplier Device Registers for Devices 2-14 H Port Multiplier Device 15 Status Register H Port Multiplier Device 15 QActive Register H Table 41. Port LRAM Slot layout 62 Silicon Image, Inc. Port Request Block (PRB) © 2007 Silicon Image, Inc. ...
Page 71
... This bit is set for environments that do not address more than 2 • Bit [9]: Scrambler Disable (W1S). When this bit is set to one, the Link scrambler operation is disabled. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Slot Status ...
Page 72
... Port Control Clear register). The register bits that are not initialized by the Port Reset are: • OOB Bypass (bit 25) in Port Control (this register) • Port PHY Configuration register (all bits) SiI -DS-0138-D 64 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 73
... Bit [31:26,24:16,12:11,2:1]: Reserved (R). These bits are reserved. • Bit [25, 15:13,10:3,0]: (W1C) Writing a one to these bits clears the associated bit position of the Port Control register. Refer to the Port Control Set register for bit descriptions. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Active Slot ...
Page 74
... Bit [17/1]: Command Error (W1C). This bit indicates that an error occurred during command execution. The error type can be determined via the port error register. • Bit [16/0]: Command Completion (W1C). This bit indicates that one or more commands have completed execution. SiI -DS-0138-D Reserved 66 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 75
... FIFO. A valid PRB must be populated in the associated slot in port LRAM. When read, this register supplies the entry at the head of the command execution FIFO. The FIFO is not popped as a result of a read operation. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Reserved ...
Page 76
... The address of a PRB written to a command activation register was not aligned on a quadword boundary. All PRB addresses must be quadword aligned. Bits[2:0] must be zeroes. A PCI Target Abort occurred while the SiI3132 was fetching a Port Request Block (PRB) from host memory. 68 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 77
... Interlock FIS. Receive FIS into slot reserved for interlocked FIS reception slot has been reserved, reject the FIS. • 11 – Reserved. Bit[1:0] (FISOcfg) defines the 2-bit code for all other FIS types not defined by bits [29:2]. © 2007 Silicon Image, Inc. Code Description A PCI Master Abort occurred while the SiI3132 was fetching a Port Request Block (PRB) from host memory ...
Page 78
... FIS without interlock fisc7cfg[1:0] 01b reject FIS without interlock fisd4cfg[1:0] 01b reject FIS without interlock fisd9cfg[1:0] 01b reject FIS without interlock fisocfg[1:0] 01b reject FIS without interlock Reserved Reserved 70 Silicon Image, Inc. PCI Exp Read Request Threshold Reserved © 2007 Silicon Image, Inc. ...
Page 79
... Clearing the interrupt status bit will also clear the counter. The count will not overflow. Once this register reaches its maximum count, it will retain that count until cleared to zero by a write operation. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller 8B/10B Decode Error Counter ...
Page 80
... Bit[4:0]: Tx Amplitude (R/W) These bits set the nominal output swing for the Transmitter. The amplitude will be increased by 50mV by an increment of the value. SiI -DS-0138-D Serial ATA Handshake Error Counter PHY Config 72 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
Page 81
... Address Offset bits are the Port Multiplier Port number for the device to which the status bits apply. • Bit [31:00]: Each bit corresponds to a slot number that contains an active outstanding legacy or native queued command. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller (PM Port 1) / F90 ...
Page 82
... Transitions to the Slumber power management state are disabled 0011 Transitions to both the Partial and Slumber power management states are disabled others Reserved SiI -DS-0138-D Reserved PMP SPM 74 Silicon Image, Inc. PM Port Slot IPM SPD DET © 2007 Silicon Image, Inc. ...
Page 83
... Device presence detected and PHY communication established 0100 PHY in offline mode as a result of the interface being disabled or running in a BIST loopback mode Others Reserved, no action © 2007 Silicon Image, Inc. Reserved 75 SiI3132 PCI Express to Serial ATA Controller Data Sheet IPM SPD ...
Page 84
... Indicates a change in the status of the Serial ATA PHY Latched Handshake error from the Serial ATA PHY Always 0 N/A, always 0 N/A, always 0 Latched ComWake status from the Serial ATA PHY Latched ComInit status from the Serial ATA PHY Active bits 76 Silicon Image, Inc ERR © 2007 Silicon Image, Inc. ...
Page 85
... Access Type: Read/Write This register provides the indirect access addressed by the Global Register Offset register. © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller Reserved ...
Page 86
... This register provides the indirect access addressed by the Port Register Offset register. SiI -DS-0138-D As defined for indirectly accessed register 78 Silicon Image, Inc. Dword Offset 00 © 2007 Silicon Image, Inc. ...
Page 87
... Partial/Slumber mode is entered. Partial/Slumber mode status is reported in the SStatus register (‘0010’/’0110’ in the IPM field). Partial/Slumber mode is cleared by ComWake (asserted when the SPM field is set to ‘0100’). © 2007 Silicon Image, Inc. Table 46. Power Management Register Bits Description This bit reports a change in the Power Management mode ...
Page 88
... I Data/Control register. SiI -DS-0138 Programming 2 C interface. For Auto-initialization of some PCI Configuration registers interface: the I 80 Silicon Image, Inc interface (see section 0). Two registers Address register and the I C © 2007 Silicon Image, Inc. ...
Page 89
... Check bit 28 in the I C Data/Control register. The bit is set if an error occurred during the access. Read the data from bits 7:0 in the I © 2007 Silicon Image, Inc. SiI3132 PCI Express to Serial ATA Controller 2 C Access Start) is zero. The bit is one when an access Data/Control register ...
Page 90
... The products and services described in these materials, and any other information, services, designs, know-how and/or products provided by Silicon Image, Inc. and/or its affiliates are provided on as “AS IS” basis, except to the extent that Silicon Image, Inc. and/or its affiliates provides an applicable written limited warranty in its standard ...