SII0680ACL144 Silicon image, SII0680ACL144 Datasheet
SII0680ACL144
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SII0680ACL144 Summary of contents
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SiI0680A PCI to IDE/ATA Data Sheet Document # SiI-DS-0069-C Data Sheet ...
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... Rev. 1.2 Changed Document Number Rev. 1.3 Made minor corrections and change the document name from 680 to 680A Rev. A3 Updated part ordering number at section 4 package drawing Rev. B Updated Formatting Rev. C Removed confidential markings © 2006 Silicon Image, Inc. Comment 2 Silicon Image, Inc. Date 08/07/00 10/09/00 10/10/00 10/13/00 01/23/01 ...
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... PCI Class Code – Revision ID ...............................................................................................................................49 9.1.4 BIST – Header Type – Latency Timer – Cache Line Size .....................................................................................50 9.1.5 Base Address Register 0 .......................................................................................................................................50 9.1.6 Base Address Register 1 .......................................................................................................................................50 9.1.7 Base Address Register 2 .......................................................................................................................................51 © 2006 Silicon Image, Inc. SiI0680A PCI to IDE/ATA Table of Contents 3 Data Sheet SiI-DS-0069-C ...
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... FIFO Valid Byte Count and Control – IDE0..........................................................................................................77 9.7.12 FIFO Valid Byte Count and Control – IDE1..........................................................................................................78 9.7.13 System Configuration Status – Command ...........................................................................................................79 9.7.14 System Software Data Register...........................................................................................................................79 9.7.15 FLASH Memory Address – Command + Status ..................................................................................................80 © 2006 Silicon Image, Inc. 4 Silicon Image, Inc. SiI-DS-0069-C ...
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... If no error, repeat the previous four steps until all data for the write command has been transferred or an error has been detected. ..........................................................................................................................................................................111 11.6 Watchdog Timer Operation..................................................................................................................... 111 11.7 IDE PIO Mode Read Ahead Operation ................................................................................................... 113 11.8 IDE MDMA/UDMA Read/Write Operation............................................................................................... 113 11.9 IDE Virtual DMA Read/Write Operation ................................................................................................. 114 © 2006 Silicon Image, Inc. SiI0680A PCI to IDE/ATA H 5 Data Sheet will cause the controller ...
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... PIO Timing Register Programming in Number of 33 MHz PCI clock .....................................................................121 13.2.3 DMA Timing Register Programming in Number of 33 MHz PCI clock ...................................................................121 13.2.4 UDMA Timing Register Programming in Number of 100 MHz IDE clock...............................................................121 13.2.4 UDMA Timing Register Programming in Number of 133 MHz IDE clock...............................................................121 © 2006 Silicon Image, Inc. 6 Silicon Image, Inc. SiI-DS-0069-C ...
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... Table 9-11: IDE1 Test Register Selections ..............................................................................................................................101 Table 10-1: Test Mode Register Selections .............................................................................................................................104 Table 10-2: SiI 0680A NAND Tree Order .................................................................................................................................105 Table 10-2, SiI 0680A NAND Tree Order (continued) ..............................................................................................................106 Table 11-1, Physical Region Descriptor (PRD) Format ............................................................................................................117 © 2006 Silicon Image, Inc. Table of Tables .....................................................................................................72 H .....................................................................................................74 ...
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... Figure 1-2: Address Lines During Configuration Cycle...............................................................................................................13 Figure 3-1: SiI 0680A Pin Diagram.............................................................................................................................................23 Figure 3-2: Package Drawing – 144 LQFP.................................................................................................................................32 Figure 3-3: Marking Specification – SiI0680ACL144 ..................................................................................................................33 Figure 3-4: Marking Specification – SiI0680ACLU144................................................................................................................33 Figure 5-1: SiI 0680A ASIC Block Diagram ................................................................................................................................34 Figure 6-1: SiI 0680A Clocking System and Test Feature Diagram ...........................................................................................37 Figure 7-1: Schematic of PLL Circuitry......................................................................................................................................38 Figure 7-2: Example Layout – ...
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... Silicon Image, Inc. 1. Overview The Silicon Image PCI-680 is a single-chip solution for a PCI to ATA controller. It accepts host commands through the PCI bus, processes them and transfers data between the host and ATA devices. It can be used to control two independent ATA channels: primary and secondary. Each channel has its own ATA bus and will support up to two ATA/ATAPI devices for a maximum of four devices ...
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... ATA Interface. Two separate channels (Primary and Secondary) to access storage media such as hard disk drives, CD-ROM’s etc. • Controller Interface. Additional hardware interface for controlling and configuring the Host Controller. © 2006 Silicon Image, Inc. 10 Silicon Image, Inc. SiI-DS-0069-C ...
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... Silicon Image, Inc. 1.6 Functional Block Diagram Figure 1-1: SiI 0680A Functional Block Diagram © 2006 Silicon Image, Inc SiI0680A PCI to IDE/ATA ...
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... All other PCI cycles are ignored by the PCI-680 PCI master, the PCI-680 generates the following PCI bus operations: • Memory Read Multiple • Memory Read Line • Memory Read • Memory Write © 2006 Silicon Image, Inc. 12 Silicon Image, Inc. SiI-DS-0069-C ...
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... The PCI-680 product has been developed and tested to the specification listed in this document result of testing and customer feedback, we may become aware of deviations to the specification that could affect the component's operation. To ensure awareness of these deviations by anyone considering the use of the PCI-680, we will include them in this document. © 2006 Silicon Image, Inc ...
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... Input High Current I IH Input Low Current I IL Output High V OH Voltage V Output Low Voltage OL 3-State Leakage I OZ Current © 2006 Silicon Image, Inc. 2. Electrical Characteristics unless otherwise specified. Parameter Ratings 3.6 -0.3 ~ 6.0 16 -65 ~ 150 Table 2-1: Absolute Maximum Ratings Condition Type Min - - 3 ...
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... Low-to-High Input Threshold V- High-to-Low Input Threshold Output Voltage High Output Voltage Low OL © 2006 Silicon Image, Inc. Parameter Table 2-3: PCI 33 MHz Timing Specifications Condition Refer to ATA Specification for specific test condition requirements Refer to ATA Specification for specific test condition ...
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... For a slight improvement in high frequency impedance of the bypass capacitors, two capacitors in parallel can be used for Local Bypass. The paired caps must be located as close as possible to each other. The following values are recommended for the capacitor pairs: Ceramic X7R Dielectric - 0.1uF Ceramic X7R Dielectric – 1000pF © 2006 Silicon Image, Inc. 16 Silicon Image, Inc. SiI-DS-0069-C ...
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... PLL_VCOBIAS 5 PLL_LOOPFLT 6 PLL_GND 7 TEST_MODE 8 IDE0_DD00 9 IDE0_DD01 10 IDE0_DD02 11 IDE0_DD03 12 IDE0_DD04 13 IDE0_DD05 14 IDE0_DD06 15 IDE0_DD07 16 VDD 17 VSS 18 IDE0_DD08 19 IDE0_DD09 © 2006 Silicon Image, Inc. Type Drive Internal Resistor GND - - PWR - - Analog - - Analog - - Analog - - GND - - – 20k ATA Buffer I/O PU – 100k ATA Buffer I/O PU – 100k ...
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... IDE0_DIOR_N 34 IDE0_DIOW_N 35 IDE0_DMACK_N 36 VDD 37 VSS 38 IDE0_CBLID_N 39 IDE0_INTRQ 40 IDE0_IORDY 41 IDE0_AT_REXT 42 IDE0_DMARQ 43 IDE0_RST_N © 2006 Silicon Image, Inc. Type Drive Internal Resistor I/O ATA Buffer PU – 100k I/O ATA Buffer PU – 100k I/O ATA Buffer PU – 100k I/O ATA Buffer PU – 100k I/O ATA Buffer PU – 100k I/O ATA Buffer PU – ...
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... IDE1_DD12 59 IDE1_DD13 60 IDE1_DD14 61 VDD 62 VSS 63 IDE1_DD15 64 IDE1_CS0_N 65 IDE1_CS1_N 66 IDE1_DA0 67 IDE1_DA1 68 IDE1_DA2 © 2006 Silicon Image, Inc. Type Drive Internal Resistor ATA Buffer I/O PU – 100k ATA Buffer I/O PU – 100k ATA Buffer I/O PU – 100k ATA Buffer I/O PU – 100k ATA Buffer I/O PU – 100k I/O ATA Buffer PU – ...
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... PCI_AD27 86 PCI_AD26 87 VDD 88 VSS 89 PCI_AD25 90 PCI_AD24 91 PCI_CBE3 92 PCI_IDSEL 93 PCI_AD23 94 PCI_AD22 95 PCI_AD21 96 PCI_AD20 97 PCI_AD19 98 VDD 99 VSS © 2006 Silicon Image, Inc. Type Drive Internal Resistor I/O ATA Buffer - I/O ATA Buffer - I-Schmitt - PU – 100k PWR - - GND - - ATA Buffer I/O - I-Schmitt - PD – 100k I-Schmitt - PU – 100k ...
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... VDD 119 VSS 120 PCI_AD12 121 PCI_AD11 122 PCI_AD10 123 PCI_AD09 124 PCI_AD08 125 PCI_CBE0 126 PCI_AD07 127 PCI_AD06 128 VDD 129 VSS 130 PCI_AD05 © 2006 Silicon Image, Inc. Type Drive Internal Resistor I/O PCI - I/O PCI - I/O PCI - I/O PCI - I/O PCI - I/O PCI - I/O PCI ...
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... PCI_AD01 135 PCI_AD00 136 PCI_REQ_N 137 PCI_GNT_N 138 PCI_INTA_N 139 BA5_EN 140 PCI_CLK 141 PCI_RST_N 142 SCAN_EN 143 MEM_CS_N 144 VDD Pin Type I I-Schmitt O T I/O OD © 2006 Silicon Image, Inc. Type Drive Internal Resistor I/O PCI - I/O PCI - I/O PCI - I/O PCI - I/O PCI - I/O PCI - T PCI - I - ...
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... PCI_REQ_N 136 PCI_GNT_N 137 PCI_INTA_N 138 BA5_EN 139 PCI_CLK 140 PCI_RST_N 141 SCAN_EN 142 MEM_CS_N 143 VDD 144 © 2006 Silicon Image, Inc. SiI 0680 Top View Figure 3-1: PCI-680 Pin Diagram 23 SiI0680A PCI to IDE/ATA Data Sheet 72 VDD 71 IDE1_CBLID_N 70 IDE1_DIOW_N 69 IDE1_DIOR_N 68 IDE1_DA2 67 ...
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... This signal is normally used by the SiI 0680A in response to IDE0_DMARQ to either acknowledge that the primary channel is ready to accept data, or that data is available. This signal is also used to write CRC code to the primary channel drive at the end of each Ultra DMA burst transfer. © 2006 Silicon Image, Inc. 24 Silicon Image, Inc. ...
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... The data bus is normally in a high impedance state and is driven by the SiI 0680A during the IDE1_DIOW_N command pulse in either single/multi-word DMA mode, or valid at every edge of IDE1_DIOR_N (HSTROBE) or IDE1_IORDY (DSTROBE) in Ultra DMA mode. IDE1_DD07 is a multifunction pin, which allows a host to recognize the © 2006 Silicon Image, Inc. 25 SiI0680A PCI to IDE/ATA ...
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... IDE1 Interrupt Request Pin Name: IDE1_INTRQ Pin Number: 75 Primary channel interrupt request is an input signal used to generate the PCI_INTA_N output. This input should have a 10kΩ pull-down resistor connected to it. IDE1 I/O Ready © 2006 Silicon Image, Inc. 26 Silicon Image, Inc. SiI-DS-0069-C ...
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... PCI ID Select Pin Name: PCI_IDSEL Pin Number: 92 This signal is used as a chip select during configuration read and write transactions. © 2006 Silicon Image, Inc. 27 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
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... However, the restoring of PCI_SERR_N to the de-asserted state is accomplished by a weak pull-up. Note that if an agent does not want a non-maskable interrupt (NMI generated, a different reporting mechanism is required. PCI Parity Pin Name: PCI_PAR © 2006 Silicon Image, Inc. 28 Silicon Image, Inc. SiI-DS-0069-C ...
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... Dedicated PLL Power supply (3.3 Volts +/- 10%). Refer to section 7.1 for PLL connections. PLL Charge Pump Bias Pin Name: PLL_CPBIAS Pin Number: 3 Dedicated PLL analog pin for charge pump bias. Refer to section 7.1 for PLL connections. © 2006 Silicon Image, Inc. 29 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
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... This pin has an internal pull-up resistor, and if left unconnected, will default to ‘1’. Otherwise, tie this pin high (1,) or low (0) to select the desired mode recommended that this pin to be tied to low (RAID Class) when Silicon Image drivers (RAID or Non-RAID) are used. Base Address 5 Enable ...
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... This pin when active (high) will place all scan flip-flops into a scan mode. This pin should be tied to ground for normal operation. Memory Chip Select Pin Name: MEM_CS_N Pin Number: 143 This pin is used to select and enable the external memory active low © 2006 Silicon Image, Inc. Table 3-3: Base Address 5 Configuration 31 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
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... SiI0680A PCI to IDE/ATA Data Sheet 108 109 144 PIN #1 Part Ordering Number: SiI0680ACLU144 (144pin LQFP lead free package) SiI0680ACL144 (144pin LQFP standard package) © 2006 Silicon Image, Inc. 22.0 + 0.25 SQ 20.0 + 0.10 SQ INDEX 0.50 NOM 0.22 + 0.05 Dimensions in millimeters Figure 3-2: Package Drawing – 144 LQFP 32 Silicon Image, Inc. ...
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... Silicon Image, Inc. Pin 1 designator location Figure 3-3: Marking Specification – SiI0680ACL144 Pin 1 designator location Figure 3-4: Marking Specification – SiI0680ACLU144 © 2006 Silicon Image, Inc. SiI0680ACL144 LLLLLL.LL YYWW SiI0680ACLU144 LLLLLL.LL YYWW 33 SiI0680A PCI to IDE/ATA Data Sheet Logo SiI P/N Lot # (= Job#) Date Code ...
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... SiI0680A PCI to IDE/ATA Data Sheet The PCI-680 ASIC contains the major logic modules shown in Figure 5-1. PCI Interface 400 MHz Phase Locked Loop © 2006 Silicon Image, Inc. PCI680 PCI680_CORE Bus Data Interface FIFO PCI DMA Engine Arbiter PCI DMA Engine Bus ...
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... IDE0_DMARQ IDE0_RST_N IDE Channel #1 IDE1_DD[15:00] IDE1_CS0_N IDE1_CS1_N IDE1_DA0 IDE1_DA1 IDE1_DA2 IDE1_DIOR_N IDE1_DIOW_N IDE1_DMACK_N IDE1_CBLID_N IDE1_INTRQ IDE1_IORDY IDE1_AT_REXT IDE1_DMARQ IDE1_RST_N © 2006 Silicon Image, Inc. Bits Type 32 I/O PCI address/data bus 4 I/O PCI command/byte enables 1 I PCI ID select 1 I/O PCI FRAME# signal 1 I/O PCI IRDY# signal ...
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... Table 5-4: PCI-680 FLASH Memory Signals Group – Shared Signals EEPROM Interface IDE1_CS1_N IDE1_CS0_N Table 5-5: PCI-680 EEPROM Memory Signals Group – Shared Signals Test Mode Signals SCAN_EN TEST_MODE © 2006 Silicon Image, Inc. Bits Type 1 O FLASH memory address bit FLASH memory address bit 17 ...
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... Clock) PCI_CLK (Test Clock) IDE0_DMARQ (Test Clock) IDE0_CBLID_N (Test Clock) IDE1_CBLID_N To all scan flip flops SCAN_EN Figure 6-1: SiI 0680A Clocking System and Test Feature Diagram © 2006 Silicon Image, Inc. SYS_NAND_TEST Nand Tree Normal Function Normal Function 4K & 33 MHz 2 SYS_IDE_CLKSEL[1:0] 2 ...
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... The schematic of PLL related components are shown in Figure 7-1. Reference Designators shown are for illustration purposes only and do not reflect those on the evaluation board. The values are subject to change. Please contact Silicon Image for the latest revision of the schematic for current reference designators and component values used on evaluation boards. ...
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... Johanson – 500-R15-Z-103-M-V6E Kemet – C0805C103M5UAC 8.) Capacitor = Ceramic, 0.1uF, 50V, 20%, X7R, 0805 Qty = 1 Ref Des Example Part Numbers: AVX – 0805-5-C-104-KATMA Rohm – MCH21-5-E-104-M Johanson – 500-R15-W-104-M-V4E © 2006 Silicon Image, Inc. 39 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
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... It is important to keep the trace lengths short. No high-speed digital signals should be allowed to pass through, above or below, any portion of the power and ground “islands”. Take extra care to make sure the data bits located on pins 8 through 15 are routed clear of the “islands”. © 2006 Silicon Image, Inc. 40 Silicon Image, Inc. ...
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... Silicon Image, Inc. © 2006 Silicon Image, Inc. Figure 7-2: Example Layout – Ground Plane 41 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
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... SiI0680A PCI to IDE/ATA Data Sheet © 2006 Silicon Image, Inc. Figure 7-2: Example Layout – Power Plane 42 Silicon Image, Inc. SiI-DS-0069-C ...
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... MEM_ADDR MEM_DATA MEM_RD_N MEM_WR_N t 1 MEM_CS_N PCI_RST_N Figure 8-1: Auto-Initialization from Flash Timing Parameter © 2006 Silicon Image, Inc. and 7FFFE ), checking for the correct data signature pattern – 7FFFC H 7FFFF 7FFFE 7FFFD 7FFFC 7FFFB 7FFFA D00 D01 ...
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... STOP condition. While the sequence is active, the SiI 0680A responds to all PCI bus accesses with a Target Retry. SDAT t 1 SCLK MEM_CS_N Figure 8-2: Auto-Initialization from EEPROM Timing © 2006 Silicon Image, Inc. Description D00 Data Signature = AA H D01 Data Signature = 55 H D02 ...
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... © 2006 Silicon Image, Inc. Value Description 26.00 μs End of Auto-Initialization from FLASH to start of Auto-Initialization from EEPROM 2.66 ms Auto-Initialization from EEPROM cycle time 19.26 μs EEPROM serial clock period Description START condition R Write Command Read Command Acknowledge ...
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... Max Latency © 2006 Silicon Image, Inc. Register Name 31 16 Vendor ID (1095h) PCI Command PCI Class Code Header Type Latency Timer Base Address Register 0 Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 ...
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... B4 IDE1 Device 1 PIO Timing H B8 IDE1 Device 1 DMA Timing H BC IDE1 Device 1 UDMA Timing H Table 9-1: SiI 0680A PCI Configuration Space (continued) © 2006 Silicon Image, Inc. Register Name 31 16 Reserved Reserved Reserved Next Item Pointer Reserved Functions Control and Status Reserved ...
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... Bit [31:16]: Device ID (R/W) – Device ID. This value in this bit field is determined by any one of three options: • 1) This field defaults to 0x0680 to identify the device as a Silicon Image SiI 0680A. • 2) loaded from an external memory device : If an external memory device – FLASH or EEPROM – is present with the correct signature, the PCI Class Code is loaded from that device after reset ...
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... If Bit 0 of the Configuration register (40 bytes are system programmable. • Bit [07:00]: Revision ID (R) – Chip Revision ID. This bit field is hardwired to 01 silicon. © 2006 Silicon Image, Inc PCI Prog Int ]. The correct signature for a FLASH device is the data pattern AA55 ...
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... Bit [31:02]: Base Address Register 1 (R/W). This register defines the I/O Space base address for the IDE Channel #0 Device Control- Alternate Status register. • Bit [01:00]: Base Address Register 1 (R). This bit field is not used and is hardwired to 01 © 2006 Silicon Image, Inc. Header Type Latency Timer . ...
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... Bit [31:04]: Base Address Register 4 (R/W). This register defines the I/O Space base address for the PCI bus master registers. • Bit [03:00]: Base Address Register 4 (R). This bit field is not used and is hardwired to 0001 © 2006 Silicon Image, Inc. Base Address Register 2 Base Address Register 3 Base Address Register 4 ...
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... BA5_EN is set to one. See section 3.1.5 for descriptions. The register bits are defined below. • Bit [31:08]: Base Address Register 5 (R/W). This register defines the Memory Space base address for all Silicon Image driver specific functions. • Bit [07:00]: Base Address Register 5 (R). This bit field is not used and is hardwired to 00 9.1.11 Subsystem ID – ...
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... INTA# interrupt. • Bit [07:00]: Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt line routing information. The SiI 0680A does not use this information. © 2006 Silicon Image, Inc. Not Used . The minimum Expansion ROM address range H ...
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... Bit [21]: Dev Special Init (R) – Device Special Initialization. This bit is hardwired indicate that the SiI 0680A does not require special initialization • Bit [20]: Reserved (R). This bit is reserved and returns zero on a read. © 2006 Silicon Image, Inc. Reserved . H ), and Subsystem ID (2F-2E ) ...
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... This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 4, Offset 00 , Base Address 5, Offset 00 H definitions. © 2006 Silicon Image, Inc. Reserved PPM Data Sel Reserved , and Base Address 5, Offset 10 ...
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... This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 4, Offset 0C and Base Address 5, Offset 0C H © 2006 Silicon Image, Inc. PRD Table Address – IDE0 . See Section 9.7.2 for bit definitions. H ...
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... Reserved This register defines the system configuration status and command register for the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 48 H © 2006 Silicon Image, Inc. Reserved Reserved Reserved Reserved ...
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... This register defines the data register for FLASH memory interface in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 54 . See Section 9.7.16 for bit definitions. H © 2006 Silicon Image, Inc. System Software Data . See Section 9.7.15 for bit definitions. H Reserved ...
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... This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset A0 . See Section 9.7.33 for bit definitions. H © 2006 Silicon Image, Inc. Reserved . See Section 9.7.17 for bit definitions. H Reserved ...
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... This register defines the UDMA timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset AC . See Section 9.7.36 for bit definitions. H © 2006 Silicon Image, Inc. Device 1 Recovery Device 0 Addr Device 0 Active Count Count ...
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... This register defines the DMA timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset E8 . See Section 9.7.48 for bit definitions. H © 2006 Silicon Image, Inc. Recovery Count Device 1 Recovery Device 0 Addr Device 0 Active Count ...
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... This register defines the UDMA timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset EC . See Section 9.7.50 for bit definitions. H © 2006 Silicon Image, Inc. Device 1 Cycle Time Count 62 Silicon Image, Inc. ...
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... IDE0 Task File Command + Status This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 84 . See Section 9.7.26 for bit definitions. H © 2006 Silicon Image, Inc. Register Name 31 16 IDE0 TF ...
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... Reserved This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 88 . See Section 9.7.27 for bit definitions. H © 2006 Silicon Image, Inc. Register Name 31 16 IDE0 TF Device ...
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... IDE1 Task File Command + Status This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset C4 . See Section 9.7.40 for bit definitions. H © 2006 Silicon Image, Inc. Register Name 31 16 IDE1 TF ...
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... Reserved This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset C8 . See Section 9.7.41 for bit definitions. H © 2006 Silicon Image, Inc. Register Name 31 16 IDE1 TF Device ...
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... This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to PCI Configuration Space, Offset 74 H © 2006 Silicon Image, Inc. Register Name 31 16 ...
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... This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to PCI Configuration Space, Offset 7C © 2006 Silicon Image, Inc. Reserved PRD Table Address – IDE1 and Base Address 5, Offset 0C ...
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... EEPROM Memory Address – Command and Status © 2006 Silicon Image, Inc. Register Name 31 16 PCI Bus Master Software Data Status – IDE0 PRD Table Address – IDE0 PCI Bus Master Reserved Status – IDE1 PRD Table Address – IDE1 ...
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... H C0 IDE1 TF Starting H Sector Number C4 IDE1 TF H Command+Status C8 Reserved H © 2006 Silicon Image, Inc. Register Name 31 16 Reserved FIFO Byte1 Read FIFO Byte0 Write Pointer – IDE0 Pointer – IDE0 FIFO Byte3 Read FIFO Byte2 Write Pointer – IDE0 Pointer – IDE0 FIFO Port – ...
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... Bit [18]: IDE0 DMA Comp (R/W1C) – IDE0 DMA Completion Interrupt. During write DMA operation, This bit set indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During Read DMA, This bit © 2006 Silicon Image, Inc. Register Name 31 16 IDE1 Read Ahead Data IDE1 TF ...
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... Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines the Descriptor Table base address. • Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read. © 2006 Silicon Image, Inc. Default Description XX Not cleared by any reset ...
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... Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines the Descriptor Table base address. • Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read. © 2006 Silicon Image, Inc. Reserved set indicates that ...
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... The properties of this bit field are detailed below. Bit Location [13:12] [11:10] [09:08] Table 9-9: Software Data Byte, Base Address 5, Offset 10 • Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read. © 2006 Silicon Image, Inc. Software set indicates that the IDE0 Default ...
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... If this bit is cleared while the PCI bus master is active, the operation will be aborted and the data discarded. While this bit is set, accessing IDE1 Task File or PIO data registers will be terminated with Target-Abort. © 2006 Silicon Image, Inc. Reserved set ...
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... This register reflects the current DMA1 Address and uses for diagnostic purposes only. • Bit [31:00]: PRD Address (R) – This field is the current DMA1 Address. © 2006 Silicon Image, Inc. PRD Address Byte Count Low PRD Address 76 Silicon Image, Inc ...
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... DMA0 read request priority is set to 1 whenever the FIFO has greater than 63 Dwords available space. This bit field is useful when two DMA channels are competing for accessing the PCI bus. © 2006 Silicon Image, Inc. FIFO Wr Req Ctrl – IDE0 ...
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... PCI bus has the same or higher priority, it remains controlling the bus. However, if the channel requesting the PCI bus has higher priority, the lower priority channel terminates the PCI transaction, yielding the bus to the channel with the higher priority. © 2006 Silicon Image, Inc. FIFO Wr Req Ctrl – IDE1 indicates empty, while a value of 100 ...
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... This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never cleared by any type of reset. © 2006 Silicon Image, Inc. Reserved Reserved = 100 MHz ...
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... Bit [31:08]: Reserved (R). • Bit [07:00]: Memory Data (R/W) – FLASH Memory Data. This bit field is used for FLASH write data on a write operation, and returns the FLASH read data on a read operation. © 2006 Silicon Image, Inc. Reserved Reserved 80 Silicon Image, Inc. ...
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... Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read. • Bit [07:00]: Memory Data (R/W) – EEPROM Memory Data. This bit field is used for EEPROM write data on a write operation, and returns the EEPROM read data on a read operation. © 2006 Silicon Image, Inc. Reserved Reserved 81 ...
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... Bit [07:00]: FIFO Byte 0 Rd Pointer – IDE0 (R) FIFO Byte 0 Read Pointer. This bit field provides the status on the read pointer for Byte 0. © 2006 Silicon Image, Inc. FIFO Port – IDE0 FIFO Byte 1 Rd Pointer – IDE0 FIFO Byte 0 Wr Pointer – IDE0 82 Silicon Image, Inc ...
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... The system can read from or write to this register for direct access to the data FIFO between the PCI bus and IDE Channel #1. While DMA1 is active, reading this register will be terminated with Target- Abort. © 2006 Silicon Image, Inc. FIFO Byte 3 Rd Pointer – IDE0 FIFO Byte 2 Wr Pointer – IDE0 FIFO Port – ...
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... Bit [07:00]: FIFO Byte 2 Rd Pointer – IDE1 (R) FIFO Byte 2 Read Pointer. This bit field provides the status on the read pointer for Byte 2. © 2006 Silicon Image, Inc. FIFO Byte 1 Rd Pointer – IDE1 FIFO Byte 0 Wr Pointer – IDE1 FIFO Byte 3 Rd Pointer – IDE1 FIFO Byte 2 Wr Pointer – ...
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... Bit [15:08]: IDE0 Task File Cylinder High (R/W). This bit field defines the IDE0 Task File Cylinder High register. • Bit [07:00]: IDE0 Task File Cylinder Low (R/W). This bit field defines the IDE0 Task File Cylinder Low register. © 2006 Silicon Image, Inc. IDE0 Task File Sector Count IDE0 Task File Features (W) ...
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... This register defines the read ahead data port for PIO transfers on IDE Channel #0 in the SiI 0680A. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. © 2006 Silicon Image, Inc. IDE0 Task File Device Control Reserved ...
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... Bit [15:08]: IDE0 Task File Cylinder High (R/W). This bit field defines the IDE0 Task File Cylinder High register. • Bit [07:00]: IDE0 Task File Cylinder Low (R/W). This bit field defines the IDE0 Task File Cylinder Low register. © 2006 Silicon Image, Inc. IDE0 Task File Sector Count IDE0 Task File Features (W) ...
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... SiI 0680A. In Virtual DMA mode (PCI bus master DMA with PIO transfers on the IDE), all 32 bits are used as the word- aligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte count. The higher 16 bits must be programmed 0x0000. © 2006 Silicon Image, Inc. Reserved IDE0 Virtual DMA/PIO Read Ahead Byte Count 88 Silicon Image, Inc ...
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... Bit [00]: Cable 80 (R) – IDE0 Cable 80 Detection. This bit provides real-time status of the inverted version of the IDE0_CBLID_N pin. When set, it indicates that 80 pin cable is detected. © 2006 Silicon Image, Inc. Recovery Count 89 SiI0680A PCI to IDE/ATA ...
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... Bit [05:00]: Device 0 Recovery Count (R/W) – IDE0 Device 0 DIOR_N and DIOW_N Recovery Time Count for PIO Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode. © 2006 Silicon Image, Inc. Device 1 Recovery Device 0 Addr Device 0 Active Count ...
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... Bit [05:00]: Device 0 Recovery Count (R/W) – IDE0 Device 0 DIOR_N and DIOW_N Recovery Time Count for DMA Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. © 2006 Silicon Image, Inc. Device 1 Recovery Device 0 Addr Device 0 Active Count ...
Page 92
... Bit [06]: Reserved (R/W) – This bit field is reserved. • Bit [05:00]: Device 0 Cycle Time Count (R/W) – IDE0 Device 0 UDMA Cycle Time Count. This bit field is used for programming the UDMA Active and Recovery Time © 2006 Silicon Image, Inc. Device 1 Cycle Time Count 92 Silicon Image, Inc ...
Page 93
... B • Bit [15:00]: Data Field (R/W) – IDE0 Test Data Field. This bit field is used to write a preload value to the selected counter or read the current value of the selected counter. © 2006 Silicon Image, Inc. Sub-Module Select = TMR module; 0011 = PIF module; and, 0100 B ...
Page 94
... Bit [15:08]: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. © 2006 Silicon Image, Inc. Reserved = PIO transfer with IORDY not monitored normal DMA ...
Page 95
... Bit [23:16]: IDE1 Task File Auxiliary Status (R). This bit field defines the IDE1 Task File Auxiliary Status register. • Bit [15:00]: Reserved (R). This bit field is reserved and returns zeros on a read. © 2006 Silicon Image, Inc. IDE1 Task File Device+Head IDE1 Task File Cylinder High IDE1 Task File Device Control ...
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... Bit [15:08]: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active. © 2006 Silicon Image, Inc. IDE1 Read Ahead Data IDE1 Task File Sector Count ...
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... This bit field is reserved and returns an indeterminate value on a read. © 2006 Silicon Image, Inc. IDE1 Task File Device+Head IDE1 Task File Cylinder High ...
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... Bit [03]: Channel Tri-State (R/W) – IDE1 Channel Tri-State. This bit is set to tri-state the IDE Channel #1 bus. This bit is cleared for normal operations. • Bit [02]: Channel Rst (R/W) – IDE1 Channel Reset. When this bit is set, IDE Channel # 1 RST signal is asserted. © 2006 Silicon Image, Inc. IDE1 Virtual DMA/PIO Read Ahead Byte Count Recovery Count 98 Silicon Image, Inc. ...
Page 99
... Bit [05:00]: Device 0 Recovery Count (R/W) – IDE1 Device 0 DIOR_N and DIOW_N Recovery Time Count for PIO Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. © 2006 Silicon Image, Inc. Device 1 Recovery Device 0 Addr Device 0 Active Count ...
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... UDMA mode. • Bit [13:12]: Device 0 DSTROBE Delay (R/W) – IDE1 Device 0 DSTROBE Delay for UDMA Mode. This bit field is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode. © 2006 Silicon Image, Inc. Device 1 Recovery Device 0 Addr Device 0 Active Count ...
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... B • Bit [15:00]: Data Field (R/W) – IDE1 Test Data Field. This bit field is used to write a preload value to the selected counter or read the current value of the selected counter. © 2006 Silicon Image, Inc. Sub-Module Select = TMR module; 0011 = PIF module; and, 0100 B ...
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... Bit [01:00]: Device 0 Transfer Mode (R/W) – IDE0 Device 0 Data Transfer Mode. This bit field is used to set the data transfer mode on IDE side during PCI DMA transfer: 00 PIO transfer with IORDY monitored; 10 When this bit field is set to value other than 00 © 2006 Silicon Image, Inc. Reserved = PIO transfer with IORDY not monitored normal DMA ...
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... PCI_CLK (Test Clock) IDE0_DMARQ (Test Clock) IDE0_CBLID_N (Test Clock) IDE1_CBLID_N To all scan flip flops SCAN_EN Figure 10-1: SiI 0680A Clocking System and Test Feature Diagram © 2006 Silicon Image, Inc. 10. Design for Testability SYS_NAND_TEST Nand Tree Normal Function Normal Function 4K & 33 MHz 2 ...
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... PCB and package pins (signal pins only), in lieu of full JTAG boundary scan. When the SiI 0680A is programmed for NAND tree test mode, all outputs and bi-directional pins are set to input mode. A logic representation of the NAND tree is shown in Fig. 10-2. Refer to Table 10-2 for the NAND tree order. © 2006 Silicon Image, Inc ...
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... IDE0_DD07 9 IDE0_DD08 10 IDE0_DD09 11 IDE0_DD10 12 IDE0_DD11 13 IDE0_DD12 14 IDE0_DD13 15 IDE0_DD14 16 IDE0_DD15 17 IDE0_CS0_N 18 IDE0_CS1_N 19 IDE0_DA0 20 IDE0_DA1 © 2006 Silicon Image, Inc. NAND Test Mode Normal Function 0 1 Figure 10-3: SiI 0680A NAND Tree Order Pin Name 33 IDE1_DD03 34 IDE1_DD04 35 IDE1_DD05 36 IDE1_DD06 37 IDE1_DD07 38 IDE1_DD08 39 IDE1_DD09 40 IDE1_DD10 41 IDE1_DD11 ...
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... Additionally, SCAN_EN selects between normal inputs and scan inputs at all the scan flip-flops is provided by the input pin SCAN_EN. There are six scan chains with input pins and output pins as follows: SCAN CHAIN SCAN INPUT PIN 1 IDE0_DMARQ IDE1_DMARQ 5 6 © 2006 Silicon Image, Inc. 53 IDE1_CBLID_N 54 IDE1_DMACK_N 55 IDE1_INTRQ 56 IDE1_IORDY 57 IDE1_DMARQ 58 IDE1_RST_N ...
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... SCAN_MODE BA5_EN & PLL_TEST_CLK_SEL & PLL_TEST_MODE TEST_MODE & PCI_GNT_N ( FB Clock ) PLL (Ref Clock) PCI_CLK (Test Clock) IDE0_DMARQ PLL_CPBIAS © 2006 Silicon Image, Inc. Normal Function 4K & 33 MHz Figure 10-4: PLL Test Logic 107 SiI0680A PCI to IDE/ATA Data Sheet 0 MEM_CS_N 1 ...
Page 108
... Programming bits [31:24] in the IDEx Task File Register 1 register with the value = 91 • Wait for the command to complete. This can be accomplished by waiting for an interrupt if interrupts have been enabled at both the controller and the device. If interrupts are not © 2006 Silicon Image, Inc. 11. Programming Sequences . ...
Page 109
... ATA/ATAPI device: Set the task file register access timing. The task file register timing is set by programming bits [31:16] of the IDEx Task File Timing + Configuration + Status register. See section 13.2.1 for recommended values to © 2006 Silicon Image, Inc. 109 SiI0680A PCI to IDE/ATA Data Sheet ...
Page 110
... PIO mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for PIO mode data transfer per the instructions in section 11.3, PIO read/write operations may be performed by following the programming sequence described below. © 2006 Silicon Image, Inc. 110 Silicon Image, Inc. ...
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... IDEx Task File Timing + Config + Status register. The following programming sequences are needed for each PIO Mode Read/Write Operation with the watchdog timer enabled: Issue a Read/Write PIO Command to the ATA drive following the steps in section 11.4. © 2006 Silicon Image, Inc. 111 SiI0680A PCI to IDE/ATA Data Sheet ...
Page 112
... Write 1 to bit 18 of the PCI Bus Master – IDEx Register to clear the ATA interrupt error, repeat the write operation steps until all data for the write command has been transferred or an error has been detected. © 2006 Silicon Image, Inc. 112 Silicon Image, Inc. ...
Page 113
... The controller had a problem transferring data to/from memory. B 100 = Normal completion. B 101 = If the IDE device does not report an error, then the PRD specified a size that is larger than B the IDE transfer size. © 2006 Silicon Image, Inc. 113 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
Page 114
... ATA/ATAPI device interrupt due to this race condition necessary to re-read the channel’s IDEx Task File Timing + Configuration + Status register after disabling DMA operation and examining bit © 2006 Silicon Image, Inc. To prevent missing an 114 Silicon Image, Inc ...
Page 115
... Task File Timing + Configuration + Status register after disabling DMA operation and examining bit 11. If bit 11 is set, the ATA/ATAPI device is interrupting and should be serviced by following the steps below (assuming that the virtual DMA operation completed successfully). © 2006 Silicon Image, Inc. To prevent missing an 115 ...
Page 116
... If operating in Large Block Transfer mode, this field contains the least significant 16-bits of the size of the memory region. Bits 62:48 If not operating in Large Block Transfer mode, this field is unused. © 2006 Silicon Image, Inc. register associated with the ATA/ATAPI device needs When performing DMA in Large Block Transfer mode, the 680A ...
Page 117
... If operating in Large Block Transfer mode, this field contains the most significant 15-bits of the size of the memory region. Bit 63 When set, this bit indicates that this is the last entry in the PRD table. Table 11-1, Physical Region Descriptor (PRD) Format © 2006 Silicon Image, Inc. 117 SiI0680A PCI to IDE/ATA Data Sheet SiI-DS-0069-C ...
Page 118
... It reads zero when the memory access is complete. Read the data from the FLASH memory access. The data field is defined by bits [07:00] in the FLASH Memory Data register at Offset 54 © 2006 Silicon Image, Inc. of Base Address 5. The bit reads one when Base Address 5 ...
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... Check bit 28 in the EEPROM Memory Address – Command + Status register. The bit is set if an error occurred during a previous memory access. Read the data from the EEPROM memory access. The data field is defined by bits [07:00] in the EEPROM Memory Data register at Offset 5C © 2006 Silicon Image, Inc. of Base Address Base Address 5. ...
Page 120
... In the UDMA timing register. the number of clocks is always 1 greater than the value loaded for the cycle time count. The only exception is that value "0" requires two cycles. © 2006 Silicon Image, Inc. 13. SiI 0680A Timing Registers Active Time in PCI Clock ...
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... PIO Timing Register 13.2.4 UDMA Timing Register Programming in Number of 100 MHz IDE clock UDMA 0 UDMA Cycle 13.2.4 UDMA Timing Register Programming in Number of 133 MHz IDE clock UDMA 0 UDMA Cycle © 2006 Silicon Image, Inc ...
Page 122
... IDE1 Task File Region (BA5 + (C0h-CFh)). Impact: May result in system errors in some systems. Workaround: At present this has only been observed in an environment in which conditions have been forced with a PCI bridge device. No tested motherboards have experienced problems. © 2006 Silicon Image, Inc. 122 Silicon Image, Inc. 14. Errata ...
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... The products and services described in these materials, and any other information, services, designs, know-how and/or products provided by Silicon Image, Inc. and/or its affiliates are provided on as “AS IS” basis, except to the extent that Silicon Image, Inc. and/or its affiliates provides an applicable written limited warranty in its standard form license agreements, standard Terms and Conditions of Sale and Service or its other applicable standard form agreements, in which case such limited warranty shall apply and shall govern in lieu of all other warranties (express, statutory, or implied) ...
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... SiI0680A PCI to IDE/ATA Data Sheet Further Information To request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit the Silicon Image, Inc. web site at www.siliconimage.com. © 2006 Silicon Image, Inc. T 408.616.4000 F 408.830.9530 124 Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 www ...