HYB25DC512160CE-5 Qimonda AG, HYB25DC512160CE-5 Datasheet
HYB25DC512160CE-5
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HYB25DC512160CE-5 Summary of contents
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HYB25DC512800C[E/F], HYB25DC512160C[E/F] Revision History: 2006-12, Rev. 1.3 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition Previous Revision: 2006-09, Rev. 1.2 We Listen to Your Comments Any information within this document that you feel is ...
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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics. 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and ...
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... Part Number Org. CAS-RCD-RP Latencies ×8 HYB25DC512800CE–5 3-3-3 HYB25DC512800CF-5 ×16 HYB25DC512160CF-5 HYB25DC512160CE-5 ×8 HYB25DC512800CE-6 2.5-3-3 HYB25DC512800CF-6 ×16 HYB25DC512160CF-6 HYB25DC512160CE-6 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers ...
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Chip Configuration The pin configuration of a DDR SDRAM is listed by function in explained in Table 4 and Table 5 respectively. The pin numbering for FBGA is depicted in package in Figure 2 Ball#/Pin# Name Pin Type Clock ...
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Ball#/Pin# Name Pin Type Data Signals ×8 organization A8, 2 DQ0 I/O B7, 5 DQ1 I/O C7, 8 DQ2 I/O D7, 11 DQ3 I/O D3, 56 DQ4 I/O C3, 59 DQ5 I/O B3, 62 DQ6 I/O A2, 65 DQ7 I/O ...
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Ball#/Pin# Name Pin Type A9, B2, C8, D2, V PWR DDQ E8 15, 55, 61 A7, F8, M7 PWR DD 18, 33 A1, B8, C2, D8, V PWR SSQ E2, 6, 12, 52, 58, 64 A3, ...
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Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminalted Logic (SSTL2) LV-CMOS Low ...
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Pin Configuration PG-TFBGA-60 Top View, see the balls through the package Rev. 1.3, 2006-12 03292006-W2FE-ELDX HYB25DC512[800/160]C[E/F] 512-Mbit Double-Data-Rate SDRAM 9 Internet Data Sheet FIGURE 1 ...
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Rev. 1.3, 2006-12 03292006-W2FE-ELDX HYB25DC512[800/160]C[E/F] 512-Mbit Double-Data-Rate SDRAM Pin Configuration PG-TSOPII-66 10 Internet Data Sheet FIGURE 2 ...
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Functional Description The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512-Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. ...
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Field Bits Type Description BL [2:0] W Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001 2 B 010 4 B 011 Burst ...
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Burst Length Starting Column Address ...
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Field Bits Type Description DLL 0 w DLL Status Drive Strength MODE [12:3] Operating Mode 00000000000 Notes 1. A2 must provide compatibility with early DDR devices ...
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Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) ...
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Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks Idle H L Bank(s) Active ...
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This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes ...
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Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active ...
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Concurrent Auto Precharge:This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the ...
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Electrical Characteristics This chapter describes the electrical characteristics. 4.1 Operating Conditions This chapter contains the operating conditions tables. Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply ...
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Parameter Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS These values are guaranteed by design and are tested on a sample base only /2, (Peak to Peak) 0.2 V. Unused pins are ...
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not applied directly to the device must track variations in the DC level Inputs are not recognized as valid until the magnitude of the difference between the input ...
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AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing. Notes V 1. All voltages referenced Tests ...
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Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs V = 2.5 V ...
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Parameter Symbol t DQ and DM input setup time DS t DQS falling edge hold time from DSH CK (write cycle) t DQS falling edge to CK setup DSS time (write cycle) t Clock Half Period HP t Data-out high-impedance ...
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Parameter Symbol t Write preamble setup time WPRES t Write postamble WPST t Write recovery time WR t Internal write to read command WTR delay t Exit self-refresh to non-read XSNR command t Exit self-refresh to read command XSRD 1) ...
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Parameter Active Standby Current: one bank active; CS ≥ V inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs ...
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Symbol –6 DDR333 I 70 DD0 DD1 95 I 4.6 DD2P I 25 DD2F I 22 DD2Q I 15 DD3P I 37 DD3N DD4R 115 I 90 DD4W 120 I 175 DD5 I 5 ...
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Current Measurement Conditions Legend Activate Read Read with Autoprecharge Precharge NOP or DESELECT I : Operating Current: One Bank Operation DD1 1. General test condition t a) Only one ...
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Package Outlines There are PG-TFBGA-60 and PG-TSOPII-66 package types used for this product family. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-W2FE-ELDX HYB25DC512[800/160]C[E/F] 512-Mbit Double-Data-Rate SDRAM Package ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2006-12 03292006-W2FE-ELDX HYB25DC512[800/160]C[E/F] 512-Mbit Double-Data-Rate SDRAM Package Outline PG-TFBGA-60 31 Internet Data Sheet FIGURE 5 ...
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List of Figures Figure 1 Pin Configuration PG-TFBGA-60 Top View, see the balls through the package . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Edition 2006-12 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party ...