HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet
HYB18H512321BF-08/10
Related parts for HYB18H512321BF-08/10
HYB18H512321BF-08/10 Summary of contents
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... Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 05292007-WAU2-UU95 2 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 ...
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... Overview This chapter lists all main features of the product family HYB18H512321BF and the ordering information. 1.1 Features V • 2 voltage HYB18H512321BF–08/10 DDQ V • 2.0 V core voltage HYB18H512321BF–08/ • 1 voltage HYB18H512321BF–11/12/14 DDQ V • 1.8 V core voltage HYB18H512321BF–11/12/14 DD • Organization: 2048K × 32 × 8 banks • ...
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... References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar fashion. Read and write accesses to the HYB18H512321BF are burst oriented. The burst length is fixed to 4 and 8 and the two least significant bits of the burst address are “Don’t Care” and internally set to LOW. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command ...
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... V J DDQ A11 DDQ SSQ DDQ SSQ V SEN RESET 5 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE DDQ V DQ9 DQ8 SSQ SSQ V DQ11 DQ10 DDQ DDQ V RDQS1 WDQS1 SSQ SSQ V DM1 ...
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... Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED MODE REGISTER SET commands. Rev. 1.1, 2007-09 05292007-WAU2-UU95 6 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 2 Ball Description ...
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... CMOS input. RES is not internally terminated. When RES is at LOW state the DDQ V CMOS input. This pin must be hardwired on board either to a power DDQ HIGH H10 F9 7 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 3 Ball Assignment with Mirror Signal RAS CAS ...
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... H11 K10 L9 K11 H10 Rev. 1.1, 2007-09 05292007-WAU2-UU95 HIGH H11 K10 K11 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 Signal WE CS CKE A10 A11 BA0 BA1 BA2 ...
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... ACT, PRE, WRITE, WRITE/A, READ, READ/A 10) - 12) - ACT 12) - 13) - 12) - 14) - 14) - 15 RCD t 9 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 4 Function Truth Table 11 PRE command on another bank is allowed RRD is met. WTR t is met. RD/A is not allowed during WTR RRD ...
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... DESEL or NOP Exit Power Down DESEL or NOP Exit Self Refresh DESEL or NOP Entry Precharge Power Down DESEL or NOP Entry Active Power Down Auto Refresh Entry Self Refresh 10 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 t . MRD TABLE period. A minimum of 1000 clock XSR ...
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... BIT# BALL BIT# BALL 25 K-11 37 R-10 26 K-10 38 T-11 27 K-9 39 T-10 28 M-9 40 T-3 29 M-11 41 T-2 30 L-10 42 R-3 31 N-11 43 R-2 32 M-10 44 P-3 33 N-10 45 P-2 34 P-11 46 N-3 35 P-10 47 M-3 36 R-11 48 N-2 11 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 6 Boundary Scan Exit Order BIT# BALL BIT# BALL 49 L-3 61 G-4 50 M-2 62 F-4 51 M-4 63 F-2 52 K-4 64 G-3 53 K-3 65 E-2 54 K-2 66 F-3 55 L-4 67 E-3 56 J-3 57 J-2 58 H-2 59 H-3 60 H-4 ...
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... Tester needs to overdrive this pin to guarantee the required input logic level in scan mode the device. No initialization sequence of the device is DD DDQ 12 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 7 Scan Pin Description V or GND through a resistor DD ...
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... The Mode Register Bitmap is supported in two configurations. The first configuration is intended to support the Mid-Range- Speed application. The second configuration supports higher clock cycles for CAS latency and is therefore prepared to support high-speed application. The selected configuration is defined by Bit0 of EMRS2. 13 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 t MRD ...
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... Rev. 1.1, 2007-09 05292007-WAU2-UU95 Mode Register Bitmap for Mid-Range-Speed Application 14 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE 3 ...
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... The starting location within this block is determined by the Rev. 1.1, 2007-09 05292007-WAU2-UU95 Mode Register Bitmap for High-Speed Application MRS NOP NOP A.C. t MRD t MRDR 15 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE 4 FIGURE 5 Mode Register Set Timing NOP RD MRS: MRS command PA: PREALL command A.C.: Any other command as READ RD: READ command Don't Care ...
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... Receivers are off and will be switched on by Write command and will be switched off again after WL+BL The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in Rev. 1.1, 2007-09 05292007-WAU2-UU95 Order of Accesses within a Burst (Type = sequential) 0-1-2-3 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 ON/OFF mode of DQ/DM receivers 16 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 8 Burst Definition TABLE 9 Table 9. ...
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... A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of operations once the DLL reset is completed. Rev. 1.1, 2007-09 05292007-WAU2-UU95 17 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 ...
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... The Extended Mode Register must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time operation (Figure 9). The timing of the EMRS command operation is equivalent to the timing of the MRS command operation. 18 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 t before initiating any subsequent MRD ...
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... Figure 8 is more focused on the high-range-speed application. Both bitmaps Extended Mode Register Bitmap for High-Speed Application 19 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE Rtt Data Z Output Driver A1 A0 Impedance 0 0 Autocal ...
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... NOP MRD A.C.: Any command EMRS: Extended MRS command Don't Care PA: ≥ where is the clock cycle time. The high-speed bitmap Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 t (in ns) and rounding [ns] / [ns]). The WR CK FIGURE 9 NOP A.C. PREALL command ...
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... Timing of Vendor Code and Revision ID Generation on DQ[7: N/D N/D N/D N/D N/D EMRS Add Vendor Code and Revision ID 21 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 10 Revision ID and Vendor Code FIGURE N/D N/D N/D t RIDoff EMRS: Extended Mode Register Set Command Add: Address N/D: NOP or Deselect ...
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... The controller must wait the specified time subsequent operation. The timing of the EMRS2 command operation is equivalent to the timing of the MRS command operation. 22 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 t before initiating any MRD FIGURE 12 Extended Mode Register 2 Bitmap ...
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... J I — OUT Power & DC Operation Conditions (0 °C ≤ T Symbol Limit Values Min. Typ 1.9 2.0 DD DDA V 1.9 2.0 DDQ 23 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 11 Absolute Maximum Ratings Rating Unit Max. 2.5 V 2.5 V 2.5 V 2.5 V °C +150 °C +125 50 mA TABLE 12 ≤ 85 °C) ...
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... CLK Input leakage current Output leakage current tracks with . AC parameters are measured with DDQ DD 2) HYB18H512321BF–11/12/14 3) HYB18H512321BF–08/ expected to equal 70% of for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise REF DDQ ...
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... ID(DC) V 0.5 ID(AC) V 0.7 × V – 0.15 IX(AC) DDQ V of the transmitting device and must track variations in the DC level of the same. DDQ V DDQ 60 Ohm DQ Test point DQS 25 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 14 ≤ 85 °C) c Unit Note Max. 0.7 × 0.10 V DDQ 0.3 V DDQ DDQ ...
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... Pull-Down and Pull-Up IV characteristics. Rev. 1.1, 2007-09 05292007-WAU2-UU95 Pin Capacitances (VDDQ = 1 25° MHz) Symbol Min. Max. CI,CCK 1.0 2.5 CIO 2.0 3.0 40 Ohm Driver Pull-Down and Pull-Up Characteristics 26 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 15 Unit Note pF pF FIGURE 14 ...
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... The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 Ω, setting the nominal DQ termination impedance to 60 Ω. (Extended Mode Register programmed to ZQ/4). Rev. 1.1, 2007-09 05292007-WAU2-UU95 Programmed Driver IV Characteristics at 40 Ohm Pull-Up Current (mA) Maximum Minimum 3.04 -2.44 5.98 -4.79 8.82 -7.03 11.56 -9.18 14.19 -11.23 16.72 -13.17 19.14 -15.01 21.44 -16.74 23.61 -18.37 26.10 -19.90 28.45 .21.34 30.45 -22.72 32.73 -24.07 34.95 -25.40 37.10 -26.73 39.15 -28.06 41.01 -29.37 42.53 -30.66 43.71 — 44.89 — 27 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 16 Maximum -3.27 -6.42 -9.45 -12.37 -15.17 -17.83 -20.37 -22.78 -25.04 -27.17 -29.17 -31.25 -33.00 -35.00 -37.00 -39.14 -41.25 -43.29 -45.23 -47.07 ...
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... IV characteristic. Voltage (V) Terminator Pull-Up Current (mA) Minimum Maximum 0.1 -1.63 -2.18 0.2 -3.19 -4.28 0.3 -4.69 -6.30 0.4 -6.12 -8.25 0.5 -7.49 -10.11 0.6 -8.78 -11.89 0.7 -10.01 -13.58 0.8 -11.16 -15.19 0.9 -12.25 -16.69 1.0 -13.27 -18.11 Rev. 1.1, 2007-09 05292007-WAU2-UU95 60 Ohm Active Termination Characteristic Programmed Terminator Characteristics at 60 Ohm Voltage (V) Terminator Pull-Up Current (mA) Minimum 1.1 -14.23 1.2 -15.14 1.3 -16.04 1.4 -16.94 1.5 -17.82 1.6 -18.70 1.7 -19.58 1.8 -20.44 1.9 — 2.0 — 28 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE 15 TABLE 17 Maximum -19.45 -20.83 -22.00 -23.33 -24.67 -26.09 -27.50 -28.86 -30.15 -31.38 ...
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... IV characteristic. Voltage (V) Terminator Pull-Up Current (mA) Minimum Maximum 0.1 -0.81 -1.09 0.2 -1.60 -2.14 0.3 -2.34 -3.15 0.4 -3.06 -4.12 0.5 -3.74 -5.06 0.6 -4.39 -5.94 0.7 -5.00 -6.79 0.8 -5.58 -7.59 0.9 -6.12 -8.35 1.0 -6.63 -9.06 Rev. 1.1, 2007-09 05292007-WAU2-UU95 120 Ohm Active Termination Characteristic Programmed Terminator Characteristics of 120 Ohm Voltage (V) Terminator Pull-Up Current (mA) Minimum 1.1 -7.11 1.2 -7.57 1.3 -8.02 1.4 -8.47 1.5 -8.91 1.6 -9.35 1.7 -9.79 1.8 -10.22 1.9 — 2.0 — 29 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE 16 TABLE 18 Maximum -9.72 -10.42 -11.00 -11.67 -12.33 -13.05 -13.75 -14.43 -15.08 -15.69 ...
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... ADD/CMD termination IV characteristic. Voltage (V) Terminator Pull-Up Current (mA) Minimum Maximum 0.1 -0.41 -0.55 0.2 -0.80 -1.07 0.3 -1.17 -1.58 0.4 -1.53 -2.06 0.5 -1.87 -2.53 0.6 -2.20 -2.97 0.7 -2.50 -3.40 0.8 -2.79 -3.80 0.9 -3.06 -4.17 1.0 -3.32 -4.53 Rev. 1.1, 2007-09 05292007-WAU2-UU95 240 Ohm Active Termination Characteristic Programmed Terminator Characteristics at 240 Ohm Voltage (V) Terminator Pull-Up Current (mA) Minimum 1.1 -3.56 1.2 -3.79 1.3 -4.01 1.4 -4.23 1.5 -4.46 1.6 -4.68 1.7 -4.90 1.8 -5.11 1.9 — 2.0 — 30 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE 17 TABLE 19 Maximum -4.86 -5.21 -5.50 -5.83 -6.17 -6.52 -6.88 -7.21 -7.54 -7.85 ...
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... Operating Currents 5.10.1 Operating Current Ratings for HYB18H512321BF Parameter Operating Current Operating Current Precharge Power-Down Standby Current Precharge Floating Standby Current Precharge Quiet Standby Current Active Power-Down Standy Current Active Standby Current Operating Current Burst Read Operating Current Burst Write t t Auto-Refresh Current ( ...
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... CKE is HIGH HIGH between valid commands; Other command REFI (min); = RCD RCDRD RRD RRD 32 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 21 ); Address and control inputs are Address and control inputs RAS RAS,max I (min); =0 mA; Address and control inputs out ...
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... TABLE is defined as inputs are stable at a HIGH level. SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals, and inputs changing 50% of each data transfer for DQ signals. Rev. 1.1, 2007-09 05292007-WAU2-UU95 DDQ 33 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 ...
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... AC Timings for HYB18H512321BF Parameter CAS latency Symbol Clock and Clock Enable f System CL=13 CK13 frequency f CL= 12 CK12 f CL= 11 CK11 f CL =10 CK10 CK9 CK8 CK7 t Clock high level width CH t Clock low-level width CL t Minimum clock half period HP Command and Address Setup and Hold Timing ...
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... HP QHS — 32 — 32 — 32 3.9 3.9 3.9 35 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 Unit Note –12 –14 Max — 2 — — 5 — WL– ...
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... CK 36 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 Unit Note –12 –14 Max. 52.0 — 52.0 — 1000 — 1000 — — 6 — — 10 — — 10 — ...
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... Package 6.1 Package Outline Note: The package is conforming with JEDEC MO-207i, VAR DR-z. Rev. 1.1, 2007-09 05292007-WAU2-UU95 Package Outline PG-TFBGA-136-054 37 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 FIGURE 18 ...
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... Theta_jB: Junction to Board thermal resistance. The value has been obtained by simulation. 3. Theta_jC: Junction to Case thermal resistance. The value has been obtained by simulation. Rev. 1.1, 2007-09 05292007-WAU2-UU95 PG-TFBGA-136 Package Thermal Resistances Theta_jA 2s0p 3 m/s 0 m Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 TABLE 23 Theta_jB Theta_jC 3 m ...
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... Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14 40 Ohm Driver Pull-Down and Pull-Up Characteristics Figure 15 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16 120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18 Package Outline PG-TFBGA-136-054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Rev. 1.1, 2007-09 05292007-WAU2-UU95 39 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 ...
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... Table 18 Programmed Terminator Characteristics of 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 19 Programmed Terminator Characteristics at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating Current Ratings ( 0 °C ≤ T Table 20 Table 21 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 22 Timing Parameters for HYB18H512321BF Table 23 PG-TFBGA-136 Package Thermal Resistances Rev. 1.1, 2007-09 05292007-WAU2-UU95 ≤ 85 °C ≤ 85 °C ≤ ...
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... Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7.1 Driver IV characteristics at 40 Ohms 5.7.2 Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8 Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.9 Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.10 Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.10.1 Operating Current Ratings for HYB18H512321BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.11 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.12 AC Timings for HYB18H512321BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Rev. 1.1, 2007-09 05292007-WAU2-UU95 41 ...
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... Package Thermal Characteristics Rev. 1.1, 2007-09 05292007-WAU2-UU95 42 Internet Data Sheet HYB18H512321BF 512-Mbit GDDR3 ...
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Edition 2007-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...