EM638325TS Etron Technology Inc., EM638325TS Datasheet

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EM638325TS

Manufacturer Part Number
EM638325TS
Description
Manufacturer
Etron Technology Inc.
Datasheet

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Etron Confidential
Features
• Fast access time: 5.5/5.5 ns
• Fast Clock rate: 166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Four internal banks (512K x 32bit x 4bank)
• Programmable Mode
• Burst stop function
• Individual byte controlled by DQM0-3
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• 86-pin 400 x 875 mil plastic TSOP II package,
Overview
CMOS synchronous DRAM containing 64 Mbits. It
is internally configured as a quad 512K x 32 DRAM
with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 512K x 32 bit banks is organized
as 2048 rows by 256 columns by 32 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue
for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth.
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345
Etron Technology, Inc. reserves the right to change products or specification without notice.
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Pb free and Halogen free
0.50mm pin pitch
The EM638325 SDRAM is a high-speed
The EM638325 provides for programmable
By having a programmable mode register, the
FAX: (886)-3-5778671
2M x 32 bit Synchronous DRAM (SDRAM)
Table 1. Key Specifications
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK (max.)
tRAS Row Active time(min.)
tRC
Table 2.Ordering Information
TS: indicates TSOPII Package,
G: indicates Pb and Halogen Free for TSOPII Package
Figure 1. Pin Assignment (Top View)
A10/AP
EM638325TS-6G
EM638325TS-7G
VDDQ
DQM0
DQM2
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDDQ
CAS#
RAS#
VSSQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
WE#
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDD
CS#
BA0
BA1
NC
NC
NC
A0
A1
A2
Part Number
Row Cycle time(min.)
Preliminary (Rev 2.0 June /2009)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
1
2
5
6
7
8
9
3
4
EM638325
86
85
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
84
83
EM638325TS
Frequency
166MHz
143MHz
VSS
DQ15
VSSQ
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQM3
DQ14
DQ8
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A6
A5
A4
A3
VSS
NC
DQ31
VDDQ
DQ30
NC
A7
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Package
5.5/5.5ns
TSOP II
TSOP II
42/49 ns
60/70 ns
-6/7
6/7 ns

Related parts for EM638325TS

EM638325TS Summary of contents

Page 1

... CS# NC BA0 BA1 A10/ DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD EM638325TS Preliminary (Rev 2.0 June /2009) EM638325 Frequency 166MHz 143MHz 1 86 VSS 2 85 DQ15 3 84 VSSQ 4 83 DQ14 5 82 DQ13 6 81 VDDQ ...

Page 2

... ADDRESS BUFFER A9 BA0 BA1 REFRESH COUNTER Etron Confidential CONTROL SIGNAL GENERATOR MODE REGISTER 2 Rev 2.0 EM638325TS 2048 x 256 x 32 CELL ARRAY (BANK #0) Column Decoder DQ0 DQ Buffer DQ31 DQM0~3 2048 x 256 x 32 CELL ARRAY (BANK #1) Column Decoder 2048 x256 x 32 CELL ARRAY (BANK #2) ...

Page 3

... CLK. The I/Os are byte-maskable during Reads and Writes. No Connect: These pins should be left unconnected Supply DQ Power: Provide isolated power to DQs for improved noise immunity. V DDQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. V SSQ Etron Confidential EM638325TS 3 Rev 2.0 June 2009 ...

Page 4

... Supply Power Supply: +3.3V±0. Supply Ground V SS Etron Confidential EM638325TS 4 Rev 2.0 June 2009 ...

Page 5

... ( EM638325TS A A CS# RAS# CAS# WE# 10 0-9 Row address Column address (A0 ~ A7) L Column address ...

Page 6

... RCD R/W A with NOP NOP AutoPrecharge RAS# - Cycle time(t (max.). Therefore, the precharge function must be performed RAS (max.). At the end of precharge, the precharged bank is still in the idle RAS 6 EM638325TS (min.) from the time of RCD Tn+3 Tn+4 Tn+5 Tn+6 Bank B Bank A Row Addr. Row Addr. RAS# - RAS# delay time(t ...

Page 7

... DOUT (Burst Length = 4, CAS# Latency = NOP NOP NOP DOUT A DOUT B DOUT DOUT A DOUT B 0 (Burst Length = 4, CAS# Latency = EM638325TS NOP NOP NOP NOP DOUT A 3 DOUT A DOUT NOP NOP NOP ...

Page 8

... Must be Hi-Z before the Write Command (Burst Length ≥ 4, CAS# Latency = READ A NOP NOP NOP DOUT A 0 Must be Hi-Z before the Write Command (Burst Length ≧ 4, CAS# Latency = 3) 8 EM638325TS READ A WRITE A NOP NOP DIN A DIN A DIN ...

Page 9

... Latency = 2, 3) RCD WRITE A NOP NOP DIN A DIN A DIN The first data element and the write are registered on the same clock edge 9 EM638325TS Bank Row tRP NOP NOP Activate NOP DOUT DOUT A DOUT A 1 ...

Page 10

... READ B NOP NOP DIN A DOUT B don’t care 0 0 DIN A don’t care don’t care 0 (Burst Length = 4, CAS# Latency = EM638325TS NOP NOP NOP NOP DIN (Burst Length = NOP NOP NOP NOP ...

Page 11

... Figure 13. Write to Precharge + t (min.)}. At full-page burst, only the write operation Write A NOP NOP NOP Auto Precharge DIN A DIN EM638325TS tRP Activate NOP NOP ROW Don’t Care Bank A NOP NOP NOP NOP Activate ...

Page 12

... Vendor Use Only 0 1 Vendor Use Only Address Key t RP PrechargeAll Mode Register Set Command Figure 15. Mode Register Set Cycle 12 EM638325TS Burst Length A3 Type 0 Sequential 1 Interleave A1 A0 Burst Length ...

Page 13

... EM638325TS Interleave ...

Page 14

... CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. Etron Confidential CK A4 CAS# Latency 0 Reserved 1 Reserved 0 2 clocks 1 3 clocks X Reserved Test Mode 0 normal mode 1 Vendor Use Only X Vendor Use Only 14 EM638325TS Rev 2.0 June 2009 ...

Page 15

... WRITE A Burst Stop DIN A DIN A DIN A don’t care (min.). To provide the AutoRefresh command, all banks need to RC (min), must be met before successive auto refresh operations are RP 15 EM638325TS NOP NOP NOP NOP DOUT A 3 DOUT ...

Page 16

... During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. Etron Confidential EM638325TS (min.) because time is required for the XSR (min.) is required when the device exits from ...

Page 17

... T Symbol Parameter C Input Capacitance I C Input/Output Capacitance I/O Note: These parameters are periodically sampled and are not 100% tested. Etron Confidential Item = -2mA ) = 2mA ) OUT = 25° EM638325TS Rating Unit -6/7 - 1.0 ~ +4.6 -1 +70 - 55~ +150 260 1 0~70°C) A Min. Typ. Max. Unit Note 3 ...

Page 18

... A Symbol One bank active I DD1 I DD2N IH I DD2NS IH I DD2P I DD2PS (min DD3N I = ∞ DD3NS CK I DD4 I DD5 I DD6 18 EM638325TS - 6 -7 Unit Note Max. 180 155 200 180 3, 4 220 210 Rev 2.0 ...

Page 19

... CL 2.5 2 VIH (Max) = 4.6V for pulse width < 3ns. VIL (Min) = -1.5V for pulse SS . Input signals are changed one time during every EM638325TS -7 Max. Min. Max 100K 49 100K - ...

Page 20

... Transition (rise and fall) of input signals are in a fixed -0.5) ns should be added to the parameter & and V (simultaneously) when CKE= “L”, DQM= “H” and all input DD DDQ levels) to ensure DQ output is in high impedance EM638325TS 1.4V / 1.4V 2.4V / 0.4V 1ns 1.4V 1.4V 50Ω Z0=50Ω 30pF Rev 2.0 June 2009 ...

Page 21

... RC Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Activate Write with Activate Command Auto Precharge Command Bank B Command Bank A Bank B 21 EM638325TS T20 T21 Begin Auto Precharge Bank B CAy Ay0 Ay1 Ay2 Ay3 Write Precharge Command Command Bank A Bank A Don’ ...

Page 22

... Ax0 Ax1 t OH Activate Read Read with Command Command Auto Precharge Bank B Bank A Command Bank B 22 EM638325TS T11 T12 T13 T14 T15 T16 T10 Begin Auto t IH Precharge Bank B RAy RAy t RP Bx0 Bx1 t HZ Precharge Activate Command ...

Page 23

... DQM DQ Precharge All Auto Refresh Command Command Etron Confidential T11 T12 T13 T14 T15 T16 T17 T18 T19 Auto Refresh Command 23 EM638325TS T20 T21 T22 RAx RAx CAx t RCD Ax1 Ax0 Activate Read Command Command Bank A Bank A Don’t Care Rev 2 ...

Page 24

... Note(*):The Auto Refresh command can be issue before or after Mode Register Set command Etron Confidential T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Minimum for 2 Refresh Cycles are required t MRD (*) 2nd Auto Refresh 1st Auto Refresh Command Command 24 EM638325TS (*) Any Command Don’t Care Rev 2.0 June 2009 ...

Page 25

... T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 t XSR *Note 5 *Note *Note 6 *Note 7 Hi-Z Self Refresh Exit is required before exit from SelfRefresh. RAS 25 EM638325TS *Note 8 t PDE *Note 9 Auto Refresh Don’t Care Rev 2.0 June 2009 ...

Page 26

... Activate Read Cammand Command Bank A Bank A Etron Confidential T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Ax0 Ax1 Ax2 Ax3 Clock Suspend Clock Suspend Clock Suspend 3 Cycles 2 Cycles 1 Cycle 26 EM638325TS T22 t HZ Don’t Care Rev 2.0 June 2009 ...

Page 27

... Activate Read Cammand Command Bank A Bank A Etron Confidential T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ax1 Ax0 Ax2 Ax3 Clock Suspend Clock Suspend Clock Suspend 3 Cycles 2 Cycles 1 Cycle 27 EM638325TS t HZ Don’t Care Rev 2.0 June 2009 ...

Page 28

... DQM Hi-Z DQ DAx0 Activate Clock Suspend Cammand 1 Cycle Bank A Write Command Bank A Etron Confidential T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx1 DAx2 DAx3 Clock Suspend Clock Suspend 2 Cycles 3 Cycles 28 EM638325TS Don’t Care Rev 2.0 June 2009 ...

Page 29

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx t Ax2 Ax0 Ax1 Clock Suspension Read Clock Suspension End Command Start Bank A 29 EM638325TS (Burst Length=4, CAS# Latency=2) t PDE Valid HZ Ax3 PRECHARGE STANDBY Precharge Power Down Command Mode Exit ...

Page 30

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Read Precharge Command Command Command Bank A Bank A Bank A 30 EM638325TS RAz RAz CAz Az0 Activate Read Command Command Bank A Bank A Don’t Care Rev 2.0 June 2009 ...

Page 31

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Read Precharge Command Command Command Bank A Bank A Bank A 31 EM638325TS RAz RAz CAz Activate Read Command Command Bank A Bank A Don’t Care Rev 2.0 June 2009 ...

Page 32

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBx CBy Write Write Precharge Command Command Command Bank B Bank B Bank B 32 EM638325TS RBz RBz CBz DBz0 DBz1 Activate Write Command Command Bank B Bank B Don’t Care Rev 2.0 June 2009 ...

Page 33

... CAx RBy t RP Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Read Activate Activate Command Command Command Bank A Bank A Bank B Precharge Command Bank B 33 Rev 2.0 EM638325TS T20 T21 T22 CBy Ax4 Ax5 Ax6 Ax7 Read Command Bank B Don’t Care June 2009 ...

Page 34

... CAx t AC Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Activate Read Precharge Command Command Command Bank A Bank A Bank B 34 EM638325TS RBy CBy RBy t RP Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Activate Read Precharge Command Command Command Bank B Bank B Bank A Don’ ...

Page 35

... T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBx RBx CBx t t WR* RP Activate Precharge Write Command Command Command Bank B Bank B Bank A 35 EM638325TS RAy RAy CAy t WR* Activate Write Precharge Command Command Command Bank A Bank A Bank B Don’t Care Rev 2.0 June 2009 ...

Page 36

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax1 Ax2 Ax3 Ax0 DAy0 DAy1 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 36 EM638325TS CAz Az1 DAy3 Az0 The Read Data Read is Masked with a Command Two Clock Bank A Latency Don’t Care Rev 2.0 ...

Page 37

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax1 Ax2 Ax3 Ax0 DAy0 DAy1 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 37 EM638325TS CAz Az1 Az0 Az3 DAy3 The Read Data is Masked with a Two Clock Latency Read Command Bank A Don’ ...

Page 38

... Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Read Activate Read Read Command Command Command Command Bank B Bank B Bank B Bank B 38 EM638325TS CAy CBz Read Read Precharge Command Command Command Bank B Bank A Bank B Precharge Command Bank A Don’ ...

Page 39

... AC Ax0 Ax1 Ax2 Ax3 By0 By1 Bz0 Bx0 Bx1 Read Read Read Read Command Command Command Command Bank B Bank B Bank B Bank A 39 EM638325TS Ay1 Ay2 Bz1 Ay0 Ay3 Precharge Precharge Command Command Bank B Bank A Don’t Care Rev 2.0 June 2009 ...

Page 40

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBw CBx CBy CAy Write Write Write Write Write Command Command Command Command Command Bank B Bank B Bank B Bank A Bank B 40 EM638325TS CBz DBz2 DBz3 Precharge Command Bank B Precharge Command Bank A Don’t Care Rev 2.0 June 2009 ...

Page 41

... RP Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Read with Auto Precharge Command Read with Bank B Auto Precharge Command Bank A 41 EM638325TS T21 T22 Begin Auto Precharge Bank A RBy RAz RBy CBy RAz Ay1 Ay2 Ay3 By0 By1 By2 Activate Activate ...

Page 42

... Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Read with Read with Activate Auto Precharge Auto Precharge Command Command Command Bank B Bank A Bank B 42 EM638325TS Begin Auto Precharge Bank A RBy RBy CBy By0 By1 By2 Read with Auto Precharge Command Bank B Don’t Care Rev 2 ...

Page 43

... Begin Auto Precharge Bank B CBx CAy t DAL Write with Write with Auto Precharge Auto Precharge Command Command Bank B Bank A 43 EM638325TS Begin Auto Precharge Bank A RBy RBy CBy DBy0 DBy1 DBy2 DBy3 Activate Write with Command Auto Precharge Bank B Command Bank B Don’ ...

Page 44

... Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 44 EM638325TS RBy RBy t RP Bx+3 Bx+4 Bx+5 Bx+6 Precharge ...

Page 45

... Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 45 EM638325TS RBy RBy t RP Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Precharge ...

Page 46

... Command Bank B Burst Stop Command Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address 46 EM638325TS RBy RBy Data is ignored Precharge Activate Command Command Bank B Bank B Don’t Care Rev 2 ...

Page 47

... CAy Ax1 Ax2 DAy2 DAy1 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write Upper Byte Lower Byte Command is masked is masked Bank A 47 EM638325TS CAz Az1 Az2 Az0 Az1 Az2 Az3 Read Lower Byte Lower Byte Command is masked is masked Bank A Don’t Care Rev 2 ...

Page 48

... Bu3 Au1 Au2 Au3 Activate Activate Command Command Bank B Bank A Read Read Bank A Bank B with Auto with Auto Precharge Precharge 48 EM638325TS Begin Auto Begin Auto Precharge Precharge Bank B Bank A RAv RBw RAv CAv RBw t RP Av2 Bv0 Bv1 Bv2 Bv3 Av0 ...

Page 49

... Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2 Read Read Read Command Command Command Bank B Bank B Bank A Read Command Bank A 49 EM638325TS T18 T19 T20 T21 T22 RBw CBz RBw t RP Precharge Read Command Bank B Command (Precharge Temination) Activate ...

Page 50

... DAz0 DAz1 DAz2 DBz0 DBz1 DBz2 DBy0 DBy1 Write Write Write Command Command Command Bank B Bank A Bank B Write Command Bank A 50 EM638325TS RBw RBw CBz Precharge Command Bank B (Precharge Temination) Activate Write Data Command are masked Bank B Don’t Care Rev 2 ...

Page 51

... T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAy RAy CAy Activate Precharge Read Command Command Command Bank A Bank A Bank A 51 EM638325TS RAz RAz t RP Ay0 Ay1 Ay2 Precharge Activate Command Command Bank A Bank A Precharge Termination of a Read Burst Don’t Care Rev 2.0 June 2009 ...

Page 52

... Dimension in mm Max Min - 0.047 - 0.008 0.05 0.043 0.9 0.011 0.17 - - 0.88 22.09 0.405 10.03 - - 0.471 11.56 0.024 0.40 - - - - 0.004 - - - 8° 0 ° 52 EM638325TS θ° Normal Max - 1.20 0.10 0.2 1 1.1 0.22 0.27 0.127 - 22.22 22.35 10.16 10.29 0.50 - 11.76 11.96 0.50 0.60 0.80 - 0.61 - 0.10 - - ...

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