HM5225805BTT-A6 Elpida Memory, Inc., HM5225805BTT-A6 Datasheet
HM5225805BTT-A6
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HM5225805BTT-A6 Summary of contents
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... Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence Sequential (BL = 1/2/4/8) Interleave (BL = 1/2/4/8) Programmable CAS latency: 2/3 Elpida Memory, Inc joint venture DRAM company of NEC Corporation and Hitachi, Ltd. 133 MHz/100 MHz 4-bit 4-bank PC/133, PC/100 SDRAM 8-bit 4 bank. The HM5225405B is a 256-Mbit 4-bit 4 bank ...
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... MHz HM5225165BTT-A6 100 MHz 2 HM5225165BTT-B6* 100 MHz 1 HM5225165BLTT-75* 133 MHz HM5225165BLTT-A6 100 MHz 2 HM5225165BLTT-B6* 100 MHz 1 HM5225805BTT-75* 133 MHz HM5225805BTT-A6 100 MHz 2 HM5225805BTT-B6* 100 MHz 1 HM5225805BLTT-75* 133 MHz HM5225805BLTT-A6 100 MHz 2 HM5225805BLTT-B6* 100 MHz 1 HM5225405BTT-75* 133 MHz HM5225405BTT-A6 100 MHz ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Pin Arrangement (HM5225165B) Pin Description Pin name Function A0 to A12, Address input BA0, BA1 Row address Column address Bank select address DQ0 to DQ15 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Pin Arrangement (HM5225805B) Pin Description Pin name Function A0 to A12, Address input BA0, BA1 Row address Column address Bank select address DQ0 to DQ7 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Pin Arrangement (HM5225405B) Pin Description Pin name Function A0 to A12, Address input BA0, BA1 Row address Column address Bank select address DQ0 to DQ3 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Block Diagram (HM5225165B Column address counter Row decoder Memory array Bank 0 8192 row X 512 column X 16 bit Data Sheet E0082H10 A12, BA0, BA1 Column address Row address buffer buffer Row ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Block Diagram (HM5225805B Column address counter Row decoder Memory array Bank 0 8192 row X 1024 column X 8 bit A0 to A12, BA0, BA1 Column address Row address buffer buffer Row decoder Row decoder Memory ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Block Diagram (HM5225405B A9, A11 Column address counter Row decoder Memory array Bank 0 8192 row X 2048 column X 4 bit Data Sheet E0082H10 A12, BA0, BA1 Column address Row address buffer buffer ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 V and V Q (power supply pins): Ground is connected output buffer.) Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Command Ignore command ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8; HM5225165B, AY0 to AY9; HM5225805B, AY0 to AY9, AY11; HM5225405B) and the bank ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 DQM Truth Table (HM5225165B) Command Upper byte (DQ8 to DQ15) write enable/output enable ENBU Lower byte (DQ0 to DQ7) write enable/output enable Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU Lower byte (DQ0 to DQ7) write inhibit/output disable ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 CKE Truth Table Current state Command Active Clock suspend mode entry Any Clock suspend Clock suspend Clock suspend mode exit Idle Auto-refresh command (REF) Idle Self-refresh entry (SELF) Idle Power down entry Self refresh Self refresh exit (SELFX) Power ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self- refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self- refresh is performed internally and automatically, external ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 CS RAS CAS WE Current state Row active Read ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 CS RAS CAS WE Current state Write Write with auto- H precharge ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 From PRECHARGE state, command operation To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after t elapsed from the completion of precharge. From IDLE state, command operation To [DESL], [NOP], [PRE] or [PALL]: These ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of t Attempting to make the ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Simplified State Diagram MODE REGISTER SET Write CKE_ WRITE SUSPEND CKE WRITE WITH AP CKE_ WRITEA SUSPEND CKE POWER POWER APPLIED ON Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set cycles. The mode register consists of five sections, each of which is assigned to ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequential Burst length = 8 Starting Ad. Addressing(decimal Sequential ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Operation of the SDRAM The following chapter shows operation example of the products below. Organization 4-Mword 16-bit 4 bank 8-Mword 8-bit 4 bank 16-Mword 4-bit 4 bank Note: The SDRAM should be used according to the product capability (See ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 CAS Latency CLK t RCD Command READ ACTV Address Row Column Dout Burst Length CLK t RCD Command ACTV READ Address Row Column out out 0 out 1 BL ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Auto Precharge Read with auto-precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM, DQMU/DQML must be set High so that the output buffer ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = CLK READ Command PRE/PALL Dout CAS Latency = 3, Burst Length = CLK ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than the case of different bank-active commands: The interval between the two bank-active commands must be no less ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than l CLK Command MRS Address CODE Mode Register Set Data Sheet E0082H10 38 . RSA ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 DQM Control The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Power up sequence CKE, DQM, Low DQMU/DQML Low CLK Low CS, DQ Power stabilize Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative to V ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/ Clamp IL IH This SDRAM has V and V clamp for CLK, CKE, CS, DQM and DQ pins Minimum V Clamp Current IL V (V) IL –2 –1.8 –1.6 –1.4 –1.2 –1 –0.9 –0.8 –0.6 ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Minimum V Clamp Current 0.6 ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/ Characteristics OL OH Output Low Current ( Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 0 Min (mA) 0 ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Output High Current ( +70˚ Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1 0.5 1 –100 –200 –300 –400 –500 –600 Data Sheet E0082H10 ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 DC Characteristics ( +70˚C, V (HM5225165B) Parameter Symbol Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power I CC2P down Standby current in power I CC2PS down ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 DC Characteristics ( +70˚C, V (HM5225805B) Parameter Symbol Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power I CC2P down Standby current in power I CC2PS down ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 DC Characteristics ( +70˚C, V (HM5225405B) Parameter Symbol Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power I CC2P down Standby current in power I CC2PS down ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Notes depends on output load condition when the device is selected output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 AC Characteristics ( + Parameter Symbol System clock cycle time (CAS latency = (CAS latency = CLK high pulse width t CKH CLK low pulse width t CKL ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Notes measurement assumes t 2. Access time is measured at 1.5 V. Load condition pF (min) defines the time at which the outputs achieves the low impedance state ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Relationship Between Frequency and Minimum Latency Parameter Frequency (MHz) t (ns) CK Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Parameter Frequency (MHz) t (ns command disable Power down exit to command input Notes are recommended value. RCD RRD 2. Be valid [DESL] or [NOP] at next command of self refresh exit. ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Timing Waveforms Read Cycle CKH CKL CLK V IH CKE t RCD RAS CAS t t ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Write Cycle CKH CKL CLK V IH CKE t RCD RAS CAS ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Mode Register Set Cycle CLK V CKE IH CS RAS CAS WE BS Address valid code DQM, DQMU/DQML DQ (output) DQ (input) l RSA l RP Precharge Mode If needed register Set Read Cycle/Write Cycle ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Read/Single Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE BS ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Read/Burst Write Cycle CLK CKE CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read V CKE IH CS RAS CAS WE BS R:a C:a ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Auto Refresh Cycle CLK CKE RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Auto Refresh Precharge If needed Self Refresh Cycle CLK CKE Low CKE ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Clock Suspend Mode t CES CLK CKE CS RAS CAS WE BS Address R:a DQM, DQMU/DQML DQ (output) DQ (input) Bank0 Active clock Active clock Active suspend start suspend end CKE CS RAS ...
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Power Down Mode CLK CKE CS RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Precharge command If needed Initialization Sequence CLK CKE RAS CAS WE Address valid ...
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... HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Package Dimensions HM5225165BTT/BLTT HM5225805BTT/BLTT HM5225405BTT/BLTT Series (TTP-54D) 22.22 22.72 Max 54 1 0.80 +0.10 *0.30 –0.05 0.13 M 0.28 0.05 0.91 Max 0.10 *Dimension including the plating thickness Base material dimension Data Sheet E0082H10 11.76 0.20 0 – 5 0.50 Hitachi Code JEDEC EIAJ Weight (reference value) Unit: mm 0.80 0.10 TTP-54D — — 0.53 g ...
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... HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...