A42MX36 Actel Corporation, A42MX36 Datasheet

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... See the Actel website (www.actel.com) for the latest version of this datasheet Diagnostic and Verification A42MX24 A42MX36 36,000 54,000 – – 2,560 954 1,230 912 1,184 – 6.1 ns 6.3 ns – – ...

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... A42MX16 – – A42MX24 – – A42MX36 – – Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array ii PQ ...

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... MX offerings. v6.0 40MX and 42MX FPGA Families A42MX24 A42MX36 – ...

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...

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Table of Contents 40MX and 42MX FPGA Families General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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FPGA Families Table of Contents 100-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... DSP. All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MIL- STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pin- compatible ...

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FPGA Families The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and decode (D-modules). Figure 1-2 combinatorial logic module. The S-module, shown in Figure 1-3, implements the same combinatorial logic function as the ...

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... The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5. The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports ...

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... Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock networks. The A42MX36 device has four additional register control resources, called quadrant clock networks page 1-5). Each quadrant clock provides a local, high- fanout resource to the contiguous logic modules within its quadrant of the device ...

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... Figure 1-7 • Clock Networks of 42MX Devices QCLKA QCLKB *QCLK1IN *QCLK2IN Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals. Figure 1-8 • Quadrant Clock Network of A42MX36 Devices CLKB CLKINB CLKA CLKINA From S0 Pads Internal CLKMOD Signal S1 CLKO(17) Clock CLKO(16) Drivers CLKO(15) CLKO(2) ...

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... PCI specification. For low-power systems, all inputs and outputs are turned off to reduce current consumption to below 500µA. To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 1-10). When the PCI fuse is not programmed, the output drive is standard ...

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Figure 1-11 • Fuselock Programming Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor compact, robust, single-site and programmer for the PC. With standalone software, Silicon Sculptor II is designed ...

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FPGA Families Power Dissipation The general power consumption of MX devices is made up of static and dynamic power and can be expressed with the following equation: General Power Equation standby + I active] ...

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... A42MX09 118 A42MX16 165 A42MX24 185 A42MX36 220 Test Circuitry and Silicon Explorer II Probe MX devices contain probing circuitry that provides built- in access to every node in a design, via the use of Silicon Explorer II. Silicon Explorer integrated hardware and software solution that, in conjunction with the ...

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FPGA Families Serial Connection to Windows PC Figure 1-13 • Silicon Explorer II Setup with 42MX Table 2 • Device Configuration Options for Probe Capability Security Fuse(s) Programmed No No Yes Notes: 1. Avoid using SDI, SDO, ...

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Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which ...

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FPGA Families JTAG Mode Activation The JTAG test logic circuit is activated in the Designer software by selecting Tools -> Device Selection. This brings up the Device Selection dialog box as shown in Figure 1-15. The JTAG ...

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Development Tool Support The MX family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an ...

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FPGA Families 5.0V Operating Conditions Table 6 • Absolute Maximum Ratings for 40MX Devices* Symbol V DC Supply Voltage CC V Input Voltage I V Output Voltage O t Storage Temperature STG Note: *Stresses beyond those listed ...

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... I/O Capacitance IO Standby Current, A40MX02 A40MX04 CC A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode 42MX devices Standby Current only I , I/O source sink Can be derived from the IO current Notes: 1. Only one output tested at a time All outputs unloaded. All inputs = V Commercial Commercial -F Min ...

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FPGA Families 3.3V Operating Conditions Table 10 • Absolute Maximum Ratings for 40MX Devices* Symbol Parameter V DC Supply Voltage CC V Input Voltage I V Output Voltage O t Storage Temperature STG Note: *Stresses beyond those ...

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... T and I/O Capacitance IO 2 Standby Current, I A40MX02, CC A40MX04 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode 42MX Standby Current devices only I , I/O source sink Can be derived from the IO current Notes: 1. Only one output tested at a time All outputs unloaded. All inputs = V Commercial Commercial -F Min ...

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... Input Transition Time, T and I/O Capacitance IO 2 Standby Current, I A42MX09 CC A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current I I/O source sink current Can be derived from the IO Notes: 1. Only one output tested at a time. V CCI 2. All outputs unloaded. All inputs = Parameter – ...

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Output Drive Characteristics for 5.0V PCI Signaling MX PCI device I/O drivers were designed specifically for high-performance PCI systems. the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus Specification. Table ...

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FPGA Families Output Drive Characteristics for 3.3V PCI Signaling Table 19 • DC Specification (3.3V PCI Signaling) Symbol Parameter V Supply Voltage for I/Os CCI V Input High Voltage IH V Input Low Voltage IL I Input ...

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MX PCI I 0.15 0.10 0.05 0. –0.05 PCI I Maximum OH –0.10 –0.15 –0.20 Figure 1-16 • Typical Output Drive Characteristics (Based Upon Measured Data) PCI I Maximum OL OL ...

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FPGA Families Junction Temperature (T The temperature variable in the Designer software refers to the junction temperature, temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient ...

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Timing Models Input Delay I/O Module t INYL=0. Array Clock t CKH=4. MAX=180 MHz Note: * Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions. Figure 1-17 • 40MX Timing Model* Input ...

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... INH=0 INSU=0 INGL=1.3 ns Array Clocks t CKH=2. MAX=296 MHz Notes: * Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions. ** Load-dependent Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks) Input Delays I/O Module t INPY=1.0ns INSU=0.5ns t INH=0 ...

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Parameter Measurement In 50% 50 PAD 1. DLH t DHL Figure 1-21 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the output under test Figure 1-22 • AC Test Loads PAD ...

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FPGA Families Sequential Module Timing Characteristics D* G, CLK E Q PRE, CLR Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-25 • Flip-Flops and Latches PRE ...

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Sequential Timing Characteristics CLK Figure 1-26 • Input Buffer Latches D G Figure 1-27 • Output Buffer Latches PAD DATA IBDL G PAD DATA G t INSU CLK t SU EXT D PAD OBDLHS G t OUTSU t OUTH v6.0 ...

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FPGA Families Decode Module Timing A– Figure 1-28 • Decode Module Timing SRAM Timing Characteristics Figure 1-29 • SRAM Timing Characteristics Dual-Port SRAM Timing Waveforms WD[7:0] WRAD[5:0] Note: ...

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RCLK REN RDAD[5:0] RD[7:0] Note: Identical timing for falling edge clock. Figure 1-31 • 42MX SRAM Synchronous Read Operation RDAD[5:0] RD[7:0] Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled) WEN WD[7:0] WRAD[5:0] BLKEN WCLK RD[7:0] Figure ...

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FPGA Families Predictable Performance: Tight Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the ...

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Temperature and Voltage Derating Factors Table 22 • 42MX Temperature and Voltage Derating Factors (Normalized 25° 42MX Voltage –55°C 4.50 0.93 4.75 0.88 5.00 0.85 5.25 0.84 5.50 0.83 1.50 1.40 1.30 1.20 1.10 1.00 ...

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FPGA Families Table 23 • 40MX Temperature and Voltage Derating Factors (Normalized 25° 40MX Voltage –55°C 4.50 0.89 4.75 0.84 5.00 0.82 5.25 0.80 5.50 0.79 1.50 1.40 1.30 1.20 1.10 1.00 ...

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Table 24 • 42MX Temperature and Voltage Derating Factors (Normalized 25° 42MX Voltage –55°C 3.00 0.97 3.30 0.84 3.60 0.81 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 3.00 Note: ...

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FPGA Families Table 25 • 40MX Temperature and Voltage Derating Factors (Normalized 25° 40MX Voltage –55°C 3.00 1.08 3.30 0.86 3.60 0.83 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 3.00 ...

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... PCI A42MX24 Min. Max. Min. Max 2.0 9 2.0 9.0 2 – 2.0 4.0 1 – 28 – 8.3 7 – 1.5 – 2 10, 12 – 1.5 – 0 – 0 – v6.0 A42MX36 Min. Max. Units 4.0 – ns 1.9 – ns 1.9 – ns A42MX36 Min. Max. Units 2.0 9.0 ns 2.0 9.0 ns 2.0 4 – 8.3 ns 1.5 – ns 1.5 – – ns 1-35 ...

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FPGA Families Timing Characteristics Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch ...

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Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...

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FPGA Families Table 28 • A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 4 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to ENZH ...

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Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS ...

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FPGA Families Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay ...

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Table 29 • A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 4 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...

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FPGA Families Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to-Q GO ...

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Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...

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FPGA Families Table 30 • A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 1 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...

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Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Dual-Module Macros PD2 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS ...

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FPGA Families Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay ...

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Table 31 • A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 4 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...

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FPGA Families Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q ...

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Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH LOW INGL ...

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FPGA Families Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...

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Table 32 • A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...

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FPGA Families Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q ...

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Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH LOW INGL ...

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FPGA Families Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to ENZH ...

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Table 33 • A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...

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FPGA Families Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q ...

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Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH LOW INGL ...

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FPGA Families Table 34 • A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...

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Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module Predicted Routing ...

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FPGA Families Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL HIGH INGH t ...

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Table 35 • A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...

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FPGA Families Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing ...

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Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...

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FPGA Families Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ...

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Table 36 • A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 CMOS Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable Pad Z to HIGH ENZH t Enable Pad Z ...

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FPGA Families Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing ...

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Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay ...

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FPGA Families Table 37 • A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing (Continued) t I/O Latch Output Hold LH t I/O Latch Clock-to-Out LCO (Pad-to-Pad) 32 ...

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... Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing Delays t FO=1 Routing Delay RD1 t FO=2 Routing Delay RD2 t FO=3 Routing Delay RD3 t FO=4 Routing Delay ...

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... FPGA Families Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Synchronous SRAM Operations (Continued) t Address/Data Hold Time ADH t Read Enable Set-Up RENSU t Read Enable Hold RENH t Write Enable Set-Up WENSU t Write Enable Hold WENH ...

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... Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay IRD4 t FO=8 Routing Delay IRD8 Global Clock Network t Input LOW to HIGH FO=32 CKH FO=635 t Input HIGH to LOW ...

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... FPGA Families Table 38 • A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing (Continued) t Enable Pad LOW to Z ENLZ t G-to-Pad HIGH GLH t G-to-Pad LOW GHL t I/O Latch Output Set-Up LSU t I/O Latch Output Hold LH t I/O Latch Clock-to-Out (Pad-to- ...

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... Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V Parameter Description Logic Module Combinatorial Functions t Internal Array Module Delay PD t Internal Decode Module Delay PDD Logic Module Predicted Routing Delays t FO=1 Routing Delay RD1 t FO=2 Routing Delay RD2 t FO=3 Routing Delay RD3 t FO=4 Routing Delay ...

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... FPGA Families Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Synchronous SRAM Operations (Continued) t Address/Data Hold Time ADH t Read Enable Set-Up RENSU t Read Enable Hold RENH t Write Enable Set-Up WENSU t Write Enable Hold ...

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... Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description Input Module Predicted Routing Delays t FO=1 Routing Delay IRD1 t FO=2 Routing Delay IRD2 t FO=3 Routing Delay IRD3 t FO=4 Routing Delay IRD4 t FO=8 Routing Delay IRD8 Global Clock Network t Input LOW to HIGH FO=32 CKH FO=635 ...

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... FPGA Families Table 39 • A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, V Parameter Description 5 TTL Output Module Timing t Enable Pad LOW to Z ENLZ t G-to-Pad HIGH GLH t G-to-Pad LOW GHL t I/O Latch Output Set-Up LSU t I/O Latch Output Hold LH t I/O Latch Clock-to-Out (Pad-to- ...

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... Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. TDI, I/O Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin functions as an I/O when " ...

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... TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG specification recommends a 10kΩ pull-up resistor on the pin. BST pins are only available in A42MX24 and A42MX36 devices Supply Voltage CC ...

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Package Pin Assignments 44-Pin PLCC Figure 2-1 • 44-Pin PLCC 44-pin PLCC Pin Number A40MX02 Function A40MX04 Function 1 I I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 GND 11 ...

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FPGA Families 68-Pin PLCC Figure 2-2 • 68-Pin PLCC 44-pin PLCC Pin A40MX02 A40MX04 Number Function Function 1 I/O I/O 2 I/O I/O 3 I/O I I/O I/O 6 I/O I/O ...

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PLCC Figure 2-3 • 84-Pin PLCC 40MX and 42MX FPGA Families 1 84 84-Pin PLCC v6.0 2-3 ...

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FPGA Families 84-Pin PLCC Pin A40MX04 A42MX09 Number Function Function 1 I/O I/O 2 I/O CLKB, I/O 3 I/O I PRB, I I/O I/O 6 I/O GND 7 I/O I/O 8 I/O I/O ...

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PLCC Pin A40MX04 A42MX09 A42MX16 Number Function Function Function 71 I/O I/O 72 SDI, I/O I/O 73 DCLK, I/O I/O 74 PRA, I/O I/O 75 PRB, I/O I/O 76 I/O SDI, I/O SDI, I/O 77 I/O I/O A42MX24 Pin ...

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FPGA Families 100-Pin PQFP Package 100 1 Figure 2-4 • 100-Pin PQFP Package (Top View 100-Pin PQFP v6.0 ...

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PQFP Pin A40MX02 A40MX04 A42MX09 Number Function Function Function DCLK, I PRB, I/O PRB, I/O 7 I/O I/O 8 I/O I/O 9 I/O ...

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FPGA Families 100-Pin PQFP Pin A40MX02 A40MX04 Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I ...

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PQFP Package 160 1 Figure 2-5 • 160-Pin PQFP Package (Top View) 40MX and 42MX FPGA Families 160-Pin PQFP v6.0 2-9 ...

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FPGA Families 160-Pin PQFP A42MX09 A42MX16 Pin Number Function Function 1 I/O I/O 2 DCLK, I/O DCLK, I I/O 4 I/O I/O 5 I/O I I/O I/O 8 I/O I/O 9 ...

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PQFP A42MX09 A42MX16 Pin Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I I/O 76 I/O I I/O 78 I/O I I/O 80 GND GND 81 I/O ...

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FPGA Families 160-Pin PQFP A42MX09 A42MX16 Pin Number Function Function 141 NC I/O 142 I/O I/O 143 I/O I/O 144 I/O I/O 145 GND GND 146 NC I/O 147 I/O I/O 148 I/O I/O 149 I/O I/O ...

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PQFP Package 208 1 Figure 2-6 • 208-Pin PQFP Package (Top View) 208-Pin PQFP v6.0 40MX and 42MX FPGA Families 2-13 ...

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... I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I CCA I/O 53 I/O 54 I/O 55 I/O 56 GND 57 I/O 58 I/O 59 I/O 60 I/O 61 GND CCI CCI V 64 CCA I CCA I/O 68 I/O 69 I/O 70 v6.0 208-Pin PQFP A42MX16 A42MX24 A42MX36 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O NC I/O I/O GND GND GND GND GND GND I/O TMS, I/O TMS, I/O I/O TDI, I/O TDI, I/O ...

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... WD, I/O 120 WD, I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 QCLKB, I/O 126 I/O 127 WD, I/O 128 WD, I/O 129 I/O 130 I/O 131 I/O 132 V 133 CCI I/O 134 WD, I/O 135 WD, I/O 136 I/O 137 138 I/O 139 GND 140 v6.0 40MX and 42MX FPGA Families 208-Pin PQFP A42MX24 A42MX36 Function Function CCA CCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

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... WD, I/O 195 WD, I/O 196 I/O 197 V 198 CCI CCI I/O 199 I/O 200 I/O 201 WD, I/O 202 WD, I/O 203 I/O 204 QCLKD, I/O 205 I/O 206 I/O 207 I/O 208 v6.0 208-Pin PQFP A42MX16 A42MX24 A42MX36 Function Function Function I/O I/O I/O I/O WD, I/O WD, I/O I/O WD, I/O WD, I/O PRA, I/O PRA, I/O PRA, I/O I/O I/O I/O CLKA, I/O CLKA, I/O CLKA, I/O NC I/O I CCI CCI CCA CCA ...

Page 101

PQFP Package 240 1 • • • Figure 2-7 • 240-Pin PQFP Package (Top View) 40MX and 42MX FPGA Families 240-Pin PQFP v6.0 • • • 2-17 ...

Page 102

... I CCA 60 GND 95 61 GND I/O 100 66 I/O 101 67 I/O 102 68 I/O 103 69 I/O 104 70 I/O 105 v6.0 240-Pin PQFP A42MX36 Pin A42MX36 Function Number Function V 106 I/O CCI I/O 107 I/O I/O 108 V CCI I/O 109 I/O I/O 110 I/O I/O 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O 116 I/O I/O 117 I/O I/O 118 V CCA ...

Page 103

... I/O 202 168 I/O 203 169 I/O 204 170 I/O 205 171 I/O 206 172 V 207 CCI 173 I/O 208 174 WD, I/O 209 175 WD, I/O 210 240-Pin PQFP A42MX36 Pin A42MX36 Function Number Function I/O 211 I/O I/O 212 I/O TDI, I/O 213 I/O TMS, I/O 214 I/O GND 215 I/O V 216 I/O CCA GND 217 I/O I/O 218 I/O I/O 219 ...

Page 104

FPGA Families 80-Pin VQFP Figure 2-8 • 80-Pin VQFP 80-Pin VQFP v6.0 ...

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VQFP Pin A40MX02 A40MX04 Number Function Function 1 I I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 I/O ...

Page 106

FPGA Families 100-Pin VQFP Package 100 1 Figure 2-9 • 100-Pin VQFP Package (Top View 100-Pin VQFP v6.0 ...

Page 107

VQFP Package Pin A42MX09 A42MX16 Number Function Function 1 I/O I/O 2 MODE MODE 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 ...

Page 108

FPGA Families 176-Pin TQFP Package 176 1 Figure 2-10 • 176-Pin TQFP Package (Top View 176-Pin TQFP v6.0 ...

Page 109

TQFP A42MX09 A42MX16 Pin Number Function Function 1 GND GND 2 MODE MODE 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I I ...

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FPGA Families 176-Pin TQFP A42MX09 A42MX16 Pin Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I I/O 75 I/O I/O 76 I/O I I/O 79 I/O I/O ...

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TQFP A42MX09 A42MX16 Pin Number Function Function 141 I/O I/O 142 I/O I/O 143 NC I/O 144 NC I/O 145 NC NC 146 I/O I/O 147 NC I/O 148 I/O I/O 149 I/O I/O 150 I/O I/O 151 NC ...

Page 112

... Figure 2-11 • 208-Pin CQFP (Top View 164163162161160159158157 A42MX36 208-Pin CQFP 100101102103104 v6.0 156 155 154 153 152 151 150 149 113 112 111 110 109 108 107 106 ...

Page 113

... I/O I/O 97 I/O I CCI I/O 99 I/O QCLKA, I/O 100 WD, I/O WD, I/O 101 WD, I/O WD, I/O 102 I/O I/O 103 TDO, I/O I/O 104 I/O WD, I/O 105 GND v6.0 40MX and 42MX FPGA Families 208-Pin CQFP Pin A42MX36 Number Function 106 V CCA 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O ...

Page 114

... I/O 183 167 I/O 184 168 WD, I/O 185 169 WD, I/O 186 170 I/O 187 171 QCLKD, I/O 188 172 I/O 189 173 I/O 190 174 I/O 191 v6.0 208-Pin CQFP A42MX36 Pin A42MX36 Function Number Function I/O 192 I/O WD, I/O 193 I/O WD, I/O 194 WD, I/O PRA, I/O 195 WD, I/O I/O 196 QCLKC, I/O CLKA, I/O 197 I/O I/O 198 I/O V 199 I/O CCI V 200 I/O ...

Page 115

... Figure 2-12 • 256-Pin CQFP (Top View) 40MX and 42MX FPGA Families 200199198197196195194193 A42MX36 256-Pin CQFP 121122123124125126127128 v6.0 192 191 190 189 188 187 186 185 137 136 135 134 133 132 ...

Page 116

... GND 96 62 GND 100 66 I/O 101 67 SDO, TDO, I/O 102 68 I/O 103 69 WD, I/O 104 70 WD, I/O 105 v6.0 256-Pin CQFP A42MX36 Pin A42MX36 Function Number Function I/O 106 WD, I/O V 107 I/O CCI I/O 108 I/O I/O 109 WD, I/O I/O 110 WD, I/O WD, I/O 111 I/O GND 112 QCLKA, I/O WD, I/O 113 I/O I/O 114 GND QCLKB, I/O ...

Page 117

... I/O V 236 I/O CCI I/O 237 I/O I/O 238 I/O I/O 239 I/O I/O 240 QCLKD, I/O GND 241 I/O I/O 242 WD, I/O I/O 243 GND QCLKC, I/O 244 WD, I/O I/O 245 I/O v6.0 40MX and 42MX FPGA Families 256-Pin CQFP Pin A42MX36 Number Function 246 I/O 247 I/O 248 V CCI 249 I/O 250 WD, I/O 251 WD, I/O 252 I/O 253 SDI, I/O 254 I/O 255 GND 256 NC 2-33 ...

Page 118

FPGA Families 272-Pin BGA Package Figure 2-13 • 272-Pin BGA Package (Top View ...

Page 119

... G1 I/O I/O G2 I/O I CCI CCI I/O G17 V CCI I/O G18 I/O V G19 I/O CCA WD, I/O G20 I I/O CCI v6.0 40MX and 42MX FPGA Families 272-Pin PBGA Pin A42MX36 Number Function H2 I CCA H17 I/O H18 I/O H19 I/O H20 I/O J1 I/O J2 I CCI J9 GND J10 GND J11 GND J12 GND ...

Page 120

... WD, I/O W4 U10 V CCA W5 U11 V CCI W6 U12 I/O W7 U13 I/O W8 U14 QCLKB, I/O W9 U15 I/O W10 U16 V CCI W11 U17 I/O W12 U18 GND v6.0 272-Pin PBGA A42MX36 Pin A42MX36 Function Number Function I/O W13 WD, I/O I/O W14 I/O I/O W15 I/O I/O W16 WD, I/O GND W17 I/O GND W18 WD, I/O I/O W19 GND I/O W20 GND I/O Y1 GND WD, I/O Y2 GND I/O ...

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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version ( v5.1 The "Ease of Integration" section The "Temperature Grade ...

Page 122

FPGA Families 40MX and 42MX Previous version Changes in current version ( 5.1 In the 160-Pin PQFP Pin 61 (42MX09, 42MX16, and 42MX64) has changed the 208-Pin PQFP Pin 129 (42MX09, 42MX16, and 42MX64) ...

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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0)1276 ...