MT4LC4M16F5TG-6 Micron Semiconductor Products, MT4LC4M16F5TG-6 Datasheet

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MT4LC4M16F5TG-6

Manufacturer Part Number
MT4LC4M16F5TG-6
Description
4 MEG x 16 FPM DRAM
Manufacturer
Micron Semiconductor Products
Datasheet
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
• 12 row, 10 column addresses
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
OPTIONS
• Plastic Package
• Timing
• Refresh Rate
KEY TIMING PARAMETERS
GENERAL DESCRIPTION
dynamic random-access memory device containing
67,108,864 bits organized in a x16 configuration. The
MT4LC4M16F5 is functionally organized as 4,194,304
locations containing 16 bits each. The 4,194,304
memory locations are arranged in 4,096 rows by 1,024
columns. During READ or WRITE cycles, each location
is uniquely addressed via the address bits: 12 row-
address bits (A0-A11) and 10 column-address bits (A0-
A9). In addition, both byte and word accesses are
supported via the two CAS# pins (CASL# and CASH#).
The CAS# functionality and timing related to address
and control functions (e.g., latching column addresses
or selecting CBR REFRESH) are such that the internal
4 Meg x 16 FPM DRAM
D28_2.p65 – Rev. 5/00
SPEED
and packages
distributed across 64ms
50-pin TSOP (400 mil)
50ns access
60ns access
Standard Refresh
The 4 Meg x 16 DRAM is a high-speed CMOS,
-5
-6
110ns
90ns
t
RC
MT4LC4M16F5TG-5
Part Number Example
t
50ns
60ns
RAC
30ns
35ns
t
PC
25ns
30ns
t
MARKING
AA
None
TG
-5
-6
t
13ns
15ns
CAC
1
MT4LC4M16F5
For the latest data sheet, please refer to the Micron
Web site: www.micron.com/mti/msp/html/
datasheet.html
CAS# signal is determined by the first external CAS#
signal (CASL# or CASH#) to transition LOW and the last
to transition back HIGH. The CAS# functionality and
timing related to driving or latching data are such that
each CAS# signal independently controls the associ-
ated eight DQ pins.
the column address by CAS#. The device provides FAST-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
cally in order to retain stored data.
NOTE: 1. The # symbol indicates signal is active LOW.
The row address is latched by the RAS# signal, then
RAS#
WE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
V
V
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
The MT4LC4M16F5 must be refreshed periodi-
NC
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
CC
CC
CC
CC
PIN ASSIGNMENT (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50-Pin TSOP
4 MEG x 16
FPM DRAM
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
©2000, Micron Technology, Inc.
V
DQ15
DQ14
DQ13
DQ12
V
DQ11
DQ10
DQ9
DQ8
NC
V
CASL#
CASH#
OE#
NC
NC
NC
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
SS

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MT4LC4M16F5TG-6 Summary of contents

Page 1

... CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms OPTIONS • Plastic Package 50-pin TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rate Standard Refresh Part Number Example MT4LC4M16F5TG-5 KEY TIMING PARAMETERS SPEED RC RAC PC -5 90ns 50ns ...

Page 2

FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Use of only one of the ...

Page 3

DRAM REFRESH The supply voltage must be maintained at the speci- fied levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the ...

Page 4

RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 WORD READ STORED OUTPUT OUTPUT STORED STORED DATA DATA DATA DATA DATA ...

Page 5

ABSOLUTE MAXIMUM RATINGS* Voltage on V Relative to V ................ -1V to +4. Voltage on NC, Inputs or I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (ambient) ... 0°C to +70°C A Storage ...

Page 6

CAPACITANCE (Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12, 13 CHARACTERISTICS PARAMETER Access time from column address Column-address ...

Page 7

AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12, 13 CHARACTERISTICS PARAMETER RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold ...

Page 8

NOTES 1. All voltages referenced This parameter is sampled. V MHz dependent on output loading and cycle DD rates. Specified values are obtained with mini- mum cycle time and the outputs open. 4. ...

Page 9

NOTES (continued) 30. Last rising CASx# edge to next cycle’s last rising CASx# edge. 31. Last rising CASx# edge to first falling CASx# edge. 32. First DQs controlled by the first CASx LOW. 33. Last DQs controlled by ...

Page 10

V IH RAS CRP V IH CAS ASR V IH ROW ADDR WE IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX MIN ...

Page 11

V IH RAS CRP V IH CAS ASR V IH ADDR ROW WE IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 12

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR V ROW WE IOH DQ V IOL ...

Page 13

V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW WE IOH DQ OPEN V IOL V IH OE# ...

Page 14

FAST-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW IL t WCS ...

Page 15

FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WE ...

Page 16

FAST-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP V IH CAS ASR V IH ADDR V ROW WE TIMING PARAMETERS -5 SYMBOL MIN ...

Page 17

V IH RAS CRP V IH CAS ASR V IH ADDR RAS RPC CSR V IH CAS# ...

Page 18

V IH RAS CRP V IH CASL#/CASH ASR t RAH V IH ADDR ROW IOH DQx V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX t AA ...

Page 19

TYP PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal ...

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