MT55L256L32FF-10 Micron Semiconductor Products, MT55L256L32FF-10 Datasheet

MT55L256L32FF-10

Manufacturer Part Number

MT55L256L32FF-10

Description

8Mb: 256K x 32 FLOW-THROUGH ZBT SRAM

Manufacturer

Micron Semiconductor Products

Datasheet

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8Mb

ZBT

FEATURES

• High frequency and 100 percent bus utilization

• Fast cycle times: 10ns, 11ns and 12ns

• Single +3.3V ±5% power supply (V

• Separate +3.3V or +2.5V isolated output buffer

• Advanced control logic for minimum control

• Individual BYTE WRITE controls may be tied LOW

• Single R/W# (read/write) control pin

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

• Internally self-timed, fully coherent WRITE

• Internally self-timed, registered outputs to

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature (optional)

• Pin/function compatibility with 2Mb, 4Mb, and

• 100-pin TQFP

• 165-pin FBGA

• Automatic power-down

OPTIONS

• Timing (Access/Cycle/MHz)

• Configurations

• Package

• Operating Temperature Range

8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM

MT55L512L18F_C.p65 – Rev. 2/02

supply (V

signal interface

I/Os and control signals

eliminate the need to control OE#

18Mb ZBT SRAM

7.5ns/10ns/100 MHz

8.5ns/11ns/90 MHz

9ns/12ns/83 MHz

3.3V I/O

2.5V I/O

100-pin TQFP

165-pin FBGA

Commercial (0ºC to +70ºC)

Industrial (-40°C to +85°C)**

512K x 18

256K x 32

256K x 36

512K x 18

256K x 32

256K x 36

SRAM

MT55L256L32FT-11

Part Number Example:

MT55L512V18F

MT55L256V32F

MT55L256V36F

MT55L512L18F

MT55L256L32F

MT55L256L36F

MARKING

)

None

-10

-11

-12

MT55L512L18F, MT55L512V18F,

MT55L256L32F, MT55L256V32F,

MT55L256L36F, MT55L256V36F

3.3V V

* A Part Marking Guide for the FBGA devices can be found on Micron’s

** Industrial temperature range offered in specific speed grades and

GENERAL DESCRIPTION

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

256K x 32, or 256K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. These SRAMs are optimized for 100 percent

bus utilization, eliminating any turnaround cycles for

READ to WRITE, or WRITE to READ, transitions. All

synchronous inputs pass through registers controlled

by a positive-edge-triggered single clock input (CLK).

The synchronous inputs include all addresses, all data

inputs, chip enable (CE#), two additional chip enables

for easy depth expansion (CE2, CE2#), cycle start input

NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).

Web

configurations. Contact factory for more information.

The Micron

Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,

site—http://www.micron.com/support/index.html.

8Mb: 512K x 18, 256K x 32/36

FLOW-THROUGH ZBT SRAM

, 3.3V or 2.5V I/O

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Zero Bus Turnaround

100-Pin TQFP

165-Pin FBGA

™

(ZBT

) SRAM

Related parts for MT55L256L32FF-10

MT55L256L32FF-10 Summary of contents

Page 1

ZBT SRAM FEATURES • High frequency and 100 percent bus utilization • Fast cycle times: 10ns, 11ns and 12ns • Single +3.3V ±5% power supply (V • Separate +3.3V or +2.5V isolated output buffer supply ( ...

Page 2

SA0, SA1, SA MODE CE CLK K CKE# ADV/LD# BWa# BWb# R/W# OE# CE# CE2 CE2# 18 SA0, SA1, SA MODE CE CLK K CKE# ADV/LD# BWa# BWb# BWc# BWd# R/W# OE# CE# CE2 CE2# NOTE: Functional block diagrams ...

Page 3

GENERAL DESCRIPTION (continued) (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc#, and BWd#), and read/write (R/W#). Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal mini- mization), clock (CLK), and snooze ...

Page 4

TQFP PIN ASSIGNMENT TABLE PIN # x18 x32 x36 PIN # DQPc DQc DQc DQc DQc DQc DQc 31 ...

Page 5

ADV/LD# 85 OE# (G#) 86 CKE# 87 R/W# 88 CLK CE2# 92 BWa# 93 BWb CE2 97 CE# 98 ...

Page 6

TQFP PIN DESCRIPTIONS x18 x32/x36 32-35, 44-50, 32-35, 44-50, 80-83, 99, 81-83, 99, 100 100 – 95 – ...

Page 7

TQFP PIN DESCRIPTIONS (CONTINUED) x18 x32/x36 (a) 58, 59, 62, 63, (a) 52, 53, 56-59, 68, 69, 72-74 62 12, 13, (b) 68, 69, 72-75, 18, 19, 22-24 78, 79 (c) 2, ...

Page 8

CE# BWb# NC CE2# CKE CE2 NC BWa# CLK R/ ...

Page 9

FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 9A, 2B, 2A, 9A, 2B, 3P, 3R, 4P, 4R, 3P, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11R ...

Page 10

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 8A 8A ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, ...

Page 11

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 1H, 4C, 4N, 1H, 4C, 4N, 5C, 5D, 5E, 5F, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, ...

Page 12

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR ...

Page 13

DS BEGIN READ READ READ BURST BURST READ KEY: COMMAND DS READ WRITE BURST NOTE STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) ...

Page 14

TRUTH TABLE (Notes 5-10) OPERATION DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT ...

Page 15

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V .................................. -0.5V to +4.6V SS Voltage Supply DD Relative to V ..................................... -0. ............................................... -0. Storage Temperature (TQFP) ............ ...

Page 16

I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0° +70° +3.3V ±0.165V DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage ...

Page 17

I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note 1) (0° +70° +3.3V ±0.165V unless otherwise noted DESCRIPTION Power Supply Device selected; All inputs V Current: Operating Cycle time IH V ...

Page 18

FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient Test conditions follow standard test methods (Airflow of 1m/s) Junction to Case (Top) Junction to Pins (Bottom) AC ELECTRICAL CHARACTERISTICS (Notes (0° +70° DESCRIPTION Clock ...

Page 19

I/O AC TEST CONDITIONS Input pulse levels ................................... V Input rise and fall times ..................................... 1ns Input timing reference levels .......................... 1.5V Output reference levels ................................... 1.5V Output load ............................. See Figures 1 and 2 3.3V I/O Output Load ...

Page 20

SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time the ZZ pin ...

Page 21

CLK t EVKH t KHEX t KHKL CKE# t CVKH t KHCX CE# ADV/LD# R/W# BWx ADDRESS t AVKH t KHAX DQ D(A1) t DVKH t KHDX OE# COMMAND WRITE WRITE D(A1) D(A2) READ/WRITE TIMING PARAMETERS ...

Page 22

CLK CKE# CE# ADV/LD# R/W# BWx ADDRESS D(A1) DQ COMMAND WRITE READ D(A1) Q(A2) NOP, STALL, AND DESELECT TIMING PARAMETERS -10 -11 SYM MIN MAX MIN MAX t KHQX 3.0 3.0 t KHQZ 5.0 5.0 NOTE: ...

Page 23

PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT ...

Page 24

BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. ...

Page 25

REVISION HISTORY Removed "Preliminary Package Data" from front page ....................................................................... February 22/02 Removed 119-pin PBGA package and references ................................................................................. February 14/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................ June 7/01 Added industrial temperature references and notes, Rev. ...

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