MT58L128L36P1T-5 Micron Semiconductor Products, MT58L128L36P1T-5 Datasheet
MT58L128L36P1T-5
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MT58L128L36P1T-5 Summary of contents
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SYNCBURST SRAM FEATURES • Fast clock and OE# access times • Single +3.3V +0.3V/-0.165V power supply (V • Separate +3.3V or +2.5V isolated output buffer supply ( • SNOOZE MODE for reduced-power standby • Single-cycle deselect (Pentium ...
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ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 17 ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# ...
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GENERAL DESCRIPTION (continued) (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable ...
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TQFP PIN ASSIGNMENT TABLE PIN # x18 x32/x36 PIN # 1 NC NC/DQPc DQc DQc DQc DQc 32 8 ...
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ADV# 83 ADSP# 84 ADSC# 85 OE# 86 BWE# 87 GW# 88 CLK CE2# 92 BWa# 93 BWb CE2 97 CE ...
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TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 44-50, 32-35, 44-50, 80-82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd BWE GW# 89 ...
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TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 85 85 ADSC MODE 64 64 (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72 12, (b) 68, 69 13, 18, 19, ...
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CE# BWb# NC CE2# BWE CE2 NC BWa# CLK GW ...
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FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11R 10P, 10R, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 9B 9B ADSP ADSC MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, ...
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INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS ...
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TRUTH TABLE OPERATION ADDRESS DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst External READ Cycle, Begin Burst External WRITE Cycle, Begin Burst External READ Cycle, Begin ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V ............................... -0.5V to +4.6V SS Voltage Supply DD Relative to V ............................... -0.5V to +4. -0. 0. Storage ...
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TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance NOTE: 1. This parameter is sampled. 2. Preliminary package data. 4Mb: 256K x 18, 128K x ...
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I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C T +70° +3.3V +0.3V/-0.165V DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low ...
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TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient Test conditions follow standard test methods (Airflow of 1m/s) Junction to ...
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I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note 1) (0°C T +70° DESCRIPTION CONDITIONS Power Supply Device selected; All inputs Current Cycle time IH Operating V = MAX; Outputs open DD Power Supply Device ...
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C T +70° DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to ...
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I/O AC TEST CONDITIONS Input pulse levels ................. V .................... V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... V Output reference levels ............................ V Output load ............................. See Figures 1 and 2 3.3V I/O ...
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SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS GW#, BWE#, BWa#-BWd# t CES t CEH CE# ...
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READ TIMING PARAMETERS -4.4 SYMBOL MIN MAX 225 2.6 t KQX 1 t KQLZ 0 t KQHZ 2.6 t OEQ 2.6 t OELZ 0 t OEHZ 2.6 ...
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KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS A1 Byte write signals are ignored for first cycle when ADSP# ...
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WRITE TIMING PARAMETERS -4.4 SYMBOL MIN MAX 225 1.7 t OEHZ 2 ADSS 1 t AAS CES 1 ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS A1 A2 BWE#, BWa#-BWd# (NOTE 4) t CES t CEH CE# (NOTE 2) ...
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READ/WRITE TIMING PARAMETERS -4.4 SYMBOL MIN MAX 225 2.6 t KQLZ 0 t OELZ 0 t OEHZ 2 ADSS ...
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PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 4Mb: 256K x 18, ...
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BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. ...
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REVISION HISTORY Removed "Preliminary Package Data" from front page ....................................................................... February 22/02 Removed -4 speed grade Removed 119-pin PBGA package and references ................................................................................... February 2/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................ June 7/01 Added Industrial Temperature ...