PEB20570FV3.1 Infineon Technologies AG, PEB20570FV3.1 Datasheet
PEB20570FV3.1
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PEB20570FV3.1 Summary of contents
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... Edition 2001-03-19 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 3/19/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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PEB 20570 Preliminary Revision History: Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.2.3 Initialization of the VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.4.1.3 DSP Accessible Buffer (D-Buffer 106 4.4.1.4 PCMU Interface Data Rate ...
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Table of Contents 4.10.1.1 Two-cycle DMA Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.10.1.2 Fly-by Mode ...
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Table of Contents 6.2.3.1 PCMU Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.3.2 ...
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Table of Contents 6.2.9.5 DSP Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 9 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Block Diagram of the DELIC- ...
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List of Figures Figure 43 A/µ-law Unit Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary Figure 83 LNC0..3 (Local Network Controller) Interface Timing . . . . . . . . . . . . 274 Figure 84 LCLK0..3 Timing in Output Mode ...
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List of Tables Table 1 IOM®-2 Interface Pins (DELIC-LC Table 2 IOM-2000 ...
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List of Tables Table 42 Interrupt Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 82 LNC0..3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary Preface This document provides reference information on the DELIC-LC/-PB Version 3.1. Organization of this Document This Data Sheet is divided into 11 chapters and appendices organized as follows: • Chapter 1 Introduction Gives a general description of ...
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Preliminary 1 Introduction The DELIC and VIP chipset realizes multiple ISDN S/T and U controller functionality typically needed in PBX or Central Office systems. This functionality comprises voice channel handling, signaling control, layer-1 control, and even signal processing tasks. Moreover ...
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Preliminary Block diagrams: Figure 1 Block Diagram of the DELIC-LC Figure 2 Block Diagram of the DELIC-PB Data Sheet DELIC-LC Switch IOM-2 / 256 x 256 TS PCM Interface IOM-2000 24 HDLC Interface Controllers Clocks µP Mailbox µP Interface DELIC-PB ...
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Preliminary DSP Embedded Line and Port Interface Controller DELIC-LC DELIC-PB Version 3.1 1.1 DELIC-LC Key Features DELIC-LC is optimized for line card applications: • One IOM-2000 interface supporting three VIPs i. ISDN channels • Two IOM-2 (GCI) ...
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Preliminary List of maximum available features: • One IOM-2000 interface supporting up to three VIPs i. ISDN channels • Support of DASL mode • two IOM-2 (GCI) ports (also configurable as PCM ports) supporting up ...
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Preliminary 1.3 Logic Symbol 7 IOM-2 Interfaces 5 IOM-2000/ LNC Interface 9 Clock Signals Figure 3 Logic Symbol Data Sheet P-TQFP-100-3 Power Supply 27 DELIC-LC PEB20570 DELIC-PB PEB 20571 P-TQFP-100 JTAG µP Interface Interface Interface 6 PEB ...
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Preliminary 1.4 Typical Applications 1.4.1 Applications for DELIC-LC The following two figures show example configurations of DELIC-LC Line card applications for different ISDN interface standards. In Figure 4, three VIP transceiver ICs are connected to the DELIC-LC via the IOM-2000 ...
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Preliminary Figure 5 DELIC-LC/PB in Uk0 Line Card for 16 Subscribers Note: In this application DELIC-PB is also meaningful. 1.4.2 Applications for DELIC-PB HV-SLIC HV-SLIC HV-SLIC HV-SLIC 16 x t/r HV-SLIC HV-SLIC HV-SLIC HV-SLIC Figure 6 ...
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Preliminary HV-SLIC HV-SLIC 32 x t/r HV-SLIC HV-SLIC Central Office Figure 7 DELIC-PB in Small PBX 2.3 MBit Figure 8 DELIC- Port SDSL Line ...
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Preliminary 2 Pin Description 2.1 Pin Diagram DELIC-LC (top view RxD0/LRxD2 76 TSC0/ LRTS2 77 78 TXD0/LTxD2 79 TSC1/ LRTS3 80 TxD1/LTxD3 TSC2 81 82 TxD2/LCLK2 83 TSC3 TxD3/LCLK3 86 ...
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Preliminary 2.2 Pin Diagram DELIC-PB (top view RxD0/LRxD2 76 77 TSC0/ LTSC2/LRTS2 78 TXD0/LTxD2 79 TSC1/ LTSC3/LRTS3 80 TxD1/LTxD3 81 TSC2 82 TxD2/LCLK2 83 TSC3 TxD3/LCLK3 86 87 PFS PDC ...
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Preliminary 2.3 Pin Definitions and Functions for DELIC-LC Note: The column “During Reset” refers to the time period that starts with activation of RESET input and ends with the deactivation of the RESIND output. During this period, the DELIC strap ...
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Preliminary ® Table 1 IOM -2 Interface Pins (DELIC-LC) Pin Symbol In (I) No. Out(O) 39 FSC O 40 DCL O 43 DD0 O(OD) High Z 44 DD1 O(OD) High Z 41 DU0 I 42 DU1 I 45 DRDY I ...
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Preliminary Table 2 IOM-2000 Interface / LNC Port 1 (DELIC-LC) Pin Symbol In (I) No. Out (O) 70 DCL_2000 / O LRTS1 LTxD1 O (OD LRxD1 I 67 CMD / O ...
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Preliminary Table 3 LNC Port 0 (DELIC-LC) Pin Symbol In (I) No. Out (O) 62 LRxD0 I 61 LTxD0 O (OD) High Z 60 LTSC0 / O LRTS0 59 LCxD0 / I LCTS0 56 LCLK0 I/O . Data Sheet During ...
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Preliminary Table 4 Microprocessor Bus Interface Pins (DELIC-LC) Pin Symbol In (I) No. Out ( I The direction of these pins 23 D5 depends on the value of the 22 D4 following pins CS, ...
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Preliminary Table 4 Microprocessor Bus Interface Pins (DELIC-LC) (cont’d) Pin Symbol In (I) No. Out ( ALE I 7 MODE I 6 IREQ O (OD) 5 IACK I 29 RESET I 89 RESIND O Data ...
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Preliminary Table 5 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) Pin Symbol In (I) No. Out (O) 87 PFS I/O 88 PDC I/O 76 RxD0 / I LRxD2 I 78 TxD0 / O LTxD2 ...
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Preliminary Table 5 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-LC) (cont’d) Pin Symbol In (I) No. Out (O) 81 TSC2 O 75 RxD1 / I LRxD3 I 80 TxD1 / O LTxD3 O(OD) 79 ...
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Preliminary Table 6 Clock Generator Pins (DELIC-LC) (additionally to IOM/PCM clocks) Pin Symbol In (I) No. Out (O) 94 CLK16- CLK16- DCXOPD I 2 CLK_DSP I 3 DSP_FRQ I 48 L1_CLK O 28 CLKOUT O 4 ...
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Preliminary Table 7 Power Supply Pins (DELIC-LC) Pin Symbol In (I) No. Out ( ...
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Preliminary Table 8 JTAG and Emulation Interface Pins (DELIC-LC) Pin Symbol In (I) No. Out (O) Used for boundary scan according to IEEE 1149.1 54 JTCK I 53 TMS I 52 TDI / I SCANEN 51 TDO O 55 TRST ...
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Preliminary Table 9 Test Interface Pins (DELIC-LC) Pin Symbol In (I) No. Out (O) 50 SCANMO I Data Sheet During After Function Reset Reset I I Scan Mode If driven to ’1’ during device tests, TDI input is used as ...
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Preliminary 2.4 Pin Definitions and Functions for DELIC-PB Note: The column “During Reset” refers to the time period that starts with activation of RESET input and ends with the deactivation of the RESIND output. During this period, the DELIC strap ...
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Preliminary ® Table 10 IOM -2 Interface Pins (DELIC-PB) Pin Symbol In (I) No. Out(O) 39 FSC O 40 DCL O 43 DD0 O(OD) High Z 44 DD1 O(OD) High Z 41 DU0 I 42 DU1 I 45 DRDY I ...
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Preliminary Table 11 IOM-2000 Interface / LNC Port 1 (DELIC-PB) Pin Symbol In (I) No. Out (O) 70 DCL_2000 / O LTSC1/ O LRTS1 LTxD1 O (OD LRxD1 I 67 CMD / ...
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Preliminary Table 12 LNC Port 0 (DELIC-PB) Pin Symbol In (I) No. Out (O) 62 LRxD0 I 61 LTxD0 O (OD) High Z 60 LTSC0 / O LRTS0 59 LCxD0 / I LCTS0 56 LCLK0 I/O Data Sheet During After ...
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Preliminary Table 13 Microprocessor Bus Interface Pins (DELIC-PB) Pin Symbol In (I) No. Out ( I The direction of these pins 23 D5 depends on the value of the 22 D4 following pins CS, ...
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Preliminary Table 13 Microprocessor Bus Interface Pins (DELIC-PB) (cont’d) Pin Symbol In (I) No. Out ( WR/ I R ALE I 7 MODE I 6 IREQ O (OD) 5 IACK I ...
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Preliminary Table 13 Microprocessor Bus Interface Pins (DELIC-PB) (cont’d) Pin Symbol In (I) No. Out (O) 29 RESET I 89 RESIND O Data Sheet During After Function Reset Reset I I System Reset DELIC is forced to go into reset ...
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Preliminary Table 14 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) Pin Symbol In (I) No. Out (O) 87 PFS I/O 88 PDC I/O 76 RxD0 / I LRxD2 I 78 TxD0 / O LTxD2 ...
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Preliminary Table 14 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (cont’d) Pin Symbol In (I) No. Out (O) 74 RxD2 / I LCxD2/ I LCTS2 82 TxD2 / O LCLK2 I/O 81 TSC2 O ...
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Preliminary Table 14 PCM Interface Ports 0 ... 3 / LNC Ports 2 ... 3 (DELIC-PB) (cont’d) Pin Symbol In (I) No. Out (O) 79 TSC1 / O LTSC3/ LRTS3 71 RxD3 / I LCxD3/ I LCTS3 86 TxD3 / ...
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Preliminary Table 15 Clock Generator Pins (DELIC-PB) (Additionally to IOM/PCM Clocks) Pin Symbol In (I) No. Out (O) 94 CLK16- CLK16- DCXOPD I 2 CLK_DSP I 3 DSP_FRQ I 48 L1_CLK O 28 CLKOUT O 4 ...
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Preliminary Table 16 Power Supply Pins (DELIC-PB) Pin Symbol In (I) No. Out ( ...
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Preliminary Table 17 JTAG and Emulation Interface Pins (DELIC-PB) Pin Symbol In (I) No. Out (O) Used for boundary scan according to IEEE 1149.1 54 JTCK I 53 TMS I 52 TDI / I SCANEN 51 TDO O 55 TRST ...
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Preliminary Table 18 Test Interface Pins (DELIC-PB) Pin Symbol In (I) No. Out (O) 50 SCANMO I Data Sheet During After Function Reset Reset I I Scan Mode If driven to ’1’ during device tests, TDI input is used as ...
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Preliminary 2.5 Strap Pin Definitions Table 19 Strap Pins (Evaluated During Reset) Pin No. Strap Name Strap Function DREQR CLOCK (11) MASTER DSP_STOP BOOT (63) DCL (40): TEST(2) TSC3 (83): TEST(1) TSC2 (81) TEST(0) DREQT EMULATION (10) BOOT Data Sheet ...
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Preliminary Table 19 Strap Pins (Evaluated During Reset) (cont’d) LTSC PLL (60) BYPASS TSC1 PLL POWER (79) DOWN TSC0 RESET (77) COUNTER BYPASS Note: When the strap pins are not driven externally during reset, they are driven by internal pull-ups/pull-downs. ...
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Preliminary 3 Interface Description 3.1 Overview of Interfaces The DELIC provides the following system interfaces: IOM-2000 Interface A new serial layer 1 interface driving up to three VIP/ VIP8 (Versatile ISDN Port, PEB 20590/ PEB 20591). Each VIP provides eight ...
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Preliminary 3.2 IOM-2000 Interface 3.2.1 Overview The IOM-2000 interface represents a new concept for connecting ISDN layer-1 devices to the DELIC. The transceiver unit (TRANSIU) and the DSP perform the layer-1 protocol, which enables flexible and efficient operation of the ...
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Preliminary 3.2.2 IOM-2000 Frame Structure 3.2.2.1 Data Interface On the ISDN line side of the VIP, data is ternary coded. Since the VIP contains logic to detect the level of the signal, only the data value is transferred via IOM-2000 ...
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Preliminary FSC DCL F-bit Ch0 bit0 Ch1 bit0 (data) Ch2 bit0 DX/DR Ch1,3,5 mode (LT-S) Ch0,2,4 mode PN Figure 12 IOM-2000 Data Sequence (1 VIP with 8 Channels) Note: 1. Data transfer on IOM-2000 interface always ...
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Preliminary FSC DCL F-bit Ch0 bit0 Ch23 bit0 Ch24 bit0 DX/DR (example for 24 channels in U Figure 13 IOM-2000 Data Order (3 VIPs with 24 Channels) Receive Data Channel Shift In receive direction (DR), data of all IOM-2000 channels ...
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Preliminary 3.2.2.2 Command and Status Interface The CMD and STAT lines are the configuration and control interface between DELIC and VIP. The bit streams are partitioned into 32-bit words carrying information dedicated to the VIPs (CMD_0 / STAT_0) followed by ...
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Preliminary Commands to VIP_n (CMD_n ... 2) Initialization and control information for each VIP is sent by DELIC in the following sequence every 125 µs via the IOM-2000 CMD line (32 CMD_n bits per VIP_n): Note: All ...
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Preliminary Status from VIP_n ( ... 2) Status information is sent by each VIP in the following sequence via the STAT line (32 STAT_n bits per VIP_n): 31 STAT_n ...
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Preliminary 3.2.3 State Machine U PN 3.2.3.1 INFO Structure on the U Signals controlling and indicating the internal state of all U are called INFOs. Four different INFOs (INFO 0, 1W may be sent over the ...
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Preliminary Note: The M channel superframe contains code violation [1 kbit/s (once in every fourth frame)] S bits transparent[1 kbit/s channel] T bits transparent[2 kbit/s channel] DC balancing bit Framing bit 2) Data Sheet Interface Description ...
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Preliminary 3.2.3.2 Mode State Diagram U PN ARx ARx i1 i1 RSY ARx Figure 16 U State Diagram PN Data Sheet TM1 TIM TM2 ...
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Preliminary The U state machine has unconditional and conditional states (refer to Figure 16): PN Unconditional States Reset This state is entered unconditionally after a low appears on the RESET pin or after the receipt of command RES (software reset). ...
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Preliminary Pending Activation This state results from a request for activation of the line, either from the terminal (INFO 1w) or from the layer-2 device (AR, AR2). INFO 2 is then transmitted and the DSP waits for the responding INFO ...
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Preliminary Table 23 U State Machine Codes (cont’d) PN Command Abbr. Activate indication = AI "blocked" Deactivate DC confirmation (x) unconditional commands Note: The U state machine does support loops but neither C/I commands (ARL) nor PN Indications are provided ...
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Preliminary 3.2.4 S/T State Machine A finite state machine in the DELIC controls the VIP S/T line activation/deactivation procedures and transmission of special pulse patterns. Such actions can be initiated by primitives (INFOs) on the S/T interface or by C/I ...
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Preliminary 3.2.4.1 LT-S Mode Table 24 LT-S State Machine Codes Command Deactivate request Reset Test mode 1 Test mode 2 Activate request Deactivate confirmation (x) unconditional commands Note: The LT-S state machine does not support loops. So neither C/I commands ...
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Preliminary RESET TIM RES DR R ese RES Any State DELPHI LT-S SM.vsd Figure 17 State Diagram of LT-S Mode Data Sheet TIM ct ARD 1) ...
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Preliminary LT-S Mode States • G1 deactivated The line interface is not transmitting. There is no signal detected on the S interface, and no activation command is received. • G2 pending activation As a result of an INFO 1 detected ...
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Preliminary 3.2.4.2 LT-T Mode Table 25 LT-T Mode State Machine Codes (Conditional States) Command Timing Request Reset Test mode 1 Test mode 2 Activate request, priority 8 AR8 Activate request, priority 10 Activate request loop Deactivate indication (x) unconditional commands ...
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Preliminary Indication Deactivate request Reset Test mode 1 Test mode 2 Slip detected Re-synchronization during level detect Power up Activate request Activate request loop Code violation received Activate indication loop Activate indication with priority class 8 Activate indication with priority ...
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Preliminary Pending Act. TIM RSY TIM i4 F5 Unsynchronized Synchronized Lost Framing ...
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Preliminary LT-T Mode (Conditional States) • F3 power down This is the deactivated state of the physical protocol. The receive line awake unit is active. • F3 power up This state is similar to “F3 power down”. The state is ...
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Preliminary LT-T Mode (Unconditional States) The unconditional states should be left with the command TIM. • Test mode 1 Single alternating pulses are sent on the T interface (2 kHz repetition rate). • Test mode 2 Continuous alternating pulses are ...
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Preliminary 3.3 IOM -2 Interface ® IOM standardized interface for interchip communication in ISDN line cards for digital exchange systems developed by ALCATEL, Siemens, Plessey and ITALTEL. The IOM-2 interface is a four-wire interface with a bit clock, ...
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Preliminary 3.4 µP Interface The µP interface may be operated in different modes. This chapter describes how to configure the DELIC to each mode. 3.4.1 Intel/Infineon or Motorola Mode The processor mode is selected by the MODE input pin of ...
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Preliminary Multiplexed Mode µP AD ALE De-multiplexed Mode µ Figure 20 DELIC in Multiplexed and in De-Multiplexed Bus Mode Note: In both modes only the 7 LSBs of A-bus or AD/bus are connected to the Address inputs of ...
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Preliminary 3.4.3 DMA or Non-DMA Mode The internal interface between the on-chip DSP and µP is established by two Mailboxes: a ’general’ Mailbox and a dedicated DMA Mailbox. The non-DMA mode provides the option to combine them together building a ...
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Preliminary 3.5 JTAG Test Interface The DELIC provides fully IEEE Standard 1149.1 compatible boundary scan support to allow cost effective board testing. It consists of: • Complete boundary scan test • Test access port controller (TAP) • Five dedicated pins: ...
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Preliminary EXTEST is used to verify the board interconnections. When the TAP controller is in the state “update DR”, all output pins are updated with the falling edge of JTCK. When it has entered state “capture DR” the levels of ...
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Preliminary 4 Functional Description As the functionality of the DELIC-PB comprises the functionality of the DELIC-LC, the following chapter describes the functionality of the DELIC-PB. The differences between the two chip versions (considering also the firmware) can be seen below: ...
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Preliminary 4.1 Functional Overview and Block Diagram Figure 21 Block Diagram Data Sheet ... 70 PEB 20570 PEB 20571 Functional Description 2001-03-19 ...
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Preliminary 4.2 IOM-2000 Transceiver Unit (TRANSIU) 4.2.1 IOM-2000 Features • The TRANSIU controls layer-1 channels via up to three VIP/ VIP8 connected to IOM-2000 interface • IOM-2000 interface: all channels may be programmed in the IOM-2000 to: ...
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Preliminary • Three VIPs connected at data rate of 9.216 Mbit/s: 24 IOM-2000 channels at a clock rate of 12.288 MHz. (Note the difference between clock rate and actual data rate) 4.2.3 Initialization of the VIP During startup the VIP ...
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Preliminary Transmit Direction • The command information per VIP is prepared by the DSP in the VIPCMR0-2 registers • The command bits from initialization command group are prepared by the DSP in the TICCMR register for one of the channels ...
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Preliminary 4.2.4.4 Command and Status format in the Data RAM The operational mode command and status bits usually are served completely by the firmware. So there is no need to set this bits by the user. Operational Mode Command bits ...
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Preliminary Operational Mode Status bits in the data RAM: Address:see memory map MSYNC RxSTA(1:0) Receiver Status Change (S/ Receiver is not synchronized to the line; no signal on line (INFO Level ...
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Preliminary 4.2.5 U Mode Frame Structure PN The U interface uses a ping-pong technique for 2B+D data transmission over the line always point-to-point. PN The frame structure of the data transfer between the exchange (PBX, LT) and ...
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Preliminary LT TE/ Figure 22 U Interface Frame Structure PN Up Coding (in VIP) The coding technique used on the Up interface is a half-bauded AMI code (with pulse width (refer ...
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Preliminary Figure 23 AMI Coding on the Up Interface Data Sheet Functional Description 78 PEB 20570 PEB 20571 2001-03-19 ...
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Preliminary 4.2.6 U Interface PN The data is received and transmitted at a nominal bit rate of 384 kbit/s. In the first half of the 4 KHz frame data is transmitted and ‘zeros’ are received, in the second half of ...
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Preliminary 4.2.7 U Framing Bit Description PN 4.2.7.1 Framing Bit (LF-Bit) On the U interface the framing (LF) bit is always logical ‘1’ the transmit direction the LF-bit is inserted by the TRANSIU at the beginning of every ...
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Preliminary S-bit The S-bit received on the U stream, and is logical OR’ ed with the detected far-end code violation. The result is sent to the DELIC as status bit ’FECV’. In transmit direction, the S-bit value is sent in ...
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Preliminary U 4.2.7.5 Scrambler/Descrambler PN B-channel data on all U PN continuous power density spectrum on the line. Scrambling is done according to ITU-T V.27 with the generator polynomial OCTAT-P and DASL. Initialization via History RAM (HRAM) ...
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Preliminary 4.2.9 S/T Interface Frame Structure The S/T interface establishes a direct link between the VIP and connected subscriber terminals or to the Central Office. It consists of two pairs of copper wires: one for the transmit and one for ...
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Preliminary Figure 26 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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Preliminary Ch_0 VIP_0 CH_7 CLKIN_0 VIP_1 Ch_0 Reference Clock LT-T Ch_7 CLKIN_1 VIP_2 Ch_0 Ch_7 CLKIN_2 Figure 27 Reference Clock Selection for Cascaded VIPs on IOM-2000 Note: A change in the reference clock source must not result in a FSC ...
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Preliminary 4.2.9.1 LT-S mode Tx: VIP hardware: F-bit & CV generation Inversion of data (B1, B2, D) E-bit mirroring VIP Tx F INV F,L INV Rx FIFOs Rx Rx: VIP hardware: F-bit & CV detection FIFOs: -for jitter etc. Inversion ...
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Preliminary D-echo Bit Generation in LT-S Mode In the LT-S mode, the last received D-bit has to be reflected in the next available E-bit (E=D). If there are no HDLC controllers available, the D-channel is blocked (E=D is transmitted). Since ...
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Preliminary 4.2.9.2 LT-T Mode Tx: VIP hardware: F-bit & CV generation Inversion of data (B1, B2, D) VIP Tx D INV Rx FIFOs INV Rx F,L E Rx: VIP hardware: F-bit & CV detection E-bit collision detection FIFOs: - for ...
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Preliminary • The B-channel data is prepared by the DSP in the Data RAM and inserted into the downstream frame by the TRANSIU • If collision was detected on the D-channel, the data transmission on this channel is blocked by ...
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Preliminary DELIC Figure 31 Collision Detection in the LT-T Mode 4.2.10 S/T Mode Control and Framing Bits on IOM-2000 4.2.10.1 Framing Bit (F-Bit) The framing (F) bit is recognized on the TRANSIU interface, when both data and control bits are ...
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Preliminary S LT Figure 32 S/Q Channel Assignment Data Sheet IOM-2000 DELIC VIP LT-T 91 PEB 20570 PEB 20571 Functional Description 2001-03-19 ...
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Preliminary Table 29 S/T Mode Multiframe Bit Positions Frame number LT LT-T, F bit position ... ... Note: ...
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Preliminary 4.2.10.4 DC-Balancing Bit (L-Bit) In transmit (downstream) direction the L-bit is generated in compliance with ITU-T I.430: • A balance bit is ‘0’ if the number of 0’s following the previous balance bit is odd. • A balance bit ...
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Preliminary LT-T Mode Transmit Data Format 7 6 D-channel Operation Mode Command/Status bits LT-T Mode Receive Data Format 7 6 D-channel Operation Mode Command/Status bits CBN Collision Detection Bit Number 0 = Collision was detected in the first D-bit of ...
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Preliminary 4.3 IOM-2 Unit 4.3.1 IOMU Features The IOMU provides the DSP access to incoming time slots from the IOM-2 interface. Features • DSP access for switching of B1 and B2 data to the PCMU, TRANSIU and IOMU (providing a ...
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Preliminary 4.3.2 IOMU Functional and Operational Description IOM-2 Interface DELIC FSC DCL DD0 D,C/I DU0 D.C DD1 D,C/I DU1 D.C DRDY IOM-2000 Interface Figure 33 IOMU Integration in ...
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Preliminary Table 30 I-Buffer Logical Memory Mapping Data Rate in0 2 x 2.048 Mbit 384 kbit 768 kbit 4.096 Mbit 4.3.2.3 DSP Access to the D-Buffer ...
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Preliminary 4.3.2.4 Circular Buffer Architecture DELIC IOMU DU1 Serial DU0 DD1 Serial DD0 Figure 34 IOMU Frame-Wise Circular-Buffer Architecture The following description analyses the frame-wise circular-buffering scheme frame to frame basis. Assume that during frame n, buffer-0 is ...
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Preliminary A buffer-swapping takes place at the end of frame- the end of any other frame. This means that during frame-n+1, buffer-1 is used as I-buffer, while buffer-0 is used as D-buffer. During this frame the IOMU handles ...
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Preliminary 4.3.2.5 IOM-2 Interface Data Rate Modes The IOMU may support different serial data rates of the IOM-2 interface: • 384 kbit/s (6 time slots per frame) • 768 kbit/s (12 time slots per frame) • 2.048 Mbit/s (32 time ...
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Preliminary FSC Frame Start DCL TS31 TS0 DD0/1 bit0 bit7 DU0/1 TS31 TS0 bit0 bit7 FSC Frame Start DCL TS31 TS0 bit0 DD0/1 DU0/1 TS31 bit0 = Upstream Sampling Figure 36 IOM-2 Interface Timing in Single/Double Clock Mode 4.3.2.6 IOMU ...
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Preliminary 4.3.2.8 IOM-2 Push-Pull and Open-Drain Modes The IOM-2 ports can be configured to Push-Pull or Open-Drain modes by a dedicated bit in the IOMU Control Register. When programmed to Open-Drain, DD0/DD1 is tri- stated when a ‘1’ is supposed ...
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Preliminary 4.3.2.9 Support of DRDY Signal from QUAT-S The DRDY input is used when connecting an Infineon QUAT-S transceiver to the DELIC via the IOM-2 interface driven by the QUAT-S to inform the DELIC when a D- channel ...
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Preliminary 4.4 PCM Unit PCM Interface Features The PCMU enables the DSP to control the 4 PCM ports. The DSP accesses the incoming PCM time slots, and prepares the outgoing PCM time slots. In general, the PCMU enables the DSP ...
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Preliminary 4.4.1 PCMU Functional and Operational Description IOM Unit HDLC Unit TRANSIU Figure 41 PCMU Integration in DELIC The PCM-unit signals share port pins with the GHDLC-unit. A multiplexer controlled by register MUXCTRL allows to define the required functionality. 4.4.1.1 ...
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Preliminary Table 33 I-Buffer Logical Memory Mapping of Input Buffers Data Rate related port 4 x 2.048 Mbit 4.096 Mbit 8.192 Mbit 16.384 Mbit/s Table 34 I-Buffer Logical Memory Mapping of Output Buffers Data ...
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Preliminary Table 36 DSP Access to D-Buffer Output Blocks Data Rate out0 related port TXD0 4 x 2.048 Mbit/s A080 4.096 Mbit/s A080 A0BF 1 x 8.192 Mbit/s A080 16.384 Mbit/s A080 H Note: ...
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Preliminary Figure 36 shows the PCM interface timing with single and double rate PDC. PFS Frame Start PDC TS31 TS0 TXD bit0 bit7 RXD TS31 TS0 bit0 bit7 PFS Frame Start PDC TS31 TS0 TXD bit0 RXD TS31 bit0 = ...
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Preliminary 4.4.1.7 PCMU Tri-state Control Logic There are eight 16-bit tri-state control registers in the PCMU. Each bit determines whether its associated time slot is valid or invalid. • '0' = the controlled time slot is invalid • '1' = ...
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Preliminary 128 time slot per frame mode, only PCM port 0 is used. TSC1, TSC2 and TSC3 are permanently '0' (all time slots are invalid 256 time slot per frame mode, only one half ...
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Preliminary 4.5 A-/µ-law Conversion Unit The A-/µ-law Unit performs a bi-directional conversion between a linear representation of voice data and its companded representation (according to A-law or µ-law). The conversion is applicable on all B-channels via IOM-2, IOM-2000 or PCM. ...
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Preliminary A-/µ-law to Linear Conversion The conversion is done via a 512 x 16 ROM table. The low 256 bytes translate the A-law value into linear, while the high 256 words translate the µ-law to linear. The DSP issues a ...
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Preliminary 4.6 HDLC Unit 4.6.1 HDLC Overview High-level data link control (HDLC most common protocol in the data link layer, layer 2 of the OSI model. Signalling protocols LABD and LAPB are based on HDLC and its framing ...
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Preliminary The HDLC automatically recognizes HDLC frames with the following interframe time fill combinations: • n consecutive flags ( 3,.. ; called shared flag, if the closing flag of one frame is the ...
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Preliminary The DSP assigns each time slot used for transmitting an HDLC message to a different address in the Receive/Transmit Input Buffers. The HDLCU decodes/encodes the time slots into the corresponding addresses in the Receive/Transmit Output Buffers. During every frame, ...
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Preliminary 4.6.2.3 Ending a Transmission When placing the last octet of the message into the Transmit Input Buffer, the DSP places an End transmission command in place of the Start transmission command without changing the CRC bit. If CRC encoding ...
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Preliminary In receive direction, the processor fetches the D-channel (16 kbit/s signalling) or the B- channel (64 kbit/s) from the assigned timeslot and writes it into the corresponding channel register of the HDLC Unit. After the HDLC Unit encoded the ...
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Preliminary The processor handles the HDLCU (tasks 1) during every IOM frame, i.e. every 125 16-kbit/s channel is handled, the task 2 is performed about every 4th to 5th frame (4 x 2-bit writing to the HDLCU ...
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Preliminary 4.7 GHDLC Unit 4.7.1 GHDLC Overview Messages are transceived serially, bit by bit over the line and undergo encoding/ decoding according to the HDLC protocol. A received message is collected bit by bit from the line and stored as ...
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Preliminary • Transparent Mode: No HDLC framing exists. In the receive direction everything on the line is automatically passed to the buffer. Each time the buffer is filled an interrupt to the DSP is generated. • Asynchronous Mode: This mode ...
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Preliminary Polling means that the DSP is polled to see if it has anything to send by way of a frame which is actually a question. The GHDLC simply receives this frame and passes the DSP like ...
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Preliminary Figure 48 Point-to-Multi Point Bus Structure If a Txd and CxD difference occur, the HDLC aborts its transmission, generates an interrupt for the DSP reporting the collision and disables the output of TxD (High Impedance or ‘1’ programmable selecting). ...
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Preliminary Receive Buffer Block 0 one channel 32 bytes two channels 16 bytes four channels 8 bytes This leads to the following address configuration: Table 41 GHDLCU Receive Buffer Configuration No. of Direction Channels 1 channel Receive Transmit 2 channels ...
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Preliminary Receive Buffer DSP read Transmit Buffer DSP write Figure 49 GHDLC Receive and Transmit Buffer Structure The GHDLC unit and DSP always read and write to different areas in the RAM. Memory is equally allocated to each of the ...
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Preliminary 4.7.7 GHDLC Protocol Features The following GHDLC features related to HDLC protocol may be selected in HDLC mode: • Collision Detection: May be active or inactive (relates only to the transmit direction) • Flags / Ones Interframe: Flags or ...
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Preliminary 4.7.9 GHDLC Using external DMA Controller One of the four GHDLC channel of the DELIC-PB can be assigned to the DMA mailbox handled by an external DMA controller. The detailed handling of DMA is described in Page 133. Data ...
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Preliminary 4.8 DSP Control Unit 4.8.1 General The DSP Control Unit (DCU) controls the DSP access to DELIC’s blocks. It performs the following tasks: • DSP program and data address decoding • Interrupt handling • Data Bus and Program Bus ...
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Preliminary Note: The NMI interrupt maybe enabled/disabled in the INTMASK register. 4.8.4 DSP Run Time Statistics The DSP run time statistics is used for the DSP work load estimation. By using this HW, the maximum time spent by the DSP ...
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Preliminary The user program should perform statistics in the following way: • The STATC is reset upon detection of FSC rising edge. • The DSP finishes its activities and reads the value of STATC and STATI. The DSP compares STATC ...
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Preliminary The program code is now transferred in pieces of maximum 15 words by use of the "Write Program Memory Command". MDT0 = 0xDESTINATION_ADDRESS MDTn = 0xOPCODE_WORDn MCMD = 0xAn[n=1..15 number of code words to write to address++] Before writing ...
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Preliminary 4.9 General Mailbox 4.9.1 Overview The µP and the DSP communicate via a bidirectional Mailbox according to the mailbox protocol described in DELIC-LC/-PB Software User’s Manual. The DELIC provides two dedicated Mailboxes that may be used in two operational ...
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Preliminary Data Transfer from the µP to the OAK • The µP reads the busy bit and checks whether the Mailbox is available (MBUSY=’0’) • The µP writes to the Data registers MDTn (optional) • The µP writes to the ...
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Preliminary Data Transfer from the OAK to the µP • The OAK reads the busy bit and checks whether the MB is available (OBUSY=’0’) • The OAK writes to the data registers ODTn (optional) • The OAK writes to the ...
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Preliminary DMA mode, and the data transfer direction. Two DMA modes are supported: • Two-cycle DMA transfer mode called also Memory-to-memory mode • Single cycle DMA transfer mode called also Fly-by mode An example for a two-cycle DMA transfer in ...
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Preliminary DMA Controller 1-Cycle-Mode Figure 53 Single cycle DMA transfer mode for Receive Data Example for a single-cycle DMA transfer mode in receive direction (data is read from DELIC and written to memory) in Intel/Infineon Mode. 1. The DMA mailbox ...
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Preliminary DMA Controller 1-Cycle-Mode-T Figure 54 Single cycle DMA transfer mode for Transmit Data 1. The DMA transmit mailbox is empty 2. DELIC requests DMA service via DREQT 3. The DMA controller addresses memory with ADDR and the DELIC with ...
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Preliminary 2. Select the type of used data bus via DELIC pin "MODE": Intel/ Infineon or Motorola 3. Set byte count by writing the number of bytes to be transferred, minus 1, into DTXCNT/DRXCNT register (is handled by the OAK ...
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Preliminary • A 4-bit Interrupt status register (DINSTA), which actually belongs to both directions - Transmit and Receive. The DELIC initiates all transfers, i.e. each transmit is initiated by the OAK. But the transfers are carried out by the DMA ...
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Preliminary After the DMA Controller has written the requested number of bytes to the transmit mailbox, DTXCNT becomes ’F programmed to cause an interrupt (INT0) to the OAK. The OAK can now read the data from the transmit mailbox: - ...
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Preliminary If the DMA controller grants the bus to the DELIC, it drives DACK low and begins toggling the control lines. In Memory-to-Memory mode on Intel / Infineon bus type, it drives RD line low when reading from the receive ...
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Preliminary 4. The DMA controller asserts DACK and issues (Rc_Num+1) read transactions from the receive mailbox (“FIFO”). 5. DREQR is deasserted (“high” or “low”). 6. If RMSK bit in DINSTA is inactive (“1”), the DMA interrupt to OAK (INT0) is ...
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Preliminary 4.11 Clock Generator 4.11.1 Overview The DELIC clock generator provides all necessary clock signals for the DELIC and connected clock slave devices. The internal clocks are generated by two on-chip PLLs digital controlled oscillator (DCXO) generates a ...
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Preliminary 16.384 MHz CLK16-XI DELIC DCXO SHP PLL 3.072 MHz 6.144 MHz 61.44 12.288 MHz MHz :20 :10 DCL_2000 :5 DSP_CLK (Fallback) MUX DSP CLK :2 : :30 :80 :1 :160 :2 :2 15.36 MHz 7.68 MHz L1_CLK ...
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Preliminary 4.11.2 DSP Clock Selection The default DSP clock is the internal 61.44 MHz generated by the PLL. For test purpose, a different frequency may be provided via DSP_CLK input pin. The selection between the internal 61.44 MHz or external ...
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Preliminary 4.11.6 IOM-2000 Clock Selection The IOM-2000 interface uses the same FSC like IOM-2, whereas the data clock DCL2000 is a dedicated pin (always output). 4.11.7 REFCLK Configuration REFCLK is an I/O pin for synchronizing the PCM interface (to 8 ...
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Preliminary 5 DELIC Memory Structure The following tables provide the DELIC memory map for the DSP and the µP. 5.1 DSP Address Space 5.1.1 DSP Register Address Space T Table 44 DSP Registers Address Space Address Description D000 - D01F ...
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Preliminary 5.1.3 DSP Data Address Space A1 Table 46 Occupied DSP Data Address Space Address Size 0000 - 03FF 1Kw 2000 - 203F 64w 2040 - 207F 64w 4000 - 401F 32w 4020 - 403F 32w 4040 - 405F 32w ...
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Preliminary Note: (*) The OAK memory mapped registers address space is described in the following table: (**) Accessing these addresses may cause unpredictable results. Table 47 OAK Memory Mapped Registers Address Space Address D000 - D01F D020 - D03F D040 ...
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Preliminary TRANSIU Receive Buffer TRANSIU Transmit Buffer Figure 58 TRANSIU Buffer Addresses Data Sheet 6000 B1-channel data H 6001 B2-channel data H 6002 D H 6003 H 6004 B1-channel data H 6005 B2-channel data H 6006 D H 6007 H ...
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Preliminary 5.2 µP Address Space The µP address space consists of the general mail-box registers, the DMA mail-box registers (only in non-DMA mode), the µP-interface control register, and the µP-interface status register (MISR) . Table 48 µP Address Space Table ...
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Preliminary 6 Register Description 6.1 Register Map Table 49 TRANSIU Register Map Reg Name Access Address TICR RD/WR D0A0 TCCR0 RD/WR D0A1 TCCR1 RD/WR D0A2 TCCR2 RD/WR D0A3 VIPCMR0 WR D0A8 VIPCMR1 WR D0A9 VIPCMR2 WR D0AA VIPSTR0 RD D0AC ...
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Preliminary Table 50 Scrambler Register Map Reg Name Access Address SCMOD RD/WR D010 SCSTA RD/WR D011 Table 51 IOMU Register Map Reg Name Access Address ICR R/W D040 ISR R D041 ITSCR Set (W) D042 Reset D043 (W) R D044 ...
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Preliminary Table 52 PCMU Register Map (cont’d) Reg Name Access Address PTSC3 RD/WR D068 (read/set) D069 (read/reset) PTSC4 RD/WR D06A (read/set) D06B (read/reset) PTSC5 RD/WR D06C (read/set) D06D (read/reset) PTSC6 RD/WR D06E (read/set) D06F (read/reset) PTSC7 RD/WR D070 (read/set) D071 ...
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Preliminary Table 54 HDLCU Register Map Reg Name Access Address HCR W D180 HSTA R D180 HCCV R/W 4040 HCSV R 40A0 Table 55 GHDLC Register Map Reg Name Access Address GTEST W D0C0 GCHM W D0C1 GINT R D0D4 ...
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Preliminary Table 55 GHDLC Register Map (cont’d) Reg Name Access Address GLCLK1 R/W D08B GLCLK2 R/W D08C GLCLK3 R/W D08D MUXCTRL R/W D14A ST2 W OAK register Table 56 DCU Register Map Reg Name Access Address IMASK R/W D002 STEVE ...
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Preliminary Table 58 General Mailbox Register Map Reg- Descrip- Reset ister tion Value (16 bit) MCMD P 00 command MBUS P MB busy MGEN P generic unchanged 16 R data reg. MDT0 P data unchanged 16 R ...
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Preliminary Table 58 General Mailbox Register Map (cont’d) Reg- Descrip- Reset ister tion Value (16 bit) OGEN DSP unchanged 16 W generic data reg ODT0 DSP data unchanged 16 W reg0 ODT1 DSP data unchanged 16 W reg1 ODT2 DSP ...
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Preliminary Table 59 DMA Mailbox Register Map Register Description DTXCN Tx counter T DINSTA DMA Int status TDT0/ Tx data reg0/ MDT8 P data reg8 TDT1/ Tx data reg1/ MDT9 P data reg9 TDT2/ Tx data reg2/ MDT10 P data ...
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Preliminary Table 59 DMA Mailbox Register Map (cont’d) Register Description RDT1/ Rx data reg1/ ODT9 DSP data reg9 RDT2/ Rx data reg2/ ODT10 DSP data reg10 RDT3/ Rx data reg3/ ODT11 DSP data reg11 RDT4/ Rx data reg4/ ODT12 DSP ...
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Preliminary Table 60 Clock Generator Register Map Reg Name Access Address CPDC R/W D080 CPFS R/W D081 CLKOUT R/W D082 CREFSEL R/W D083 CREFCLK R/W D084 CDCL2 R/W D085 CDCL R/W D086 CFSC R/W D087 CL1CLK R/W D088 CPFSSY R/W ...
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Preliminary 6.2 Detailed Register Description 6.2.1 TRANSIU Register Description 6.2.1.1 TRANSIU IOM-2000 Configuration Register TICR Register Reset value: 0000 H Note: The reset value of bit 4KFSC is undefined, since this read-only bit is toggled every 250 µ ...
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Preliminary 6.2.1.2 TRANSIU Channel Configuration Registers The Channel registers are used for IOM-2000 channel disabling and mode programming. Each IOM-2000 channel may be programmed to U mode, or completely disabled. Important Only four channels out of eight channels are programmable ...
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Preliminary C7..0M(1:0) Operational Mode of IOM-2000 Channel7.. Channel is configured to S mode (LT- Channel is configured to S mode (LT- Channel is configured Channel is disabled, ’0’s are sent ...
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Preliminary 6.2.1.3 VIP Command Registers (VIPCMR0, VIPCMR1, VIPCMR2) The VIPCMR0-2 registers contain command information dedicated to the VIP (only the VIPCMR0 is shown here, VIPCMR1 and VIPCMR2 have the same structure). VIPCMR Register Reset value: 0000 H ...
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Preliminary external reference clock source. Reference clock is generated REFCLK(2:0) and passed on via REFCLK pin to VIP_n-1 or directly to DELIC Reference clock is generated from external source via pin INCLK and passed on ...
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Preliminary 1 = The DSP reads the VIP register (during initialization, debugging or error conditions). The register value is available for the read operation in the consecutive frame (after the next FSC). Note: To avoid blocking, the DSP must not ...
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Preliminary 6.2.1.4 VIP Status Registers The VIPSTR0-2 registers contain the status bits received from the dedicated VIP for VIPs respectively (all three registers have the same structure). VIPSTR Register VIPSTR0: D0AC , H Reset value: 0000 H ...
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Preliminary 6.2.1.5 TRANSIU Initialization Channel Command Register The Initialization Channel Command Register contains the Command bits for VIP_n, Channel_m together with 5 bits of the VIP channel address. The VIP only acts upon the command bits if they were declared ...
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Preliminary 1 = DELIC read request of the TICCMR register which was sent to the VIP. It includes initialization and configuration commands and the channel addresses. The VIP returns these values (instead of sending the actual VIP status information) within ...
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Preliminary ... 111 = 16 BBC(1:0) Balancing Bit Control ( Adaptive generation of balancing bit (depending on line delay). upon reception of INFO3 or INFO4 10 = Balancing bit control is disabled, and no balancing bit is added ...
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Preliminary 0 = Operational mode 1 = Channel_m in power-down mode (only the level detector in the VIP receiver is in operational mode) DHEN D-channel Handling Enable (LT- D-channel transmitted transparently, without any condition 1 = D-channel transmitted ...
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Preliminary 111 = Command word is dedicated to VIP_n Channel_7 VIPADR(2:0) VIP_n Address for Commands 00 = Command word is dedicated to VIP_0 01 = Command word is dedicated to VIP_1 10 = Command word is dedicated to VIP_2 11 ...
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Preliminary 6.2.1.6 TRANSIU Initialization Channel Status Register (TICSTR) The Initialization Channel Status Register contains the Command bits to VIP_n, Channel_m mirrored by the VIP in response to a read command issued by the DELIC in the previous frame. Note: The ...
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Preliminary 6.2.1.7 Up Test Loop Register The Up Test Loop Register allows to switch an analog loop in the VIP for test purposes. TUTLR Register Reset value: 0000 UT(n) ...
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Preliminary 6.2.1.8 Scrambler Mode Register SCMOD Register Reset value: 0003 SCMOD1..0 Scrambling Mode of the Scrambling according to ITU-T V. Scrambling compatible to OCTAT-P PEB 2096 ...
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Preliminary 6.2.1.9 Scrambler Status Register SCSTA Register Reset value: undefined SCSTA0 Descrambler Status 0 = Write access: start of descrambling algorithm for all channels enabled in the HRAM (only valid if bit ...
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Preliminary 6.2.2 IOMU Register Description 6.2.2.1 IOMU Control Register ICR Register Reset value ICDB Idle Current D-Buffer (for test purpose; only if IOMU is in idle mode: ICR:A = ’0’) ...
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Preliminary 6.2.2.2 IOMU Status Register ISR Register Reset value: undefined 15 14 IBUFF IBUFF I-Buffer Index Note: Used for testing. May also be used in double data rate mode of the IOMU to determine if ...
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Preliminary 6.2.2.3 IOMU Tri-State Control Register ITSCR Register Reset Value TS(15:0) Every bit determines whether DD0/1 output is in tri-state during the time slot sequence. The time slot sequence length, indices and port controlled ...
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Preliminary Table 62 Tristate Control Assignment for IOM-2 Time Slots ITSCR TS/frame Bit DD0 TS TS0 DD0 0 TS1 DD0 1 TS2 DD0 2 TS3 DD0 3 TS4 DD0 4 TS5 DD0 5 TS6 not used TS7 ...
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Preliminary 6.2.2.4 IOMU DRDY Register IDRDYR Register Reset value: undefined bit DRDY Sample DSx indicates the availability of the D-channels of the previous frame STOP (D-channel blocked due to collision ...
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Preliminary 6.2.2.5 IOMU Data Prefix Register IDPR Register Reset value IDP(7:0) IOMU Data Prefix Determines the high byte of every word being read from the IOM circular- buffer (I-buffer or D-buffer). The ...
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Preliminary 6.2.3 PCMU Register Description 6.2.3.1 PCMU Command Register PCR Register Reset value: 0000 PDR(1:0) PCM Data Rate 00 = 2.048 Mbit/s (port 0.. 4.096 Mbit/s (port 0, 2) ...