PEB4264VV1.2 Infineon Technologies AG, PEB4264VV1.2 Datasheet
PEB4264VV1.2
Related parts for PEB4264VV1.2
PEB4264VV1.2 Summary of contents
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... Edition 2000-07-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 8/16/00. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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DuSLIC Preliminary Revision History: Previous Version: Page Subjects (major changes since last revision) Page 15 Usage of the term SLICOFI-2x as synonym used for all codec versions SLICOFI-2/-2S/-2S2. Page 33 Chapter 3.1 Page 94 Chapter 4.7.2 were replaced by cross-references ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.8.3 Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/- 3.8.4 Universal Tone Detection (UTD) (only DuSLIC-E/-E2/- ...
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Table of Contents 4.8.2.13 Foreign- and Ring Voltage Measurements . . . . . . . . . . . . . . . . . . . 129 4.9 Signal Path and Test Loops . . . . . ...
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Table of Contents 6.3.4.2 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7.7.2.1 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 43 SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops). 101 Figure 44 Circuit Diagram for Ringing . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 85 Group Delay Distortion Receive and Transmit 353 Figure 86 Out-of-Band Signals at Analog Output (Receive ...
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List of Tables Table 1 DuSLIC Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 43 SLIC-E/-E2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary Preface This document describes the DuSLIC chip set comprising a programmable dual channel SLICOFI-2x codec and two single channel high-voltage SLIC chips. For more DuSLIC related documents please see our webpage at http://www.infineon.com/duslic. To simplify matters, the following synonyms ...
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Preliminary 1 Overview DuSLIC is a chip set, comprising one dual channel SLICOFI-2x codec and two single channel SLIC chips highly flexible codec/SLIC solution for an analog line circuit and is widely programmable via software. Users can ...
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Preliminary The DuSLIC family comprises five different chip sets (see – Three basic DuSLIC chip sets optimized for different applications: DuSLIC-S (Standard), DuSLIC-E (Enhanced), DuSLIC-P (Power Management). – Two different performance versions of the basic DuSLIC-E and DuSLIC-S chip sets: ...
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Preliminary SLIC SLIC HV SLIC Functions Voltage feeding Transversal current sensing Longitudinal current sensing Overload protection Battery switching Ring amplification On-hook transmission Polarity reversal Figure 1 DuSLIC Chip Set Data Sheet SLICOFI-2x LV SLIC Functions Codec Filter Functions Programmable DC ...
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Dual Channel Subscriber Line Interface Circuit DuSLIC Version 1.2 1.1 Features • Internal unbalanced/balanced ringing capability Vrms • Programmable Teletax (TTX) generation • Programmable battery feeding with capability for driving longer loops • Fully programmable dual-channel codec ...
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Preliminary 1.2 Logic Symbols Tip/Ring interface Power supply Figure 2 Logic Symbol SLIC-S / SLIC-S2 / SLIC-E / SLIC-E2 Tip/Ring interface Power supply Figure 3 Logic Symbol SLIC-P Data Sheet TIP RING PEB 4264 PEB 4264-2 PEB 4265 VDD PEB ...
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Preliminary ITA ITB Line ITACA current ITACB ILA ILB VCMITA VCMITB DCPA DC DCPB loop DCNA DCNB CDCPA CDCNA CDCPB CDCNB VCM VCMS ACPA ACPB AC ACNA loop ACNB C1A C1B Logic C2A control C2B IO1A IO2A IO3A I/O IO4A ...
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Preliminary 1.3 Typical Applications • Digital Loop Carrier (DLC) • Wireless Local Loop • Fiber in the Loop • Private Branch Exchange • Intelligent NT (Network Termination) for ISDN • ISDN Terminal Adapter • Central Office • Cable Modem • ...
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Preliminary 2 Pin Descriptions 2.1 Pin Diagram SLIC ...
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Preliminary Table 2 Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2 Pin Symbol Input (I) No. Output (O) 1 RING I/O 2 TIP I/O 3 BGND Power 4 VHR Power 5 VDD Power 6 VBATL Power 7 VBATH Power 8 N.C. ...
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Preliminary Table 2 Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2 (cont’d) Pin Symbol Input (I) No. Output ( Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note ...
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Preliminary Table 3 Pin Definitions and Functions SLIC-P Pin Symbol Input (I) No. Output (O) 1 RING I/O 2 TIP I/O 3 BGND Power 4 N.C. – 5 VDD Power 6 VBATL Power 7 VBATH Power 8 VBATR Power 9 ...
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Preliminary Table 3 Pin Definitions and Functions SLIC-P (cont’d) Pin Symbol Input (I) No. Output ( Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the ...
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Preliminary 2.2 Pin Diagram SLICOFI-2/-2S/-2S2 C1A ILA ITACA ITA VCMITA VDDR GNDR VCMS VCM CREF SELCLK VCMITB ITB ITACB ILB C1B 1 Figure 6 Pin Configuration SLICOFI-2/-2S/-2S2 (top view) Data Sheet PEB 3265 PEB 3264 PEB 3264-2 28 DuSLIC Pin ...
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Preliminary Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 Pin Symbol Input (I) No. Output (O) 1 C2B O 2 DCPB O 3 CDCPB I/O 4 CDCNB I/O 5 DCNB O 6 ACPB O 7 ACNB O 8 VDDB Power 9 ...
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Preliminary Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Symbol Input (I) No. Output ( DOUT O 19 DCL I PCLK DRB I 21 SEL24 I DRA I 22 MCLK I 23 ...
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Preliminary Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Symbol Input (I) No. Output (O) 32 PCM/ I IOM-2 33 RSYNC I 34 RESET I 35 TEST I 36 IO4A I/O 37 IO3A I/O 38 IO2A I/O 39 IO1A ...
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Preliminary Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Symbol Input (I) No. Output (O) 52 ITA I 53 VCMITA I 54 VDDR Power 55 GNDR Power 56 VCMS O 57 VCM O 58 CREF I/O 59 SELCLK I ...
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Preliminary 3 Functional Description 3.1 Functional Overview 3.1.1 Basic Functions available for all DuSLIC Chip Sets The functions described in this chapter are integrated in all DuSLIC chip sets (see Figure 7 for DuSLIC-S/-S2 and All BORSCHT functions are integrated: ...
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Preliminary The characteristics for the two voice channels within SLICOFI-2x can be programmed independently of each other. The DuSLICOS software is provided to automate calculation of coefficients to match different requirements. DuSLICOS also verifies the calculated coefficients. 3.1.2 Additional Functions ...
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Preliminary SLIC-S/-S2 Current Sensor & Offhook Detection TIP Gain Channel A RING V /V Control BAT H switch Logic SLIC-S/-S2 Channel B Current Sensor & Offhook Detection TIP Gain SLIC-S/-S2 RING V /V Control BAT H switch Logic * not ...
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Preliminary 3.2 Block Diagrams Figure 9, Figure 10 and SLIC versions of the DuSLIC chip set. BGND PDRHL PDRH I TO TIP RING PDRHL PDRH VBATL VBATH (Sub) Figure 9 Block Diagram SLIC-S/-S2 (PEB 4264/-2) Data Sheet ...
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Preliminary BGND PDRHL PDRH I TO TIP RING PDRHL PDRH VBATL VBATH (Sub) Figure 10 Block Diagram SLIC-E/-E2 (PEB 4265/-2) Data Sheet PEB 4265/- Off hook ( ...
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Preliminary PDRR PDRRL PDRH PDRHL TIP RING PDRR PDRRL VBATL VBATH VBATR (SUB) Figure 11 Block Diagram SLIC-P (PEB 4266) Data Sheet PEB 4266 ( Off-hook BGND ( 100 ...
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Preliminary Figure 12 shows the internal block structure of all SLICOFI-2x codec versions available. The Enhanced Digital Signal Processor (EDSP) realizing the add-on funtions integrated in the SLICOFI-2 (PEB 3265) device. PEB 3265 / PEB 3264 / PEB 3264-2 CDCNB ...
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Preliminary 3.3 DC Feeding DC feeding with the DuSLIC is fully programmable by using the software coefficients depicted in Table 5 on Page Figure 13 shows the signal paths for DC feeding between the SLIC and SLICOFI-2x: TIP SLIC Channel ...
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Preliminary 3.3.1 DC Characteristic Feeding Zones The DuSLIC DC feeding characteristic has three different zones: the constant current zone, the resistive zone and the constant voltage zone. A voltage reserve V Chapter 3.3.7) can be selected to avoid clipping the ...
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Preliminary 3.3.2 Constant Current Zone In the off-hook state, the feed current must usually be kept at a constant value independent of load (see information to SLICOFI-2x via the IT pin (input pin for DC control). SLICOFI-2x compares the actual ...
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Preliminary 3.3.3 Resistive Zone The programmable resistive zone range of applications. The resistive zone is used for very long lines where the battery is incapable of feeding a constant current into the line. The operating point in this case crosses ...
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Preliminary 3.3.4 Constant Voltage Zone The constant voltage zone (see constant voltage to the line. In this case on the load between the Tip and Ring pin. In the constant voltage zone the external resistors stability and protection define the ...
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Preliminary 3.3.5 Programmable Voltage and Current Range of DC Characteristic The DC characteristic and all symbols are shown in I TIP/RING Figure 18 DC Characteristic Table 5 DC Characteristic Symbol Programmable Range R 1.8 ...
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Preliminary 3.3.6 SLIC Power Dissipation The major portion of the power dissipation in the SLIC can be estimated by the power dissipation in the output stages. The power dissipation can be calculated from – V SLIC BAT ...
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Preliminary 3.3.7 Necessary Voltage Reserve To avoid clipping AC speech signals as well as AC metering pulses, a voltage reserve V (see Figure 14) has to be provided. RES – RES BAT LIM V ...
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Preliminary 3.3.8 Extended Battery Feeding If the battery voltage is not sufficient to supply the minimum required current through the line even in the resistive zone, the auxiliary positive battery voltage can be used to expand the voltage swing between ...
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Preliminary 3.4 AC Transmission Characteristics SLICOFI-2x uses either an IOM PCM digital interface. In receive direction, SLICOFI-2x converts PCM data from the network and outputs a differential analog signal (ACP and ACN) to the SLIC, that amplifies the ...
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Preliminary SLICOFI-2x Channel B ITAC TTX filter Impedance matching ACP ACN Figure 23 Signal Flow in Voice Channel (A) 3.4.1 Transmit Path The current sense signal (ITAC) is converted to a voltage by an external resistor. This voltage is first ...
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Preliminary 3.4.3 Impedance Matching The SLIC outputs the voice signal to the line (receive direction) and also senses the voice signal coming from the subscriber. The AC impedance of the SLIC and the load impedance need to be matched in ...
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Preliminary 3.5 Ringing With the 170 V technology used for the SLIC, a ringing voltage Vrms can be generated on-chip without the need for an external ringing generator. The SLICOFI-2x generates a sinusoidal ringing signal that ...
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Preliminary ringer period. This causes the integration result to represent the DC component of the ring current. If the DC current exceeds the programmed ring trip threshold, SLICOFI-2x generates an interrupt. Ring trip is reliably detected and reported within two ...
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Preliminary 3.5.4 DuSLIC Ringing Options Application requirements differ with regard to ringing amplitudes, power requirements, loop length and loads. The DuSLIC options include three different SLICs to select the most appropriate ringing methods (see Table 6 Ringing Options with SLIC-S, ...
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Preliminary The low-power SLIC-P is optimized for power-critical applications (e.g. intelligent ISDN network termination). Internal ringing can be used Vrms balanced or 50 Vrms unbalanced. For lowest power applications where external ringing is preferred, three different battery ...
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Preliminary E xte lta Figure 26 External Ringing Zero Crossing Synchronization Data Sheet T T ...
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Preliminary 3.5.5 Internal Balanced Ringing via SLICs SLIC-E/-E2 and SLIC-P support internal balanced ringing up to SLIC-S support balanced ringing up to The ringing signal is generated digitally within SLICOFI-2x V DROP,T V DC,RING V DROP,R Figure 27 Balanced Ringing ...
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Preliminary With the DuSLIC ringing voltages Vrms sinusoidal can be applied, but also trapezoidal ringing can be programmed. For a detailed application diagram of internal balanced ringing refer to the chapter on “Application Circuits” (see 3.5.6 Internal ...
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Preliminary In both balanced and unbalanced ringing modes, SLICOFI-2 automatically applies and removes the ringing signal during zero-crossing. This reduces noise and cross-talk to adjacent lines. 3.5.7 External Unbalanced Ringing SLICOFI-2x supports external ringing for higher unbalanced ringing voltage requirements ...
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Preliminary • In Sleep/Power Down mode (PDRx) a similar mechanism is used. In this mode, the internal current sensor of the SLIC is switched off to minimize power consumption. The loop current is therefore fed and sensed through 5 k ...
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Preliminary 3.7 Metering There are two different metering methods: • Metering by sinusoidal bursts with either kHz or • Polarity reversal of Tip and Ring. 3.7.1 Metering by 12/16 kHz Sinusoidal Bursts To satisfy worldwide application requirements, ...
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Preliminary 3.7.2 Metering by Polarity Reversal SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching the REVPOL bit in register BCR1 to one or ...
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Preliminary 3.8 DuSLIC Enhanced Signal Processing Capabilities The signal processing capabilities described in this chapter are realized by an Enhanced Digital Signal Processor (EDSP) except for DTMF generation. Each function can be individually enabled or disabled for each DuSLIC channel. ...
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Preliminary The enhanced Signal Processing Capabilities are available only for the DuSLIC-E/-E2/ -P versions, with an exception of DTMF generation. The DTMF generation is available for all DuSLIC versions. The functions of the EDSP are configured and controlled by POP ...
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Preliminary Table 7 shows the performance characteristics of the DTMF decoder algorithm: Table 7 Performance Characteristics of the DTMF Decoder Algorithm Characteristic 1 Valid input signal detection level 2 Input signal rejection level 3 Positive twist accept 4 Negative twist ...
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Preliminary In the event of pauses < 20 ms: • If the pause is followed by a tone pair with the same frequencies as before, this is interpreted as drop-out. • If the pause is followed by a tone pair ...
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Preliminary DuSLIC FSK Generation Different countries use different standards to send Caller ID information. The DuSLIC chip set is compatible with the widely used standards Bellcore GR-30-CORE, British Telecom (BT) SIN227, SIN242 or the UK Cable Communications Association (CCA) specification ...
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Preliminary Bellcore On-hook Caller ID Physical Layer Transmission First Ring Burst Channel Seizure A B Parameter Header Message Message Parameter 1 Type Length Type Message Header 1 Message length equals the number of bytes to follow in the message body, ...
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Preliminary 3.8.3 Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P) The DuSLIC contains an adaptive line echo cancellation unit for the cancellation of near end echoes. With the adaptive balancing of the LEC unit the Transhybrid Loss can be improved up to ...
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Preliminary If the adaptation of the shadow filter is performed better than the adaption of the actual filter by a value of more than DeltaQ then the shadow filter coefficients will be copied to the actual filter. At the start ...
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Preliminary The UTDR-OK respectively UTDX-OK bit (register INTREG3) will be set if both of the following conditions hold for a time span of at least RTIME without breaks longer than RBRKTime occurring: 1. The in-band signal exceeds a programmable level ...
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Preliminary 3.9 Message Waiting Indication (only DuSLIC-E/-E2/-P) Message Waiting Indication (MWI) is usually performed using a glow lamp at the subscriber phone. Current does not flow through a glow lamp until the voltage reaches a threshold value above approximately 80 ...
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Preliminary To activate the Message Waiting function of DuSLIC the following steps should be performed: • Activating Ring Pause mode by setting the M0-M2 bits • Select Ring Offset RO2 by setting the bits in register LMCR3 • Enable the ...
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Preliminary 3.10 Three-party Conferencing (only DuSLIC-E/-E2/-P) Each DuSLIC channel has a three-party conferencing facility implemented which consist of four PCM registers, adders and gain stages in the microprogram and the corresponding control registers (see This facility is available in PCM/ ...
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Preliminary 3.10.1 Conferencing Modes Table 10 Conference Modes Configuration Registers Mode PCMX CONF -EN -EN PCM Off 0 0 PCM Active 1 0 External 0 0 Conference External 1 0 Conference + PCM Active Internal 0 1 Conference (see also ...
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Preliminary 3.11 16 kHz Mode on PCM Highway In addition to the standard 8 kHz transmission PCM interface modes, there are also two 16 kHz modes for high data transmission performance. Table 11 shows the configuration of PCM channels for ...
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Preliminary • LIN Mode Similar to the PCM mode, but for 16 bit linear data at 8 kHz sample rate via the PCM channels R1, R1L (receive) and X1, X1L (transmit). • PCM16 Mode Mode for higher data transmission rate ...
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Preliminary 4 Operational Description 4.1 Operating Modes for the DuSLIC Chip Set Table 12 Overview of DuSLIC Operating Modes SLICOFI-2x Mode SLIC-S/ SLIC-S2 Sleep (SL) – Power Down PDRH Resistive (PDR) Power Down PDH High Impedance (PDH) Active High ACTH ...
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Preliminary Table 12 Overview of DuSLIC Operating Modes (cont’d) SLICOFI-2x Mode SLIC-S/ SLIC-S2 Ground Start HIT 3) Ring Pause ACTR 1) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 interface) CIOP = Command/Indication Operation For further information see “SLICOFI-2x Command ...
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Preliminary Power Down Resistive (PDRH for SLIC-E/-E2/-S/-S2 and PDRR for SLIC-P) The Power Down Resistive mode is the standard mode for none-active lines. Off-hook is detected by a current value fed to the DSP, compared with a programmable threshold, and ...
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Preliminary Active with HIR HIR is similar to HIT but with the Ring wire set to high impedance. Active with Metering Any available active mode can be used for metering either with Reverse Polarity or with TTX Signals. Ground Start ...
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Preliminary 4.2 Operating Modes for the DuSLIC-S/-S2 Chip Set Table 13 DuSLIC-S/-S2 Operating SLICOFI-2S / SLIC-S / SLICOFI-2S2 SLIC-S2 Mode Mode PDH PDH Power Down PDRH Resistive – PDRHL 1) Active Low ACTL (ACTL) Active High ACTH (ACTH) Active Ring ...
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Preliminary Table 13 DuSLIC-S/-S2 Operating SLICOFI-2S / SLIC-S / SLICOFI-2S2 SLIC-S2 Mode Mode Ring Pause ACTR Active with HIR HIR Active with HIT HIT 1) load ext. C for switching from PDRH to ACTH in on-hook mode V … Tip/Ring ...
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Preliminary 4.3 Operating Modes for the DuSLIC-E/-E2 Chip Set Table 14 DuSLIC-E/-E2 Operating SLICOFI-2 SLIC-E / SLIC-E/-E2 Mode SLIC-E2 Internal Mode Supply Voltages (+/–) [ PDH PDH Open/ Sleep PDRH Open/ Power PDRH Open/ Down Resistive 1) – PDRHL Open/ ...
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Preliminary Table 14 DuSLIC-E/-E2 Operating SLICOFI-2 SLIC-E / SLIC-E/-E2 Mode SLIC-E2 Internal Mode Supply Voltages (+/–) [ Ringing ACTR V HR (Ring) V Ring ACTR HR Pause HIRT HIRT V HR Active with HIR V HR HIR Active with HIT ...
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Preliminary 4.4 Operating Modes for the DuSLIC-P Chip Set Table 15 DuSLIC P Operating SLICOFI-2 SLIC-P SLIC-P Mode Mode Internal Supply Voltages PDH PDH V BATR Sleep PDRH V BATH Sleep PDRR V BATR V Power PDRH ...
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Preliminary Table 15 DuSLIC P Operating SLICOFI-2 SLIC-P SLIC-P Mode Mode Internal Supply Voltages Active ACTR V BATR Ring (ACTR) V Ringing ACTR BATR (Ring) Ringing ROR V BATR (Ring) Ringing ROT V BATR (Ring) Ring ACTR, ...
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Preliminary 4.5 Reset Mode and Reset Behavior 4.5.1 Hardware and Power On Reset A reset of the DuSLIC is initiated by a power-on reset or a hardware reset by setting the signal at RESET input pin to low level for ...
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Preliminary sig µ all I ctiva all ...
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Preliminary 4.5.2 Software Reset When performing a software reset, the DuSLIC is running the reset routine and sets the default settings of the configuration registers. The software reset can be performed individually for each channel. Table 16 Default Values I ...
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Preliminary Table 16 Default Values (cont’d) SRend2 1/512 – DUP 10 ms DUP-IO 16.5 ms SR-Time 80 ms IM-Filter 900 TH-Filter TH – BRD ATTX 2.5 Vrms f 16 kHz TTX TG1 940 Hz ...
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Preliminary 4.6 Interrupt Handling SLICOFI-2x provides much interrupt data for the host system. Interrupt handling is performed by the on chip microprogram which handles the interrupts in a fixed 2 kHz (500 s) frame. Therefore, some delays up to 500 ...
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Preliminary 4.7 Operating Modes and Power Management In many applications, the power dissipated on the line card is a critical parameter. In larger systems, the mean power value (taking into account traffic statistics and line length distribution) determines cooling requirements. ...
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Preliminary – Ringing For SLIC-E/-E2 and SLIC-S, an auxiliary positive supply voltage total supply range 150 V. For SLIC-P the whole supply range is provided The low-impedance line feed ( BATR 101 output impedance) ...
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Preliminary 4.7.3 Power Dissipation of the SLIC The SLIC power dissipation mainly comes from internal bias currents and the buffers output stage (to a lesser extent from the sensor) where additional power is dissipated whenever current is fed to the ...
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Preliminary The most efficient way to reduce short-loop power dissipation is to use a lower battery supply voltage ( V ) whenever line resistance is small enough. This method is BATL supported on the SLIC-E/-E2 by integrating a battery switch. ...
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Preliminary Table 18 shows line currents and output voltages for different operating modes. Table 18 Line Feed Conditions for Power Calculation of SLIC-E/-E2 Operating Mode PDRH, PDRHL ACTL ACTH ACTR extended battery feeding at higher loop length R ( > ...
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Preliminary 1000 900 800 700 600 500 400 300 200 100 0 Figure 41 SLIC-E/-E2 Power Dissipation with Switched Battery Voltage Typical Power Consumption Calculation with SLIC-P (Internal Ringing) Assuming a typical application where the following battery voltages are used: ...
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Preliminary Table 21 SLIC-P PEB 4266 Power Dissipation P Q Operating Mode [mW] PDH 8.8 PDRH 7.7 PDRR 10.4 ACTL 81.7 ACTH 135 ACTR (Extended 383 Battery Feeding) ROR, ROT 263 (Ring Pause) Figure 43 shows the total power dissipation ...
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Preliminary Typical Power Consumption Calculation with SLIC-P (External Ringing) Assuming a typical application where the following battery voltages are used – BATL R teed 600 . L Requirement ...
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Preliminary 350 300 250 200 150 100 50 0 Figure 43 SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops) 4.7.3.4 Ringing Modes Internal Balanced Ringing (SLIC-E/-E2 and SLIC-P) The SLIC-E/-E2/-P internal balanced ringing facility requires a higher supply voltage V ...
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Preliminary The strong influence of the ringer load impedance is demonstrated by the formula for the current sensor power dissipation ( Table 24 and Table 25. The ringer load impedance ...
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Preliminary 4.7.3.5 SLIC Power Consumption Calculation in Ringing Mode The average power consumption for a ringing cadence of 1 second on and 4 seconds off is given TOT, average TOT, Ringing with k = 0.20 ...
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Preliminary – Power Consumption Calculation for SLIC-E/-E2 in Balanced Ringing Mode With the example of the above calculation for SLIC-E/-E2 (see typical ringer load 450 = 3.4 F, required ringing voltage RNG RNG frequency f = ...
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Preliminary – Power Consumption Calculation for SLIC-P in Balanced Ringing Mode With the example of the above calculation with Chapter 4.7.3.3) when the internal ringing feature will be used. R Typical ringer load Vrms and ringing frequency ...
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Preliminary – Power Consumption Calculation for SLIC-P in Unbalanced Ringing Mode A similar power calculation is valid for internal unbalanced ringing mode, which is only available for the SLIC-P. With the following example – ...
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Preliminary 4.8 Integrated Test and Diagnosis Functions (ITDF) 4.8.1 Introduction Subscriber loops are affected by a variety of failures which have to be monitored. Monitoring the loop supposes the access to the subscriber loop and to have test equipment in ...
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Preliminary 4.8.2 Diagnostics The two-channel chip set has a set of signal generators and features implemented to accomplish a variety of diagnostic functions. The SLICOFI-2 device generates all test signals, processes the information that comes back from the SLIC-E/-E2/-P and ...
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Preliminary • TTX metering signal generator (12/16 kHz) Please refer to the CRAM coefficient set and register BCR2 (bits TTX-DIS, TTX-12k) on Page 192. • Ramp generator (used for capacitance measurements) Please refer to the CRAM coefficient set and register ...
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Preliminary 4.8.2.3 Result Register Data Format The result of any measurement can be read via the result registers LMRES1/2. This gives a 16 bit value with LMRES1 being the high and LMRES2 being the low byte. The result is coded ...
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Preliminary Continuous Measurement Sequence (DC Levelmeter Figure 47 Continuous Measurement Sequence (DC Levelmeter) Continuous ...
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Preliminary 4.8.2.5 DC Levelmeter The path of the DC levelmeter is shown in will be determined and prepared depending on certain configuration settings. The selected input signal becomes digitized after pre-filtering and analog-to-digital conversion. The DC levelmeter is selected and ...
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Preliminary CRAM: Address 0x76: LMDC2/LMDC1 Address 0x77: 0/LMDC3 LMDC1, LMDC2 and LMDC3 are 4 bit nibbles which contain K Table 29 K Setting Table INTDC LMDC1 LMDC2 DuSLICOS allows to ...
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Preliminary Table 30 N Setting Table Samples RGF1 RGF2 RGF3 The integration function can be turned on and off by bit LM-EN in register LMCR1. ...
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Preliminary Table 31 Levelmeter Results with and without Integrator Function LM- (without Integrator TRANS Power TRANS Result Down Resistive TRANS Result TRANS any other I LM ...
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Preliminary K Shift Factor (see INTDC K Value of the current divider in power down resistive mode IT,PDR K Value of the current divider for transversal current IT K Value of the current divider for longitudinal current IL R Sense ...
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Preliminary V Mean V = ---------------------------- - Peak 2 V Peak V = --------------- RMS 2 4.8.2.6 AC Levelmeter The AC levelmeter is selected and enabled as shown in Table 32 Selecting AC Levelmeter Path LM-SEL[3: Levelmeter Path ...
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Preliminary Table 33 K Setting Table INTAC LM-AC K INTAC ½ 1/64 7 1/128 The integration function accumulates and sums up the levelmeter values over a set time period. The time period from 1*16 ...
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Preliminary This setting results in a receive gain of 11.88 dB caused by the internal filters. Based on this a factor K (analog to digital) can be defined: AD filter 11. ------------------- - ------------------- - ...
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Preliminary K Constant factor from Digital to Analog DA K Amplification factor of the SLIC AC,SLIC V Voltage at D/A converter refered to digital fullscale DAC Trapez Crestfactor of the trapazoidal signal Output voltage between Tip and Ring ...
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Preliminary 4.8.2.7 Levelmeter Threshold For the levelmeter result a threshold can be set. When the result exceeds the threshold then bit LM-THRES in register INTREG 2 is set to '1 also possible to activate an interrupt when the ...
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Preliminary 4.8.2.8 Current Offset Error Compensation The current offset error caused by the current sensor inside the SLIC-E/-E2/-P can be compensated by programming the compensation registers OFR1 and OFR2 accordingly. The current offset error can be measured with the DC ...
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Preliminary 4.8.2.9 Loop Resistance Measurements The DC loop resistance can be determined by supplying a constant DC voltage V to the Ring- and Tip line and measuring the DC loop current via IT pin. The following steps are necessary to ...
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Preliminary Assumption: • Loop resistance R = 1000 loop • Ring offset RO2 = 60 V (CRAM coefficient set accordingly). Ring offset RO2 is selected by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. The exact value for the Ring ...
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Preliminary eliminates the offsets caused by the SLIC-E/-E2/-P current sensor and the offset caused by the DC voltage output (Ring offset voltage). Differential Resistance Calculation prog I = ---------------------------------------------- - measure normal V – TR prog I = ...
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Preliminary 4.8.2.11 Capacitance Measurements Capacitance measurements with the DuSLIC are accomplished by using the integrated ramp generator function. The ramp generator is capable of applying a voltage ramp to the Ring- and Tip line with the flexibility of: – Programmable ...
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Preliminary S LIC - Line C urrent ...
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Preliminary Example: • Assumptions: – Capacitance as object to be determined: C – Resistor R in series to C Measure – Measure Measure • Calculating parameter values: – Choose Ring Offset voltage 1: RO1 = 70 V ...
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Preliminary • Apply Ring Offset voltage RO2 to Ring and Tip line by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. • Enable the levelmeter by setting bit LM-EN in register LMCR1 to 1. – Comment: The voltage ramp starts ...
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Preliminary Table 36 Measurement Input Selection LM-SEL[3:0] in Measurement Input register LMCR2 1010 Voltage on IO3 1011 Voltage on IO4 1111 Voltage IO4 – IO3 The measurement is accomplished by the DC levelmeter function. FOREIGN VOLTAGE SOURCE AC LINECARD DC ...
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Preliminary --------------------- - FOREIGN INPUT – V (refer to INPUT IOx VCM V = Voltage on pins IOx (e.g. pins IO3, IO4) IOx The resistor directly connected to either Ring or Tip (R1, ...
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Preliminary 4.9 Signal Path and Test Loops The following figures show the main AC and DC signal path and the integrated analog and digital loops of DuSLIC-E/-E2/-P, DuSLIC-S and DuSLIC-S2. Please note the interconnections between the AC and DC pictures ...
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Preliminary LM-SEL[3: IO3 PD-DC-PR IO4 PREFI IO4 – IO3 VDD Offset PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 54 DC Test Loops DuSLIC-E/-E2/-P ...
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Preliminary 4.9.2 Test Loops DuSLIC-S/-S2 The AC test loops for DuSLIC-S since Teletax (TTX) is not available with SLICOFI-2S2. The DC test loops are identical. AC-DLB-32K COX16 a AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 ITAC Adapt. Programmable via ...
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Preliminary AC-DLB-32K COX16 a AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 56 AC Test Loops DuSLIC-S2 Data Sheet LPX FRX LPRX-CR FRX-DIS ...
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Preliminary PD-DC- PREFI PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 57 DC Test Loops DuSLIC-S/-S2 Data Sheet * ...
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Preliminary 4.10 Caller ID Buffer Handling of SLICOFI-2 This chapter intends to describe the handling of the caller ID buffer and the corresponding handshake bits in the interrupt registers. Programming Sequence In order to send a caller ID information over ...
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Preliminary 5 Interfaces The DuSLIC connects the analog subscriber to the digital switching network by two different types of digital interfaces to allow for the highest degree of flexibility in different applications: • PCM interface combined with a serial microcontroller ...
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Preliminary clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by default, the second falling edge is used to buffer the contents of the data line DRA (DRB). FSC PCLK DRA ...
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Preliminary highway assignment for each DuSLIC channel can be programmed. Receive and transmit time slots can also be programmed individually. When DuSLIC is transmitting data on DXA (DXB), pin TCA (TCB) is activated to control an external driving device. The ...
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Preliminary FSC PCLK Bit 7 Time-Slot 0 PCLK Figure 59 Setting of Slopes in Register PCMC1 Data Sheet transmit slope receive slope Single Clock Mode DBL NO- PCMC1: CLK SLOPE SLOPE DRIVE DBL- X- ...
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Preliminary 5.1.2 Control of the Active PCM Channels The SLICOFI-2x offers additional functionality on the PCM interface including three- party conferencing and a 16 kHz sample rate. Five configuration bits control, together with the PCM configuration registers, the activation of ...
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Preliminary 5.1.3 Serial Microcontroller Interface The microcontroller interface consists of four lines: CS, DCLK, DIN and DOUT synchronization signal starting a read or write access to SLICOFI-2x. DCLK A clock signal (up to 8.192 MHz) supplied to SLICOFI-2x. ...
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Preliminary CS DIN Comm 1st Comm 2nd DCLK * DOUT * high impedance Figure 61 Serial Microcontroller Interface Read Access Programming the Microcontroller Interface Without Clocks at FSC, MCLK, PCLK The SLICOFI-2x can also be programmed via the connected to ...
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Preliminary 5.2 The IOM-2 Interface IOM-2 defines an industry-standard serial bus for interconnecting telecommunication ICs for a broad range of applications - typically ISDN-based applications. The IOM-2 bus provides a symmetrical full-duplex communication link containing data, control/programming and status channels. ...
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Preliminary The information is multiplexed into frames, which are transmitted at an 8-kHz rate. The frames are subdivided into 8 sub-frames, with one sub-frame dedicated to each transceiver or pair of codecs (in this case, two SLICOFI-2x channels). The sub-frames ...
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Preliminary FSC DCL 2048 kHz TS0 DD TS0 DU Detail C Detail C FSC DCL DD/DU Bit N Figure 64 IOM-2 Interface Timing (DCL = 2048 kHz, Per 8-kHz Frame) Both DuSLIC channels (see Set the IOM-2 time slot selection ...
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Preliminary 5.2.1 IOM-2 Interface Monitor Transfer Protocol Monitor Channel Operation The monitor channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data are transferred in ...
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Preliminary Monitor Handshake Procedure The monitor channel works in three states – idle state: A pair of inactive (set to ‘1’) MR and MX bits during two or more consecutive frames: End of Message (EOM) – sending state: MX bit ...
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Preliminary MR + MXR Idle MR ° MXR ° RQT st 1 byte MR ° RQT ° RQT th n byte MR ack ° RQT MR wait for ...
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Preliminary Idle ° byte MX rec byte MX ° LL valid new byte Figure 67 State Diagram of the SLICOFI-2x Monitor ...
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Preliminary Address Byte Messages to and from the SLICOFI-2x start with the following byte: Bit 5.2.2 SLICOFI-2x Identification Command (only IOM-2 Interface) In order to unambiguously identify different devices by software, a two-byte identification command is ...
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Preliminary 5.4 SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface The SLIC-S/-S2 PEB 4264/-2 operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 40 SLIC-S/-S2 Interface Code 1) C1 (Pin 18 ...
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Preliminary Active (ACTL, ACTH): These are the regular transmit and receive modes for voice band. The line driving section is operated between Active Ring (ACTR): In order to provide a balanced ring signal Vrms or to ...
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Preliminary Off-hook Current BGND Sensor PDRHL PDRH VHI TIP I T VBI VHI RING PDRHL PDRH VBATL VBAT Switch VBATH VBI (Sub) Figure 68 Interface SLICOFI-2S/-2S2 and SLIC-S/-S2 Capacitor and resistor values ...
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Preliminary 5.5 SLICOFI-2 and SLIC-E/-E2 Interface The SLIC-E/-E2 PEB 4265/-2 operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 42 SLIC-E/-E2 Interface Code “Overtemp” ...
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Preliminary High Impedance (HIR/HIT/HIRT): In this mode each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while the current through the RING output still can be measured IL. ...
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Preliminary Off-hook BGND PDRHL PDRH VHI TIP I T VBI VHI RING PDRHL PDRH VBATL VBAT Switch VBATH VBI (Sub) Figure 69 Interface SLICOFI-2 and SLIC-E/-E2 Capacitor and resistor values are specified ...
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Preliminary 5.6 SLICOFI-2 and SLIC-P Interface The SLIC-P PEB 4266 operates in the following modes controlled by a ternary logic signal at the C1, C2 inputs and a binary logic signal at C3 input: Table 44 SLIC-P Interface Code L ...
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Preliminary Active (ACTL, ACTH): These are the regular transmit and receive modes for voice band. The line driving section is operated between Ringing: Active Ring (ACTR): In order to provide a balanced ring signal Vrms or ...
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Preliminary Active (ACTL, ACTH, ACTR): These are the regular transmit and receive modes for voice band. The line driving section is operated between V . BGND PDRR is a power down mode providing a connection and ...
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Preliminary BGND PDRR PDRRL PDRH PDRHL TIP I RING PDRR PDRH PDRRL PDRHL VBATL Battery VBATH switch VBATR (SUB) Figure 70 Interface SLICOFI-2 and SLIC-P Capacitor and resistor values are specified in ...
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Preliminary 6 SLICOFI-2x Command Structure and Programming With the commands described in this chapter, the SLICOFI-2x can be programmed, configured and tested very flexibly via the microcontroller interface or via the IOM-2 interface monitor channel. The command structure uses one ...
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Preliminary Table 47 M2, M1, M0: General Operating Mode Command/Indication Operation (CIOP ADR[2:0] Channel address for ...
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Preliminary CMD[2: CMD[2: Structure of the Second Command Byte The second command byte specifies a particular SOP, COP or POP command, depending on the CMD[2:0] bits of the first command byte. In ...
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Preliminary 6.1 Overview of Commands SOP STATUS OPERATION Bit 7 6 Byte Byte 2 COP COEFFICIENT OPERATION Bit 7 6 Byte Byte 2 POP POP OPERATION (only SLICOFI-2 PEB 3265 used for DuSLIC-E/-E2/-P) Bit ...
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Preliminary 6.2 SLICOFI-2 Command Structure and Programming This chapter comprises only the SLICOFI-2 PEB 3265 and therefore the DuSLIC-E, DuSLIC-E2 and DuSLIC-P chip sets. 6.2.1 SOP Command The SOP “Status Operation” command provides access to the configuration and status registers ...
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Preliminary 07 INTREG1 H INT-CH HOOK 08 INTREG2 H LM-THRES READY 09 INTREG3 H DTMF-OK 0A INTREG4 H EDSP-FAIL 0 0B CHKR1 H SUM-OK 0C CHKR2 H 0D LMRES1 H 0E LMRES2 H 0F FUSE2 H 10 FUSE3 H 11 ...
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Preliminary 12 IOCTL1 H IO[4:1]-INEN 13 IOCTL2 H IO[4:1]-OEN 14 IOCTL3 H DUP[3:0] 15 BCR1 H HIR HIT 16 BCR2 H REXT-EN SOFT-DIS 17 BCR3 H MU-LAW LIN 18 BCR4 H TH-DIS IM-DIS 19 BCR5 H UTDR-EN UTDX-EN 1A DSCR ...
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Preliminary 1C LMCR1 H TEST-EN LM-EN 1D LMCR2 H LM-NOTCH LM-FILT 1E LMCR3 H AC-SHORT- RTR-SEL EN 1F OFR1 H 20 OFR2 H 21 PCMR1 H R1-HW 22 PCMR2 H R2-HW 23 PCMR3 H R3-HW 24 PCMR4 H R4-HW 25 ...
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Preliminary 26 PCMX2 H X2-HW 27 PCMX3 H X3-HW 28 PCMX4 H X4-HW 29 TSTR1 H PD-AC-PR PD-AC-PO 2A TSTR2 H PD-DC- TSTR3 TSTR4 H OPIM-AN OPIM-4M 2D TSTR5 Data Sheet ...
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Preliminary 6.2.1.2 SOP Register Description 00 REVISION Revision Number (read-only) H Bit 7 6 REV[7:0] Current revision number of the SLICOFI-2. 01 CHIPID 1 Chip Identification 1 (read-only) H Bit CHIPID 2 Chip Identification 2 (read-only) H ...
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Preliminary 05 PCMC1 PCM Configuration Register 1 H Bit 7 6 DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 DBL-CLK Clock mode for the PCM interface (see DBL-CLK = 0 DBL-CLK = 1 X-SLOPE Transmit slope (see X-SLOPE = 0 X-SLOPE = 1 R-SLOPE ...
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Preliminary 06 XCR Extended Configuration Register H Bit 7 6 EDSP- ASYNC EN H-R EDSP-EN Enables the Enhanced Digital Signal Processor EDSP. EDSP- EDSP- ASYNCH-R Enables asynchronous ringing in case of external ringing. ASYNCH ...
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Preliminary 07 INTREG1 Interrupt Register 1 (read-only) H Bit 7 6 INT-CH HOOK INT-CH Interrupt channel bit. This bit indicates that the corresponding channel caused the last interrupt. Will be automatically set to zero after all interrupt registers were read. ...
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Preliminary ICON Constant current information. Filtered by DUP-IO counter and interrupt generation masked by the ICON-M bit. A change of this bit generates an interrupt. ICON = 0 ICON = 1 VRTLIM Exceeding of a programmed voltage threshold for the ...
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Preliminary 08 INTREG2 Interrupt Register 2 (read-only) H Bit 7 6 LM- READY RSTAT THRES After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the default value of INTREG2 is 20h. After reading all four ...
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Preliminary 09 INTREG3 Interrupt Register 3 (read-only) H Bit 7 6 DTMF- OK DTMF-OK Indication of a valid DTMF Key by the DTMF receiver. A change of this bit generates an interrupt. DTMF- DTMF- DTMF-KEY[4:0] Valid ...
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Preliminary Table 48 Valid DTMF Keys (Bit DTMF-KEY4 = 1) (cont’d) f [Hz] f DIGIT LOW HIGH [Hz] 852 1633 C 941 1633 D UTDR-OK Universal Tone Detection Receive (e.g., Fax/Modem tones) UTDR- UTDR- UTDX-OK Universal ...
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Preliminary 0A INTREG4 Interrupt Register 4 (read-only) H Bit 7 6 EDSP- 0 FAIL EDSP-FAIL Indication of a malfunction of the Enhanced Digital Signal Processor EDSP. EDSP-FAIL = 0 Enhanced Digital Signal Processor EDSP normal EDSP-FAIL = 1 Enhanced Digital ...
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Preliminary CIS-REQ Caller ID data request. An interrupt is only generated if the CIS-REQ bit changes from CIS-REQ = 0 CIS-REQ = 1 CIS-ACT Caller ID generator active. This is a status bit only. No interrupt will ...
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Preliminary 0B CHKR1 Checksum Register 1 (High Byte) H (read-only) Bit 7 6 SUM- OK SUM-OK Information about the validity of the checksum. The checksum is valid if the internal checksum calculation is finished. Checksum calculation: SUM- SUM-OK ...
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Preliminary 0D LMRES1 Level Metering Result 1 (High Byte) H (read-only) Bit 7 6 LM-VAL-H[7:0] LM result high byte (selected by the LM-SEL bits in the LMCR2 register) 0E LMRES2 Level Metering Result 2 (Low Byte) H (read-only) Bit 7 ...
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Preliminary 11 MASK Mask Register H Bit 7 6 READY HOOK -M -M The mask bits in the mask register only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit ...
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Preliminary OTEMP-M Mask bit for Thermal Overload Warning OTEMP bit OTEMP OTEMP SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit SYNC SYNC Data Sheet SLICOFI-2x Command Structure and Programming A change of ...
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Preliminary 12 IOCTL1 IO Control Register 1 H Bit 7 6 IO[4:1]-INEN The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers ...
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Preliminary IO2-M Mask bit for IO2-DU bit IO2 IO2 IO1-M Mask bit for IO1-DU bit IO1 IO1 Data Sheet SLICOFI-2x Command Structure and Programming Each change of the IO2 bit generates an ...
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Preliminary 13 IOCTL2 IO Control Register 2 H Bit 7 6 IO[4:1]-OEN IO4-OEN Enabling output driver of the IO4 pin IO4-OEN = 0 IO4-OEN = 1 IO3-OEN Enabling output driver of the IO3 pin IO3-OEN = 0 IO3-OEN = 1 ...
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Preliminary IO2-DD Value for the programmable IO pin IO2 if programmed as an output pin. IO2- IO2- IO1-DD Value for the programmable IO pin IO1 if programmed as an output pin. IO1- IO1-DD = ...
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Preliminary 15 BCR1 Basic Configuration Register 1 H Bit 7 6 HIR HIT HIR This bit modifies different basic modes. In ringing mode an unbalanced ringing on the RING wire (ROR) is enabled. In active mode, high impedance on the ...
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Preliminary ACTR Selection of extended battery feeding in Active mode. Changes also the voltage in Power Down Resistive mode for SLIC-P. In this case V SLIC-P and V HR ACTR = 0 ACTR = 1 ACTL Selection of the low ...
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Preliminary 16 BCR2 Basic Configuration Register 2 H Bit 7 6 REXT- SOFT- EN DIS REXT-EN Enables the use of an external ring signal generator. The synchronization is done via the RSYNC pin and the Ring Burst Enable signal is ...
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Preliminary AC-XGAIN Analog gain in transmit direction (should be set to zero). AC-XGAIN = 0 AC-XGAIN = 1 UTDX-SRC Universal Tone Detector transmit source UTDX-SRC = 0 UTDX-SRC = 1 (see Figure 32 PDOT-DIS Power Down Overtemperature Disable PDOT-DIS = ...
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Preliminary 17 BCR3 Basic Configuration Register 3 H Bit 7 6 MU- LIN LAW MU-LAW Selects the PCM Law MU-LAW = 0 MU-LAW = 1 LIN Voice transmission in a 16-bit linear representation for test purposes. Note: Voice transmission on ...
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Preliminary CONF-EN Selection of three-party conferencing for this channel. The voice data of this channel and the voice data from the corresponding conferencing channels (see Chapter 3.10). CONF- CONF- LPRX-CR Select CRAM coefficients for the filter ...
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Preliminary 18 BCR4 Basic Configuration Register 4 H Bit 7 6 TH-DIS IM-DIS TH-DIS Disables the TH filter. TH-DIS = 0 TH-DIS = 1 IM-DIS Disables the IM filter. IM-DIS = 0 IM-DIS = 1 AX-DIS Disables the AX filter. ...
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Preliminary HPR-DIS Disables the high-pass filter in receive direction. HPR-DIS = 0 HPR-DIS = 1 Data Sheet SLICOFI-2x Command Structure and Programming High-pass filter is enabled. High-pass filter is disabled (H 197 DuSLIC-E/-E2/-P = 1). HPR 2000-07-14 ...
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Preliminary 19 BCR5 Basic Configuration Register 5 H Bit 7 6 UTDR- UTDX UTDR-EN Enables the Universal Tone detection in receive direction. UTDR- Universal Tone detection is disabled. UTDR- Universal Tone detection is enabled. ...
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Preliminary LEC-OUT Line Echo Canceller result for transmit path. LEC-OUT = 0 Line Echo Canceller result used for DTMF only. LEC-OUT = 1 Line Echo Canceller result fed to transmit path. LEC-EN Line Echo Canceller LEC- LEC-EN = ...
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Preliminary 1A DSCR DTMF Sender Configuration Register H Bit 7 6 DG-KEY[3:0] DG-KEY[3:0] Selects one of sixteen DTMF keys generated by the two tone generators. The key will be generated if TG1-EN and TG2-EN are ‘1’. Table 49 DTMF Keys ...